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bgmac: initialize the DMA controller of core rev >= 4

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The DMA controller used in the device supported by GMAC with core rev
>= 4 has some new options which are now set to the default values used
in the Broadcom SDK.

Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Hauke Mehrtens 2014-01-05 01:10:44 +01:00 committed by David S. Miller
parent b2395b8aea
commit 56ceecde1f
2 changed files with 73 additions and 0 deletions
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23
drivers/net/ethernet/broadcom/bgmac.c
View File

@ -96,6 +96,19 @@ static void bgmac_dma_tx_enable(struct bgmac *bgmac,
u32 ctl; u32 ctl;
ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL); ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
if (bgmac->core->id.rev >= 4) {
ctl &= ~BGMAC_DMA_TX_BL_MASK;
ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
ctl &= ~BGMAC_DMA_TX_MR_MASK;
ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
ctl &= ~BGMAC_DMA_TX_PC_MASK;
ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
ctl &= ~BGMAC_DMA_TX_PT_MASK;
ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
}
ctl |= BGMAC_DMA_TX_ENABLE; ctl |= BGMAC_DMA_TX_ENABLE;
ctl |= BGMAC_DMA_TX_PARITY_DISABLE; ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl); bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
@ -240,6 +253,16 @@ static void bgmac_dma_rx_enable(struct bgmac *bgmac,
u32 ctl; u32 ctl;
ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL); ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
if (bgmac->core->id.rev >= 4) {
ctl &= ~BGMAC_DMA_RX_BL_MASK;
ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
ctl &= ~BGMAC_DMA_RX_PC_MASK;
ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
ctl &= ~BGMAC_DMA_RX_PT_MASK;
ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
}
ctl &= BGMAC_DMA_RX_ADDREXT_MASK; ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
ctl |= BGMAC_DMA_RX_ENABLE; ctl |= BGMAC_DMA_RX_ENABLE;
ctl |= BGMAC_DMA_RX_PARITY_DISABLE; ctl |= BGMAC_DMA_RX_PARITY_DISABLE;

50
drivers/net/ethernet/broadcom/bgmac.h
View File

@ -237,9 +237,34 @@
#define BGMAC_DMA_TX_SUSPEND 0x00000002 #define BGMAC_DMA_TX_SUSPEND 0x00000002
#define BGMAC_DMA_TX_LOOPBACK 0x00000004 #define BGMAC_DMA_TX_LOOPBACK 0x00000004
#define BGMAC_DMA_TX_FLUSH 0x00000010 #define BGMAC_DMA_TX_FLUSH 0x00000010
#define BGMAC_DMA_TX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
#define BGMAC_DMA_TX_MR_SHIFT 6
#define BGMAC_DMA_TX_MR_1 0
#define BGMAC_DMA_TX_MR_2 1
#define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800 #define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800
#define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000 #define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000
#define BGMAC_DMA_TX_ADDREXT_SHIFT 16 #define BGMAC_DMA_TX_ADDREXT_SHIFT 16
#define BGMAC_DMA_TX_BL_MASK 0x001C0000 /* BurstLen bits */
#define BGMAC_DMA_TX_BL_SHIFT 18
#define BGMAC_DMA_TX_BL_16 0
#define BGMAC_DMA_TX_BL_32 1
#define BGMAC_DMA_TX_BL_64 2
#define BGMAC_DMA_TX_BL_128 3
#define BGMAC_DMA_TX_BL_256 4
#define BGMAC_DMA_TX_BL_512 5
#define BGMAC_DMA_TX_BL_1024 6
#define BGMAC_DMA_TX_PC_MASK 0x00E00000 /* Prefetch control */
#define BGMAC_DMA_TX_PC_SHIFT 21
#define BGMAC_DMA_TX_PC_0 0
#define BGMAC_DMA_TX_PC_4 1
#define BGMAC_DMA_TX_PC_8 2
#define BGMAC_DMA_TX_PC_16 3
#define BGMAC_DMA_TX_PT_MASK 0x03000000 /* Prefetch threshold */
#define BGMAC_DMA_TX_PT_SHIFT 24
#define BGMAC_DMA_TX_PT_1 0
#define BGMAC_DMA_TX_PT_2 1
#define BGMAC_DMA_TX_PT_4 2
#define BGMAC_DMA_TX_PT_8 3
#define BGMAC_DMA_TX_INDEX 0x04 #define BGMAC_DMA_TX_INDEX 0x04
#define BGMAC_DMA_TX_RINGLO 0x08 #define BGMAC_DMA_TX_RINGLO 0x08
#define BGMAC_DMA_TX_RINGHI 0x0C #define BGMAC_DMA_TX_RINGHI 0x0C
@ -267,8 +292,33 @@
#define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100 #define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100
#define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400 #define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400
#define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800 #define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800
#define BGMAC_DMA_RX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
#define BGMAC_DMA_RX_MR_SHIFT 6
#define BGMAC_DMA_TX_MR_1 0
#define BGMAC_DMA_TX_MR_2 1
#define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000 #define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000
#define BGMAC_DMA_RX_ADDREXT_SHIFT 16 #define BGMAC_DMA_RX_ADDREXT_SHIFT 16
#define BGMAC_DMA_RX_BL_MASK 0x001C0000 /* BurstLen bits */
#define BGMAC_DMA_RX_BL_SHIFT 18
#define BGMAC_DMA_RX_BL_16 0
#define BGMAC_DMA_RX_BL_32 1
#define BGMAC_DMA_RX_BL_64 2
#define BGMAC_DMA_RX_BL_128 3
#define BGMAC_DMA_RX_BL_256 4
#define BGMAC_DMA_RX_BL_512 5
#define BGMAC_DMA_RX_BL_1024 6
#define BGMAC_DMA_RX_PC_MASK 0x00E00000 /* Prefetch control */
#define BGMAC_DMA_RX_PC_SHIFT 21
#define BGMAC_DMA_RX_PC_0 0
#define BGMAC_DMA_RX_PC_4 1
#define BGMAC_DMA_RX_PC_8 2
#define BGMAC_DMA_RX_PC_16 3
#define BGMAC_DMA_RX_PT_MASK 0x03000000 /* Prefetch threshold */
#define BGMAC_DMA_RX_PT_SHIFT 24
#define BGMAC_DMA_RX_PT_1 0
#define BGMAC_DMA_RX_PT_2 1
#define BGMAC_DMA_RX_PT_4 2
#define BGMAC_DMA_RX_PT_8 3
#define BGMAC_DMA_RX_INDEX 0x24 #define BGMAC_DMA_RX_INDEX 0x24
#define BGMAC_DMA_RX_RINGLO 0x28 #define BGMAC_DMA_RX_RINGLO 0x28
#define BGMAC_DMA_RX_RINGHI 0x2C #define BGMAC_DMA_RX_RINGHI 0x2C