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spi: cadence-qspi: minimise register accesses on each op if !DTR

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cqspi_enable_dtr() is called for each operation, commands or not, reads
or writes. It writes CQSPI_REG_CONFIG then waits for idle (three
successful reads). Skip that in the no-DTR case if DTR is already
disabled.

It cannot be skipped in the DTR case as cqspi_setup_opcode_ext() writes
to a register and we must wait for idle state.

According to ftrace, the average cqspi_exec_mem_op() call goes from
85.4µs to 83.6µs when reading 235M over UBIFS on an octal flash.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://msgid.link/r/20240405-cdns-qspi-mbly-v2-6-956679866d6d@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Théo Lebrun 2024-04-05 17:02:16 +02:00 committed by Mark Brown
parent dcc594aef1
commit 563f8598cb
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GPG Key ID: 24D68B725D5487D0
1 changed files with 5 additions and 2 deletions
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7
drivers/spi/spi-cadence-quadspi.c
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@ -491,8 +491,11 @@ static int cqspi_enable_dtr(struct cqspi_flash_pdata *f_pdata,
if (ret)
return ret;
} else {
reg &= ~CQSPI_REG_CONFIG_DTR_PROTO;
reg &= ~CQSPI_REG_CONFIG_DUAL_OPCODE;
unsigned int mask = CQSPI_REG_CONFIG_DTR_PROTO | CQSPI_REG_CONFIG_DUAL_OPCODE;
/* Shortcut if DTR is already disabled. */
if ((reg & mask) == 0)
return 0;
reg &= ~mask;
}
writel(reg, reg_base + CQSPI_REG_CONFIG);