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arm64: perf: Expose some new events via sysfs
Some new PMU events can been detected by PMCEID1_EL0, but it can't be listed, Let's expose these through sysfs. Signed-off-by: Shaokun Zhang <zhangshaokun@hisilicon.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Link: https://lore.kernel.org/r/1595328573-12751-2-git-send-email-zhangshaokun@hisilicon.com Signed-off-by: Will Deacon <will@kernel.org>
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@ -72,6 +72,13 @@
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#define ARMV8_PMUV3_PERFCTR_LL_CACHE_RD 0x36
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#define ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD 0x37
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#define ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD 0x38
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#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD 0x39
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#define ARMV8_PMUV3_PERFCTR_OP_RETIRED 0x3A
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#define ARMV8_PMUV3_PERFCTR_OP_SPEC 0x3B
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#define ARMV8_PMUV3_PERFCTR_STALL 0x3C
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#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND 0x3D
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#define ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND 0x3E
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#define ARMV8_PMUV3_PERFCTR_STALL_SLOT 0x3F
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/* Statistical profiling extension microarchitectural events */
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#define ARMV8_SPE_PERFCTR_SAMPLE_POP 0x4000
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@ -79,6 +86,26 @@
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#define ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE 0x4002
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#define ARMV8_SPE_PERFCTR_SAMPLE_COLLISION 0x4003
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/* AMUv1 architecture events */
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#define ARMV8_AMU_PERFCTR_CNT_CYCLES 0x4004
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#define ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM 0x4005
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/* long-latency read miss events */
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#define ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS 0x4006
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#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD 0x4009
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#define ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS 0x400A
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#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD 0x400B
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/* additional latency from alignment events */
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#define ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT 0x4020
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#define ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT 0x4021
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#define ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT 0x4022
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/* Armv8.5 Memory Tagging Extension events */
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#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED 0x4024
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#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD 0x4025
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#define ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR 0x4026
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/* ARMv8 recommended implementation defined event types */
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD 0x40
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#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR 0x41
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@ -225,10 +225,29 @@ static struct attribute *armv8_pmuv3_event_attrs[] = {
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ARMV8_EVENT_ATTR(ll_cache_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_RD),
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ARMV8_EVENT_ATTR(ll_cache_miss_rd, ARMV8_PMUV3_PERFCTR_LL_CACHE_MISS_RD),
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ARMV8_EVENT_ATTR(remote_access_rd, ARMV8_PMUV3_PERFCTR_REMOTE_ACCESS_RD),
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ARMV8_EVENT_ATTR(l1d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L1D_CACHE_LMISS_RD),
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ARMV8_EVENT_ATTR(op_retired, ARMV8_PMUV3_PERFCTR_OP_RETIRED),
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ARMV8_EVENT_ATTR(op_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC),
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ARMV8_EVENT_ATTR(stall, ARMV8_PMUV3_PERFCTR_STALL),
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ARMV8_EVENT_ATTR(stall_slot_backend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_BACKEND),
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ARMV8_EVENT_ATTR(stall_slot_frontend, ARMV8_PMUV3_PERFCTR_STALL_SLOT_FRONTEND),
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ARMV8_EVENT_ATTR(stall_slot, ARMV8_PMUV3_PERFCTR_STALL_SLOT),
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ARMV8_EVENT_ATTR(sample_pop, ARMV8_SPE_PERFCTR_SAMPLE_POP),
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ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED),
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ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE),
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ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION),
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ARMV8_EVENT_ATTR(cnt_cycles, ARMV8_AMU_PERFCTR_CNT_CYCLES),
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ARMV8_EVENT_ATTR(stall_backend_mem, ARMV8_AMU_PERFCTR_STALL_BACKEND_MEM),
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ARMV8_EVENT_ATTR(l1i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L1I_CACHE_LMISS),
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ARMV8_EVENT_ATTR(l2d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L2D_CACHE_LMISS_RD),
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ARMV8_EVENT_ATTR(l2i_cache_lmiss, ARMV8_PMUV3_PERFCTR_L2I_CACHE_LMISS),
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ARMV8_EVENT_ATTR(l3d_cache_lmiss_rd, ARMV8_PMUV3_PERFCTR_L3D_CACHE_LMISS_RD),
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ARMV8_EVENT_ATTR(ldst_align_lat, ARMV8_PMUV3_PERFCTR_LDST_ALIGN_LAT),
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ARMV8_EVENT_ATTR(ld_align_lat, ARMV8_PMUV3_PERFCTR_LD_ALIGN_LAT),
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ARMV8_EVENT_ATTR(st_align_lat, ARMV8_PMUV3_PERFCTR_ST_ALIGN_LAT),
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ARMV8_EVENT_ATTR(mem_access_checked, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED),
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ARMV8_EVENT_ATTR(mem_access_checked_rd, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_RD),
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ARMV8_EVENT_ATTR(mem_access_checked_wr, ARMV8_MTE_PERFCTR_MEM_ACCESS_CHECKED_WR),
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NULL,
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};
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