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arm64: ZynqMP DT changes for 6.8

Browse Source 
- Fix overlay rules to remove KR260 targets
 - Move ethernet phys to mdio node
 - Fix couple of issues reported by W=1
  - Do not use _ in node names
  - Use lowercase in register address
  - Remove address/size-cells from nodes without child
  - Moved fixed clock to root on KV260
 - Fix issues reported by dt-schema
  - additional compatible string for qspi on SOM
 - Move arm/xilinx.yaml to soc vendor to cover also other archs
 - Describe new Microblaze V qemu platform
 - Add missing mailbox destination compatible string
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Merge tag 'zynqmp-dt-for-6.8' of https://github.com/Xilinx/linux-xlnx into soc/dt

arm64: ZynqMP DT changes for 6.8

- Fix overlay rules to remove KR260 targets
- Move ethernet phys to mdio node
- Fix couple of issues reported by W=1
 - Do not use _ in node names
 - Use lowercase in register address
 - Remove address/size-cells from nodes without child
 - Moved fixed clock to root on KV260
- Fix issues reported by dt-schema
 - additional compatible string for qspi on SOM
- Move arm/xilinx.yaml to soc vendor to cover also other archs
- Describe new Microblaze V qemu platform
- Add missing mailbox destination compatible string

* tag 'zynqmp-dt-for-6.8' of https://github.com/Xilinx/linux-xlnx:
  arm64: zynqmp: Add missing destination mailbox compatible
  arm64: zynqmp: Fix clock node name in kv260 cards
  arm64: zynqmp: Move fixed clock to / for kv260
  dt-bindings: soc: Add new board description for MicroBlaze V
  dt-bindings: soc: xilinx: Move xilinx.yaml from arm to soc
  arm64: xilinx: Remove address/size-cells from gem nodes
  arm64: xilinx: Remove address/size-cells from flash node
  arm64: xilinx: Put ethernet phys to mdio node
  arm64: xilinx: Remove mt25qu512a compatible string from SOM
  arm64: xilinx: Use lower case for partition address
  arm64: xilinx: Do not use '_' in DT node names
  arm64: dts: xilinx: Apply overlays to base dtbs

Link: https://lore.kernel.org/r/CAHTX3dLyA1Y9guLKSNJTChFVvkspMfTa0odULyAdcuFUSiSH3A@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-12-21 16:47:31 +00:00
commit 55bfefaabd
13 changed files with 139 additions and 123 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
Documentation/devicetree/bindings/arm/xilinx.yaml → Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/xilinx.yaml#
$id: http://devicetree.org/schemas/soc/xilinx/xilinx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx Zynq Platforms
@ -132,6 +132,11 @@ properties:
- const: xlnx,zynqmp-smk-k26
- const: xlnx,zynqmp
- description: AMD MicroBlaze V (QEMU)
items:
- const: qemu,mbv
- const: amd,mbv
additionalProperties: true
...

1
MAINTAINERS
View File

@ -3020,6 +3020,7 @@ F: Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml
F: Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml
F: Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
F: Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml
F: Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
F: Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml
F: arch/arm/mach-zynq/
F: drivers/clocksource/timer-cadence-ttc.c

9
arch/arm64/boot/dts/xilinx/Makefile
View File

@ -22,11 +22,10 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA.dtb
zynqmp-sm-k26-revA-sck-kv-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kv-g-revA.dtb
zynqmp-sm-k26-revA-sck-kv-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-sm-k26-revA-sck-kv-g-revB.dtb
zynqmp-smk-k26-revA-sck-kv-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revA.dtbo
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revA.dtb
zynqmp-smk-k26-revA-sck-kv-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kv-g-revB.dtbo
zynqmp-sm-k26-revA-sck-kr-g-revA-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo
zynqmp-sm-k26-revA-sck-kr-g-revB-dtbs := zynqmp-sm-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo
zynqmp-smk-k26-revA-sck-kr-g-revA-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revA.dtbo
zynqmp-smk-k26-revA-sck-kr-g-revB-dtbs := zynqmp-smk-k26-revA.dtb zynqmp-sck-kr-g-revB.dtbo
dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-smk-k26-revA-sck-kv-g-revB.dtb

76
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
View File

@ -21,6 +21,44 @@
/dts-v1/;
/plugin/;
&{/} {
si5332_0: si5332-0 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
si5332_1: si5332-1 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
si5332_2: si5332-2 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
si5332_3: si5332-3 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
si5332_4: si5332-4 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
si5332_5: si5332-5 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
#address-cells = <1>;
#size-cells = <0>;
@ -34,44 +72,6 @@
/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
};
&amba {
si5332_0: si5332_0 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
si5332_1: si5332_1 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
si5332_2: si5332_2 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
si5332_3: si5332_3 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
si5332_4: si5332_4 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
si5332_5: si5332_5 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
/* DP/USB 3.0 and SATA */
&psgtr {
status = "okay";

76
arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso
View File

@ -16,6 +16,44 @@
/dts-v1/;
/plugin/;
&{/} {
si5332_0: si5332-0 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
si5332_1: si5332-1 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
si5332_2: si5332-2 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
si5332_3: si5332-3 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
si5332_4: si5332-4 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
si5332_5: si5332-5 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
#address-cells = <1>;
#size-cells = <0>;
@ -30,44 +68,6 @@
/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
};
&amba {
si5332_0: si5332_0 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
si5332_1: si5332_1 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
si5332_2: si5332_2 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
si5332_3: si5332_3 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
};
si5332_4: si5332_4 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
si5332_5: si5332_5 { /* u17 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
};
};
/* DP/USB 3.0 */
&psgtr {
status = "okay";

8
arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts
View File

@ -131,9 +131,7 @@
&qspi { /* MIO 0-5 - U143 */
status = "okay";
spi_flash: flash@0 { /* MT25QU512A */
compatible = "mt25qu512a", "jedec,spi-nor"; /* 64MB */
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor"; /* 64MB */
reg = <0>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
@ -222,9 +220,9 @@
label = "Secure OS Storage";
reg = <0x2280000 0x20000>; /* 128KB */
};
partition@22A0000 {
partition@22a0000 {
label = "User";
reg = <0x22A0000 0x1d60000>; /* 29.375 MB */
reg = <0x22a0000 0x1d60000>; /* 29.375 MB */
};
};
};

8
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts
View File

@ -98,8 +98,12 @@
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem3_default>;
phy0: ethernet-phy@0 {
reg = <0>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};

16
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts
View File

@ -91,12 +91,16 @@
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem2_default>;
phy0: ethernet-phy@5 {
reg = <5>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@5 {
reg = <5>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
ti,dp83867-rxctrl-strap-quirk;
};
};
};

8
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dts
View File

@ -88,8 +88,12 @@
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
phy0: ethernet-phy@0 { /* VSC8211 */
reg = <0>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 { /* VSC8211 */
reg = <0>;
};
};
};

26
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dts
View File

@ -116,17 +116,21 @@
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy0>;
ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
reg = <0>;
};
ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
reg = <7>;
};
ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
reg = <3>;
};
ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
reg = <8>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
reg = <0>;
};
ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
reg = <7>;
};
ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
reg = <3>;
};
ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
reg = <8>;
};
};
};

8
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dts
View File

@ -77,8 +77,12 @@
phy-mode = "rgmii-id";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem1_default>;
phy0: ethernet-phy@0 {
reg = <0>;
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
reg = <0>;
};
};
};

4
arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts
View File

@ -123,13 +123,13 @@
io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
};
si5335_0: si5335_0 { /* clk0_usb - u23 */
si5335_0: si5335-0 { /* clk0_usb - u23 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
si5335_1: si5335_1 { /* clk1_dp - u23 */
si5335_1: si5335-1 { /* clk1_dp - u23 */
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;

15
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
View File

@ -129,7 +129,7 @@
};
};
zynqmp_ipi: zynqmp_ipi {
zynqmp_ipi: zynqmp-ipi {
bootph-all;
compatible = "xlnx,zynqmp-ipi-mailbox";
interrupt-parent = <&gic>;
@ -141,6 +141,7 @@
ipi_mailbox_pmu1: mailbox@ff9905c0 {
bootph-all;
compatible = "xlnx,zynqmp-ipi-dest-mailbox";
reg = <0x0 0xff9905c0 0x0 0x20>,
<0x0 0xff9905e0 0x0 0x20>,
<0x0 0xff990e80 0x0 0x20>,
@ -194,12 +195,12 @@
mbox-names = "tx", "rx";
};
nvmem_firmware {
nvmem-firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;
#size-cells = <1>;
soc_revision: soc_revision@0 {
soc_revision: soc-revision@0 {
reg = <0x0 0x4>;
};
};
@ -584,8 +585,6 @@
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0b0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <1>;
#size-cells = <0>;
iommus = <&smmu 0x874>;
power-domains = <&zynqmp_firmware PD_ETH_0>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>;
@ -600,8 +599,6 @@
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0c0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <1>;
#size-cells = <0>;
iommus = <&smmu 0x875>;
power-domains = <&zynqmp_firmware PD_ETH_1>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>;
@ -616,8 +613,6 @@
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0d0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <1>;
#size-cells = <0>;
iommus = <&smmu 0x876>;
power-domains = <&zynqmp_firmware PD_ETH_2>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>;
@ -632,8 +627,6 @@
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xff0e0000 0x0 0x1000>;
clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
#address-cells = <1>;
#size-cells = <0>;
iommus = <&smmu 0x877>;
power-domains = <&zynqmp_firmware PD_ETH_3>;
resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>;