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drm/msm: Clean up GMU OOB set/clear handling.
Now that the bug is fixed in the minimal way for stable, go make the code table-driven. Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Eric Anholt
Rob Clark
parent
5f98b33b04
commit
555c50a4a1
@ -245,47 +245,66 @@ static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu)
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return ret;
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}
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struct a6xx_gmu_oob_bits {
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int set, ack, set_new, ack_new;
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const char *name;
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};
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/* These are the interrupt / ack bits for each OOB request that are set
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* in a6xx_gmu_set_oob and a6xx_clear_oob
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*/
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static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = {
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[GMU_OOB_GPU_SET] = {
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.name = "GPU_SET",
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.set = 16,
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.ack = 24,
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.set_new = 30,
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.ack_new = 31,
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},
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[GMU_OOB_PERFCOUNTER_SET] = {
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.name = "PERFCOUNTER",
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.set = 17,
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.ack = 25,
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.set_new = 28,
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.ack_new = 30,
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},
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[GMU_OOB_BOOT_SLUMBER] = {
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.name = "BOOT_SLUMBER",
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.set = 22,
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.ack = 30,
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},
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[GMU_OOB_DCVS_SET] = {
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.name = "GPU_DCVS",
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.set = 23,
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.ack = 31,
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},
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};
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/* Trigger a OOB (out of band) request to the GMU */
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int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
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{
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int ret;
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u32 val;
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int request, ack;
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const char *name;
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switch (state) {
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case GMU_OOB_GPU_SET:
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if (gmu->legacy) {
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request = GMU_OOB_GPU_SET_REQUEST;
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ack = GMU_OOB_GPU_SET_ACK;
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} else {
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request = GMU_OOB_GPU_SET_REQUEST_NEW;
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ack = GMU_OOB_GPU_SET_ACK_NEW;
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}
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name = "GPU_SET";
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break;
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case GMU_OOB_PERFCOUNTER_SET:
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if (gmu->legacy) {
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request = GMU_OOB_PERFCOUNTER_REQUEST;
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ack = GMU_OOB_PERFCOUNTER_ACK;
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} else {
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request = GMU_OOB_PERFCOUNTER_REQUEST_NEW;
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ack = GMU_OOB_PERFCOUNTER_ACK_NEW;
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}
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name = "PERFCOUNTER";
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break;
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case GMU_OOB_BOOT_SLUMBER:
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request = GMU_OOB_BOOT_SLUMBER_REQUEST;
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ack = GMU_OOB_BOOT_SLUMBER_ACK;
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name = "BOOT_SLUMBER";
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break;
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case GMU_OOB_DCVS_SET:
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request = GMU_OOB_DCVS_REQUEST;
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ack = GMU_OOB_DCVS_ACK;
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name = "GPU_DCVS";
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break;
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default:
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if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
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return -EINVAL;
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if (gmu->legacy) {
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request = a6xx_gmu_oob_bits[state].set;
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ack = a6xx_gmu_oob_bits[state].ack;
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} else {
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request = a6xx_gmu_oob_bits[state].set_new;
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ack = a6xx_gmu_oob_bits[state].ack_new;
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if (!request || !ack) {
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DRM_DEV_ERROR(gmu->dev,
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"Invalid non-legacy GMU request %s\n",
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a6xx_gmu_oob_bits[state].name);
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return -EINVAL;
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}
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}
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/* Trigger the equested OOB operation */
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@ -298,7 +317,7 @@ int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
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if (ret)
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DRM_DEV_ERROR(gmu->dev,
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"Timeout waiting for GMU OOB set %s: 0x%x\n",
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name,
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a6xx_gmu_oob_bits[state].name,
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gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO));
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/* Clear the acknowledge interrupt */
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@ -310,36 +329,17 @@ int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
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/* Clear a pending OOB state in the GMU */
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void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
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{
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if (!gmu->legacy) {
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if (state == GMU_OOB_GPU_SET) {
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gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
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1 << GMU_OOB_GPU_SET_CLEAR_NEW);
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} else {
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WARN_ON(state != GMU_OOB_PERFCOUNTER_SET);
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gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
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1 << GMU_OOB_PERFCOUNTER_CLEAR_NEW);
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}
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return;
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}
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int bit;
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switch (state) {
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case GMU_OOB_GPU_SET:
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gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
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1 << GMU_OOB_GPU_SET_CLEAR);
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break;
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case GMU_OOB_PERFCOUNTER_SET:
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gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
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1 << GMU_OOB_PERFCOUNTER_CLEAR);
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break;
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case GMU_OOB_BOOT_SLUMBER:
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gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
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1 << GMU_OOB_BOOT_SLUMBER_CLEAR);
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break;
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case GMU_OOB_DCVS_SET:
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gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET,
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1 << GMU_OOB_DCVS_CLEAR);
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break;
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}
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if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
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return;
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if (gmu->legacy)
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bit = a6xx_gmu_oob_bits[state].ack;
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else
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bit = a6xx_gmu_oob_bits[state].ack_new;
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gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, bit);
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}
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/* Enable CPU control of SPTP power power collapse */
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@ -153,52 +153,27 @@ static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value)
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*/
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enum a6xx_gmu_oob_state {
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/*
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* Let the GMU know that a boot or slumber operation has started. The value in
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* REG_A6XX_GMU_BOOT_SLUMBER_OPTION lets the GMU know which operation we are
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* doing
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*/
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GMU_OOB_BOOT_SLUMBER = 0,
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/*
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* Let the GMU know to not turn off any GPU registers while the CPU is in a
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* critical section
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*/
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GMU_OOB_GPU_SET,
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/*
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* Set a new power level for the GPU when the CPU is doing frequency scaling
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*/
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GMU_OOB_DCVS_SET,
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/*
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* Used to keep the GPU on for CPU-side reads of performance counters.
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*/
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GMU_OOB_PERFCOUNTER_SET,
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};
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/* These are the interrupt / ack bits for each OOB request that are set
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* in a6xx_gmu_set_oob and a6xx_clear_oob
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*/
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/*
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* Let the GMU know that a boot or slumber operation has started. The value in
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* REG_A6XX_GMU_BOOT_SLUMBER_OPTION lets the GMU know which operation we are
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* doing
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*/
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#define GMU_OOB_BOOT_SLUMBER_REQUEST 22
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#define GMU_OOB_BOOT_SLUMBER_ACK 30
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#define GMU_OOB_BOOT_SLUMBER_CLEAR 30
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/*
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* Set a new power level for the GPU when the CPU is doing frequency scaling
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*/
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#define GMU_OOB_DCVS_REQUEST 23
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#define GMU_OOB_DCVS_ACK 31
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#define GMU_OOB_DCVS_CLEAR 31
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/*
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* Let the GMU know to not turn off any GPU registers while the CPU is in a
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* critical section
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*/
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#define GMU_OOB_GPU_SET_REQUEST 16
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#define GMU_OOB_GPU_SET_ACK 24
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#define GMU_OOB_GPU_SET_CLEAR 24
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#define GMU_OOB_GPU_SET_REQUEST_NEW 30
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#define GMU_OOB_GPU_SET_ACK_NEW 31
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#define GMU_OOB_GPU_SET_CLEAR_NEW 31
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#define GMU_OOB_PERFCOUNTER_REQUEST 17
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#define GMU_OOB_PERFCOUNTER_ACK 25
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#define GMU_OOB_PERFCOUNTER_CLEAR 25
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#define GMU_OOB_PERFCOUNTER_REQUEST_NEW 28
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#define GMU_OOB_PERFCOUNTER_ACK_NEW 30
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#define GMU_OOB_PERFCOUNTER_CLEAR_NEW 30
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void a6xx_hfi_init(struct a6xx_gmu *gmu);
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int a6xx_hfi_start(struct a6xx_gmu *gmu, int boot_state);
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void a6xx_hfi_stop(struct a6xx_gmu *gmu);
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