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drm/radeon/kms: clean up radeon_asic struct (v2)
v2: fix typo. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König<christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
parent
9e6f3d02c4
commit
54e88e065e
@ -1133,12 +1133,23 @@ struct radeon_asic {
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void (*vga_set_state)(struct radeon_device *rdev, bool state);
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bool (*gpu_is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp);
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int (*asic_reset)(struct radeon_device *rdev);
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/* ioctl hw specific callback. Some hw might want to perform special
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* operation on specific ioctl. For instance on wait idle some hw
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* might want to perform and HDP flush through MMIO as it seems that
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* some R6XX/R7XX hw doesn't take HDP flush into account if programmed
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* through ring.
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*/
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void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
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/* check if 3D engine is idle */
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bool (*gui_idle)(struct radeon_device *rdev);
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/* wait for mc_idle */
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int (*mc_wait_for_idle)(struct radeon_device *rdev);
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/* gart */
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struct {
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void (*tlb_flush)(struct radeon_device *rdev);
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int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr);
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} gart;
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/* ring specific callbacks */
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struct {
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void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
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int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib);
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@ -1150,12 +1161,12 @@ struct radeon_asic {
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int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
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int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp);
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} ring[RADEON_NUM_RINGS];
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/* irqs */
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struct {
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int (*set)(struct radeon_device *rdev);
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int (*process)(struct radeon_device *rdev);
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} irq;
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/* displays */
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struct {
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/* display watermarks */
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void (*bandwidth_update)(struct radeon_device *rdev);
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@ -1164,7 +1175,7 @@ struct radeon_asic {
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/* wait for vblank */
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void (*wait_for_vblank)(struct radeon_device *rdev, int crtc);
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} display;
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/* copy functions for bo handling */
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struct {
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int (*blit)(struct radeon_device *rdev,
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uint64_t src_offset,
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@ -1187,30 +1198,20 @@ struct radeon_asic {
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/* ring used for bo copies */
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u32 copy_ring_index;
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} copy;
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/* surfaces */
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struct {
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int (*set_reg)(struct radeon_device *rdev, int reg,
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uint32_t tiling_flags, uint32_t pitch,
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uint32_t offset, uint32_t obj_size);
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void (*clear_reg)(struct radeon_device *rdev, int reg);
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} surface;
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/* hotplug detect */
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struct {
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void (*init)(struct radeon_device *rdev);
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void (*fini)(struct radeon_device *rdev);
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bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
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void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
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} hpd;
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/* ioctl hw specific callback. Some hw might want to perform special
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* operation on specific ioctl. For instance on wait idle some hw
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* might want to perform and HDP flush through MMIO as it seems that
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* some R6XX/R7XX hw doesn't take HDP flush into account if programmed
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* through ring.
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*/
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void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
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/* check if 3D engine is idle */
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bool (*gui_idle)(struct radeon_device *rdev);
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/* power management */
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struct {
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void (*misc)(struct radeon_device *rdev);
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@ -1232,9 +1233,6 @@ struct radeon_asic {
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u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
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void (*post_page_flip)(struct radeon_device *rdev, int crtc);
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} pflip;
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/* wait for mc_idle */
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int (*mc_wait_for_idle)(struct radeon_device *rdev);
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};
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/*
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@ -136,6 +136,9 @@ static struct radeon_asic r100_asic = {
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.vga_set_state = &r100_vga_set_state,
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.gpu_is_lockup = &r100_gpu_is_lockup,
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.asic_reset = &r100_asic_reset,
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.ioctl_wait_idle = NULL,
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.gui_idle = &r100_gui_idle,
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.mc_wait_for_idle = &r100_mc_wait_for_idle,
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.gart = {
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.tlb_flush = &r100_pci_gart_tlb_flush,
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.set_page = &r100_pci_gart_set_page,
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@ -178,8 +181,6 @@ static struct radeon_asic r100_asic = {
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.sense = &r100_hpd_sense,
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.set_polarity = &r100_hpd_set_polarity,
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},
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.ioctl_wait_idle = NULL,
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.gui_idle = &r100_gui_idle,
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.pm = {
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.misc = &r100_pm_misc,
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.prepare = &r100_pm_prepare,
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@ -199,7 +200,6 @@ static struct radeon_asic r100_asic = {
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.page_flip = &r100_page_flip,
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.post_page_flip = &r100_post_page_flip,
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},
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.mc_wait_for_idle = &r100_mc_wait_for_idle,
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};
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static struct radeon_asic r200_asic = {
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@ -210,6 +210,9 @@ static struct radeon_asic r200_asic = {
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.vga_set_state = &r100_vga_set_state,
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.gpu_is_lockup = &r100_gpu_is_lockup,
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.asic_reset = &r100_asic_reset,
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.ioctl_wait_idle = NULL,
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.gui_idle = &r100_gui_idle,
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.mc_wait_for_idle = &r100_mc_wait_for_idle,
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.gart = {
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.tlb_flush = &r100_pci_gart_tlb_flush,
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.set_page = &r100_pci_gart_set_page,
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@ -252,8 +255,6 @@ static struct radeon_asic r200_asic = {
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.sense = &r100_hpd_sense,
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.set_polarity = &r100_hpd_set_polarity,
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},
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.ioctl_wait_idle = NULL,
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.gui_idle = &r100_gui_idle,
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.pm = {
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.misc = &r100_pm_misc,
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.prepare = &r100_pm_prepare,
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@ -273,7 +274,6 @@ static struct radeon_asic r200_asic = {
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.page_flip = &r100_page_flip,
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.post_page_flip = &r100_post_page_flip,
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},
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.mc_wait_for_idle = &r100_mc_wait_for_idle,
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};
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static struct radeon_asic r300_asic = {
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@ -284,6 +284,9 @@ static struct radeon_asic r300_asic = {
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.vga_set_state = &r100_vga_set_state,
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.gpu_is_lockup = &r300_gpu_is_lockup,
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.asic_reset = &r300_asic_reset,
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.ioctl_wait_idle = NULL,
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.gui_idle = &r100_gui_idle,
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.mc_wait_for_idle = &r300_mc_wait_for_idle,
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.gart = {
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.tlb_flush = &r100_pci_gart_tlb_flush,
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.set_page = &r100_pci_gart_set_page,
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@ -326,8 +329,6 @@ static struct radeon_asic r300_asic = {
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.sense = &r100_hpd_sense,
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.set_polarity = &r100_hpd_set_polarity,
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},
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.ioctl_wait_idle = NULL,
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.gui_idle = &r100_gui_idle,
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.pm = {
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.misc = &r100_pm_misc,
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.prepare = &r100_pm_prepare,
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@ -347,7 +348,6 @@ static struct radeon_asic r300_asic = {
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.page_flip = &r100_page_flip,
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.post_page_flip = &r100_post_page_flip,
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},
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.mc_wait_for_idle = &r300_mc_wait_for_idle,
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};
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static struct radeon_asic r300_asic_pcie = {
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@ -358,6 +358,9 @@ static struct radeon_asic r300_asic_pcie = {
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.vga_set_state = &r100_vga_set_state,
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.gpu_is_lockup = &r300_gpu_is_lockup,
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.asic_reset = &r300_asic_reset,
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.ioctl_wait_idle = NULL,
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.gui_idle = &r100_gui_idle,
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.mc_wait_for_idle = &r300_mc_wait_for_idle,
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.gart = {
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.tlb_flush = &rv370_pcie_gart_tlb_flush,
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.set_page = &rv370_pcie_gart_set_page,
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@ -400,8 +403,6 @@ static struct radeon_asic r300_asic_pcie = {
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.sense = &r100_hpd_sense,
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.set_polarity = &r100_hpd_set_polarity,
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},
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.ioctl_wait_idle = NULL,
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.gui_idle = &r100_gui_idle,
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.pm = {
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.misc = &r100_pm_misc,
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.prepare = &r100_pm_prepare,
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@ -421,7 +422,6 @@ static struct radeon_asic r300_asic_pcie = {
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.page_flip = &r100_page_flip,
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.post_page_flip = &r100_post_page_flip,
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},
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.mc_wait_for_idle = &r300_mc_wait_for_idle,
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};
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static struct radeon_asic r420_asic = {
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@ -432,6 +432,9 @@ static struct radeon_asic r420_asic = {
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.vga_set_state = &r100_vga_set_state,
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.gpu_is_lockup = &r300_gpu_is_lockup,
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.asic_reset = &r300_asic_reset,
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.ioctl_wait_idle = NULL,
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.gui_idle = &r100_gui_idle,
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.mc_wait_for_idle = &r300_mc_wait_for_idle,
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.gart = {
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.tlb_flush = &rv370_pcie_gart_tlb_flush,
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.set_page = &rv370_pcie_gart_set_page,
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@ -474,8 +477,6 @@ static struct radeon_asic r420_asic = {
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.sense = &r100_hpd_sense,
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.set_polarity = &r100_hpd_set_polarity,
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},
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.ioctl_wait_idle = NULL,
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.gui_idle = &r100_gui_idle,
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.pm = {
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.misc = &r100_pm_misc,
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.prepare = &r100_pm_prepare,
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@ -495,7 +496,6 @@ static struct radeon_asic r420_asic = {
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.page_flip = &r100_page_flip,
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.post_page_flip = &r100_post_page_flip,
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},
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.mc_wait_for_idle = &r300_mc_wait_for_idle,
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};
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static struct radeon_asic rs400_asic = {
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@ -506,6 +506,9 @@ static struct radeon_asic rs400_asic = {
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.vga_set_state = &r100_vga_set_state,
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.gpu_is_lockup = &r300_gpu_is_lockup,
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.asic_reset = &r300_asic_reset,
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.ioctl_wait_idle = NULL,
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.gui_idle = &r100_gui_idle,
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.mc_wait_for_idle = &rs400_mc_wait_for_idle,
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.gart = {
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.tlb_flush = &rs400_gart_tlb_flush,
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.set_page = &rs400_gart_set_page,
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@ -548,8 +551,6 @@ static struct radeon_asic rs400_asic = {
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.sense = &r100_hpd_sense,
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.set_polarity = &r100_hpd_set_polarity,
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},
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.ioctl_wait_idle = NULL,
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.gui_idle = &r100_gui_idle,
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.pm = {
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.misc = &r100_pm_misc,
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.prepare = &r100_pm_prepare,
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@ -569,7 +570,6 @@ static struct radeon_asic rs400_asic = {
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.page_flip = &r100_page_flip,
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.post_page_flip = &r100_post_page_flip,
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},
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.mc_wait_for_idle = &rs400_mc_wait_for_idle,
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};
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static struct radeon_asic rs600_asic = {
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@ -580,6 +580,9 @@ static struct radeon_asic rs600_asic = {
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.vga_set_state = &r100_vga_set_state,
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.gpu_is_lockup = &r300_gpu_is_lockup,
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.asic_reset = &rs600_asic_reset,
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.ioctl_wait_idle = NULL,
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.gui_idle = &r100_gui_idle,
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.mc_wait_for_idle = &rs600_mc_wait_for_idle,
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.gart = {
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.tlb_flush = &rs600_gart_tlb_flush,
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.set_page = &rs600_gart_set_page,
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@ -622,8 +625,6 @@ static struct radeon_asic rs600_asic = {
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.sense = &rs600_hpd_sense,
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.set_polarity = &rs600_hpd_set_polarity,
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},
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.ioctl_wait_idle = NULL,
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.gui_idle = &r100_gui_idle,
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.pm = {
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.misc = &rs600_pm_misc,
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.prepare = &rs600_pm_prepare,
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@ -643,7 +644,6 @@ static struct radeon_asic rs600_asic = {
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.page_flip = &rs600_page_flip,
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.post_page_flip = &rs600_post_page_flip,
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},
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.mc_wait_for_idle = &rs600_mc_wait_for_idle,
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};
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static struct radeon_asic rs690_asic = {
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@ -654,6 +654,9 @@ static struct radeon_asic rs690_asic = {
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.vga_set_state = &r100_vga_set_state,
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.gpu_is_lockup = &r300_gpu_is_lockup,
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.asic_reset = &rs600_asic_reset,
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.ioctl_wait_idle = NULL,
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.gui_idle = &r100_gui_idle,
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.mc_wait_for_idle = &rs690_mc_wait_for_idle,
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.gart = {
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.tlb_flush = &rs400_gart_tlb_flush,
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.set_page = &rs400_gart_set_page,
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@ -696,8 +699,6 @@ static struct radeon_asic rs690_asic = {
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.sense = &rs600_hpd_sense,
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.set_polarity = &rs600_hpd_set_polarity,
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},
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.ioctl_wait_idle = NULL,
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.gui_idle = &r100_gui_idle,
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.pm = {
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.misc = &rs600_pm_misc,
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.prepare = &rs600_pm_prepare,
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@ -717,7 +718,6 @@ static struct radeon_asic rs690_asic = {
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.page_flip = &rs600_page_flip,
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.post_page_flip = &rs600_post_page_flip,
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},
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.mc_wait_for_idle = &rs690_mc_wait_for_idle,
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};
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static struct radeon_asic rv515_asic = {
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@ -728,6 +728,9 @@ static struct radeon_asic rv515_asic = {
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.vga_set_state = &r100_vga_set_state,
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.gpu_is_lockup = &r300_gpu_is_lockup,
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.asic_reset = &rs600_asic_reset,
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.ioctl_wait_idle = NULL,
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.gui_idle = &r100_gui_idle,
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.mc_wait_for_idle = &rv515_mc_wait_for_idle,
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.gart = {
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.tlb_flush = &rv370_pcie_gart_tlb_flush,
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.set_page = &rv370_pcie_gart_set_page,
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@ -770,8 +773,6 @@ static struct radeon_asic rv515_asic = {
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.sense = &rs600_hpd_sense,
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.set_polarity = &rs600_hpd_set_polarity,
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},
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.ioctl_wait_idle = NULL,
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.gui_idle = &r100_gui_idle,
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.pm = {
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.misc = &rs600_pm_misc,
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.prepare = &rs600_pm_prepare,
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@ -791,7 +792,6 @@ static struct radeon_asic rv515_asic = {
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.page_flip = &rs600_page_flip,
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.post_page_flip = &rs600_post_page_flip,
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},
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.mc_wait_for_idle = &rv515_mc_wait_for_idle,
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};
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static struct radeon_asic r520_asic = {
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@ -802,6 +802,9 @@ static struct radeon_asic r520_asic = {
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.vga_set_state = &r100_vga_set_state,
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.gpu_is_lockup = &r300_gpu_is_lockup,
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.asic_reset = &rs600_asic_reset,
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.ioctl_wait_idle = NULL,
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.gui_idle = &r100_gui_idle,
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.mc_wait_for_idle = &r520_mc_wait_for_idle,
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.gart = {
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.tlb_flush = &rv370_pcie_gart_tlb_flush,
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.set_page = &rv370_pcie_gart_set_page,
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@ -844,8 +847,6 @@ static struct radeon_asic r520_asic = {
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.sense = &rs600_hpd_sense,
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.set_polarity = &rs600_hpd_set_polarity,
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},
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.ioctl_wait_idle = NULL,
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.gui_idle = &r100_gui_idle,
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.pm = {
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.misc = &rs600_pm_misc,
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.prepare = &rs600_pm_prepare,
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@ -865,7 +866,6 @@ static struct radeon_asic r520_asic = {
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.page_flip = &rs600_page_flip,
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.post_page_flip = &rs600_post_page_flip,
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},
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.mc_wait_for_idle = &r520_mc_wait_for_idle,
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};
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static struct radeon_asic r600_asic = {
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@ -876,6 +876,9 @@ static struct radeon_asic r600_asic = {
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.vga_set_state = &r600_vga_set_state,
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.gpu_is_lockup = &r600_gpu_is_lockup,
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.asic_reset = &r600_asic_reset,
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.ioctl_wait_idle = r600_ioctl_wait_idle,
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.gui_idle = &r600_gui_idle,
|
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.mc_wait_for_idle = &r600_mc_wait_for_idle,
|
||||
.gart = {
|
||||
.tlb_flush = &r600_pcie_gart_tlb_flush,
|
||||
.set_page = &rs600_gart_set_page,
|
||||
@ -917,8 +920,6 @@ static struct radeon_asic r600_asic = {
|
||||
.sense = &r600_hpd_sense,
|
||||
.set_polarity = &r600_hpd_set_polarity,
|
||||
},
|
||||
.ioctl_wait_idle = r600_ioctl_wait_idle,
|
||||
.gui_idle = &r600_gui_idle,
|
||||
.pm = {
|
||||
.misc = &r600_pm_misc,
|
||||
.prepare = &rs600_pm_prepare,
|
||||
@ -938,7 +939,6 @@ static struct radeon_asic r600_asic = {
|
||||
.page_flip = &rs600_page_flip,
|
||||
.post_page_flip = &rs600_post_page_flip,
|
||||
},
|
||||
.mc_wait_for_idle = &r600_mc_wait_for_idle,
|
||||
};
|
||||
|
||||
static struct radeon_asic rs780_asic = {
|
||||
@ -949,6 +949,9 @@ static struct radeon_asic rs780_asic = {
|
||||
.gpu_is_lockup = &r600_gpu_is_lockup,
|
||||
.vga_set_state = &r600_vga_set_state,
|
||||
.asic_reset = &r600_asic_reset,
|
||||
.ioctl_wait_idle = r600_ioctl_wait_idle,
|
||||
.gui_idle = &r600_gui_idle,
|
||||
.mc_wait_for_idle = &r600_mc_wait_for_idle,
|
||||
.gart = {
|
||||
.tlb_flush = &r600_pcie_gart_tlb_flush,
|
||||
.set_page = &rs600_gart_set_page,
|
||||
@ -990,8 +993,6 @@ static struct radeon_asic rs780_asic = {
|
||||
.sense = &r600_hpd_sense,
|
||||
.set_polarity = &r600_hpd_set_polarity,
|
||||
},
|
||||
.ioctl_wait_idle = r600_ioctl_wait_idle,
|
||||
.gui_idle = &r600_gui_idle,
|
||||
.pm = {
|
||||
.misc = &r600_pm_misc,
|
||||
.prepare = &rs600_pm_prepare,
|
||||
@ -1011,7 +1012,6 @@ static struct radeon_asic rs780_asic = {
|
||||
.page_flip = &rs600_page_flip,
|
||||
.post_page_flip = &rs600_post_page_flip,
|
||||
},
|
||||
.mc_wait_for_idle = &r600_mc_wait_for_idle,
|
||||
};
|
||||
|
||||
static struct radeon_asic rv770_asic = {
|
||||
@ -1022,6 +1022,9 @@ static struct radeon_asic rv770_asic = {
|
||||
.asic_reset = &r600_asic_reset,
|
||||
.gpu_is_lockup = &r600_gpu_is_lockup,
|
||||
.vga_set_state = &r600_vga_set_state,
|
||||
.ioctl_wait_idle = r600_ioctl_wait_idle,
|
||||
.gui_idle = &r600_gui_idle,
|
||||
.mc_wait_for_idle = &r600_mc_wait_for_idle,
|
||||
.gart = {
|
||||
.tlb_flush = &r600_pcie_gart_tlb_flush,
|
||||
.set_page = &rs600_gart_set_page,
|
||||
@ -1063,8 +1066,6 @@ static struct radeon_asic rv770_asic = {
|
||||
.sense = &r600_hpd_sense,
|
||||
.set_polarity = &r600_hpd_set_polarity,
|
||||
},
|
||||
.ioctl_wait_idle = r600_ioctl_wait_idle,
|
||||
.gui_idle = &r600_gui_idle,
|
||||
.pm = {
|
||||
.misc = &rv770_pm_misc,
|
||||
.prepare = &rs600_pm_prepare,
|
||||
@ -1084,7 +1085,6 @@ static struct radeon_asic rv770_asic = {
|
||||
.page_flip = &rv770_page_flip,
|
||||
.post_page_flip = &rs600_post_page_flip,
|
||||
},
|
||||
.mc_wait_for_idle = &r600_mc_wait_for_idle,
|
||||
};
|
||||
|
||||
static struct radeon_asic evergreen_asic = {
|
||||
@ -1095,6 +1095,9 @@ static struct radeon_asic evergreen_asic = {
|
||||
.gpu_is_lockup = &evergreen_gpu_is_lockup,
|
||||
.asic_reset = &evergreen_asic_reset,
|
||||
.vga_set_state = &r600_vga_set_state,
|
||||
.ioctl_wait_idle = r600_ioctl_wait_idle,
|
||||
.gui_idle = &r600_gui_idle,
|
||||
.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
|
||||
.gart = {
|
||||
.tlb_flush = &evergreen_pcie_gart_tlb_flush,
|
||||
.set_page = &rs600_gart_set_page,
|
||||
@ -1136,8 +1139,6 @@ static struct radeon_asic evergreen_asic = {
|
||||
.sense = &evergreen_hpd_sense,
|
||||
.set_polarity = &evergreen_hpd_set_polarity,
|
||||
},
|
||||
.ioctl_wait_idle = r600_ioctl_wait_idle,
|
||||
.gui_idle = &r600_gui_idle,
|
||||
.pm = {
|
||||
.misc = &evergreen_pm_misc,
|
||||
.prepare = &evergreen_pm_prepare,
|
||||
@ -1157,7 +1158,6 @@ static struct radeon_asic evergreen_asic = {
|
||||
.page_flip = &evergreen_page_flip,
|
||||
.post_page_flip = &evergreen_post_page_flip,
|
||||
},
|
||||
.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
|
||||
};
|
||||
|
||||
static struct radeon_asic sumo_asic = {
|
||||
@ -1168,6 +1168,9 @@ static struct radeon_asic sumo_asic = {
|
||||
.gpu_is_lockup = &evergreen_gpu_is_lockup,
|
||||
.asic_reset = &evergreen_asic_reset,
|
||||
.vga_set_state = &r600_vga_set_state,
|
||||
.ioctl_wait_idle = r600_ioctl_wait_idle,
|
||||
.gui_idle = &r600_gui_idle,
|
||||
.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
|
||||
.gart = {
|
||||
.tlb_flush = &evergreen_pcie_gart_tlb_flush,
|
||||
.set_page = &rs600_gart_set_page,
|
||||
@ -1209,8 +1212,6 @@ static struct radeon_asic sumo_asic = {
|
||||
.sense = &evergreen_hpd_sense,
|
||||
.set_polarity = &evergreen_hpd_set_polarity,
|
||||
},
|
||||
.ioctl_wait_idle = r600_ioctl_wait_idle,
|
||||
.gui_idle = &r600_gui_idle,
|
||||
.pm = {
|
||||
.misc = &evergreen_pm_misc,
|
||||
.prepare = &evergreen_pm_prepare,
|
||||
@ -1230,7 +1231,6 @@ static struct radeon_asic sumo_asic = {
|
||||
.page_flip = &evergreen_page_flip,
|
||||
.post_page_flip = &evergreen_post_page_flip,
|
||||
},
|
||||
.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
|
||||
};
|
||||
|
||||
static struct radeon_asic btc_asic = {
|
||||
@ -1241,6 +1241,9 @@ static struct radeon_asic btc_asic = {
|
||||
.gpu_is_lockup = &evergreen_gpu_is_lockup,
|
||||
.asic_reset = &evergreen_asic_reset,
|
||||
.vga_set_state = &r600_vga_set_state,
|
||||
.ioctl_wait_idle = r600_ioctl_wait_idle,
|
||||
.gui_idle = &r600_gui_idle,
|
||||
.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
|
||||
.gart = {
|
||||
.tlb_flush = &evergreen_pcie_gart_tlb_flush,
|
||||
.set_page = &rs600_gart_set_page,
|
||||
@ -1282,8 +1285,6 @@ static struct radeon_asic btc_asic = {
|
||||
.sense = &evergreen_hpd_sense,
|
||||
.set_polarity = &evergreen_hpd_set_polarity,
|
||||
},
|
||||
.ioctl_wait_idle = r600_ioctl_wait_idle,
|
||||
.gui_idle = &r600_gui_idle,
|
||||
.pm = {
|
||||
.misc = &evergreen_pm_misc,
|
||||
.prepare = &evergreen_pm_prepare,
|
||||
@ -1303,7 +1304,6 @@ static struct radeon_asic btc_asic = {
|
||||
.page_flip = &evergreen_page_flip,
|
||||
.post_page_flip = &evergreen_post_page_flip,
|
||||
},
|
||||
.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
|
||||
};
|
||||
|
||||
static const struct radeon_vm_funcs cayman_vm_funcs = {
|
||||
@ -1324,6 +1324,9 @@ static struct radeon_asic cayman_asic = {
|
||||
.gpu_is_lockup = &cayman_gpu_is_lockup,
|
||||
.asic_reset = &cayman_asic_reset,
|
||||
.vga_set_state = &r600_vga_set_state,
|
||||
.ioctl_wait_idle = r600_ioctl_wait_idle,
|
||||
.gui_idle = &r600_gui_idle,
|
||||
.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
|
||||
.gart = {
|
||||
.tlb_flush = &cayman_pcie_gart_tlb_flush,
|
||||
.set_page = &rs600_gart_set_page,
|
||||
@ -1384,8 +1387,6 @@ static struct radeon_asic cayman_asic = {
|
||||
.sense = &evergreen_hpd_sense,
|
||||
.set_polarity = &evergreen_hpd_set_polarity,
|
||||
},
|
||||
.ioctl_wait_idle = r600_ioctl_wait_idle,
|
||||
.gui_idle = &r600_gui_idle,
|
||||
.pm = {
|
||||
.misc = &evergreen_pm_misc,
|
||||
.prepare = &evergreen_pm_prepare,
|
||||
@ -1405,7 +1406,6 @@ static struct radeon_asic cayman_asic = {
|
||||
.page_flip = &evergreen_page_flip,
|
||||
.post_page_flip = &evergreen_post_page_flip,
|
||||
},
|
||||
.mc_wait_for_idle = &evergreen_mc_wait_for_idle,
|
||||
};
|
||||
|
||||
int radeon_asic_init(struct radeon_device *rdev)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user