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myri10ge: replace the chipset whitelist with firmware autodetection
Remove the aligned-completion whitelist, and replace it by using the 1.4.16 firmware's auto-detection features to choose which firmware to load. The driver now loads the aligned firmware, performs a MXGEFW_CMD_UNALIGNED_TEST, and falls back to using the unaligned firmware if: - The firmware is too old (ie, MXGEFW_CMD_UNALIGNED_TEST is an unknown command). - The MXGEFW_CMD_UNALIGNED_TEST returns MXGEFW_CMD_ERROR_UNALIGNED, meaning that it has seen an unaligned completion during the DMA test. Signed-off-by: Brice Goglin <brice@myri.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Brice Goglin
Jeff Garzik
parent
0d6ac257ab
commit
5443e9ead4
@ -355,6 +355,8 @@ myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
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return 0;
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} else if (result == MXGEFW_CMD_UNKNOWN) {
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return -ENOSYS;
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} else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
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return -E2BIG;
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} else {
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dev_err(&mgp->pdev->dev,
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"command %d failed, result = %d\n",
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@ -2483,8 +2485,6 @@ static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
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err_cap |= PCI_ERR_CAP_ECRC_GENE;
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pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
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dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
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mgp->tx.boundary = 4096;
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mgp->fw_name = myri10ge_fw_aligned;
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}
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/*
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@ -2506,22 +2506,70 @@ static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
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* firmware image, and set tx.boundary to 4KB.
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*/
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#define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7
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#define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa
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#define PCI_DEVICE_ID_INTEL_6300ESB_PCIEE1 0x3510
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#define PCI_DEVICE_ID_INTEL_6300ESB_PCIEE4 0x351b
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#define PCI_DEVICE_ID_INTEL_E3000_PCIE 0x2779
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#define PCI_DEVICE_ID_INTEL_E3010_PCIE 0x277a
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#define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST 0x140
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#define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST 0x142
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static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
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static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
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{
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struct pci_dev *bridge = mgp->pdev->bus->self;
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struct pci_dev *pdev = mgp->pdev;
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struct device *dev = &pdev->dev;
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int cap, status;
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u16 val;
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mgp->tx.boundary = 4096;
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/*
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* Verify the max read request size was set to 4KB
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* before trying the test with 4KB.
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*/
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cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
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if (cap < 64) {
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dev_err(dev, "Bad PCI_CAP_ID_EXP location %d\n", cap);
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goto abort;
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}
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status = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &val);
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if (status != 0) {
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dev_err(dev, "Couldn't read max read req size: %d\n", status);
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goto abort;
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}
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if ((val & (5 << 12)) != (5 << 12)) {
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dev_warn(dev, "Max Read Request size != 4096 (0x%x)\n", val);
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mgp->tx.boundary = 2048;
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}
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/*
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* load the optimized firmware (which assumes aligned PCIe
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* completions) in order to see if it works on this host.
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*/
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mgp->fw_name = myri10ge_fw_aligned;
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status = myri10ge_load_firmware(mgp);
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if (status != 0) {
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goto abort;
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}
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/*
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* Enable ECRC if possible
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*/
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myri10ge_enable_ecrc(mgp);
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/*
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* Run a DMA test which watches for unaligned completions and
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* aborts on the first one seen.
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*/
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status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
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if (status == 0)
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return; /* keep the aligned firmware */
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if (status != -E2BIG)
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dev_warn(dev, "DMA test failed: %d\n", status);
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if (status == -ENOSYS)
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dev_warn(dev, "Falling back to ethp! "
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"Please install up to date fw\n");
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abort:
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/* fall back to using the unaligned firmware */
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mgp->tx.boundary = 2048;
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mgp->fw_name = myri10ge_fw_unaligned;
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}
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static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
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{
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if (myri10ge_force_firmware == 0) {
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int link_width, exp_cap;
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u16 lnk;
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@ -2530,8 +2578,6 @@ static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
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pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
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link_width = (lnk >> 4) & 0x3f;
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myri10ge_enable_ecrc(mgp);
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/* Check to see if Link is less than 8 or if the
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* upstream bridge is known to provide aligned
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* completions */
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@ -2540,46 +2586,8 @@ static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
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link_width);
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mgp->tx.boundary = 4096;
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mgp->fw_name = myri10ge_fw_aligned;
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} else if (bridge &&
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/* ServerWorks HT2000/HT1000 */
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((bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
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&& bridge->device ==
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PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE)
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/* ServerWorks HT2100 */
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|| (bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
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&& bridge->device >=
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PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST
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&& bridge->device <=
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PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST)
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/* All Intel E3000/E3010 PCIE ports */
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|| (bridge->vendor == PCI_VENDOR_ID_INTEL
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&& (bridge->device ==
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PCI_DEVICE_ID_INTEL_E3000_PCIE
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|| bridge->device ==
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PCI_DEVICE_ID_INTEL_E3010_PCIE))
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/* All Intel 6310/6311/6321ESB PCIE ports */
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|| (bridge->vendor == PCI_VENDOR_ID_INTEL
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&& bridge->device >=
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PCI_DEVICE_ID_INTEL_6300ESB_PCIEE1
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&& bridge->device <=
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PCI_DEVICE_ID_INTEL_6300ESB_PCIEE4)
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/* All Intel E5000 PCIE ports */
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|| (bridge->vendor == PCI_VENDOR_ID_INTEL
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&& bridge->device >=
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PCI_DEVICE_ID_INTEL_E5000_PCIE23
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&& bridge->device <=
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PCI_DEVICE_ID_INTEL_E5000_PCIE47))) {
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dev_info(&mgp->pdev->dev,
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"Assuming aligned completions (0x%x:0x%x)\n",
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bridge->vendor, bridge->device);
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mgp->tx.boundary = 4096;
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mgp->fw_name = myri10ge_fw_aligned;
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} else if (bridge &&
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bridge->vendor == PCI_VENDOR_ID_SGI &&
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bridge->device == 0x4002 /* TIOCE pcie-port */ ) {
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/* this pcie bridge does not support 4K rdma request */
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mgp->tx.boundary = 2048;
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mgp->fw_name = myri10ge_fw_aligned;
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} else {
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myri10ge_firmware_probe(mgp);
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}
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} else {
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if (myri10ge_force_firmware == 1) {
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@ -2847,7 +2855,6 @@ static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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status = -ENODEV;
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goto abort_with_netdev;
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}
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myri10ge_select_firmware(mgp);
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/* Find the vendor-specific cap so we can check
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* the reboot register later on */
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@ -2941,6 +2948,8 @@ static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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goto abort_with_ioremap;
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memset(mgp->rx_done.entry, 0, bytes);
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myri10ge_select_firmware(mgp);
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status = myri10ge_load_firmware(mgp);
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if (status != 0) {
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dev_err(&pdev->dev, "failed to load firmware\n");
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