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drm/amd/display: Update dram_clock_change_latency for DCN2.1

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[WHY]
dram clock change latencies get updated using ddr4 latency table, but
that update does not happen before validation. This value
should not be the default and should be number received from
df for better mode support.
This may cause a PState hang on high refresh panels with short vblanks
such as on 1080p 360hz or 300hz panels.

[HOW]
Update latency from 23.84 to 11.72.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Reviewed-by: Sung Lee <Sung.Lee@amd.com>
Acked-by: Anson Jacob <anson.jacob@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jake Wang 2021-01-08 12:27:51 -05:00 committed by Alex Deucher
parent 8aeb42bd2b
commit 5383007716
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
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@ -296,7 +296,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
.num_banks = 8, .num_banks = 8,
.num_chans = 4, .num_chans = 4,
.vmm_page_size_bytes = 4096, .vmm_page_size_bytes = 4096,
.dram_clock_change_latency_us = 23.84, .dram_clock_change_latency_us = 11.72,
.return_bus_width_bytes = 64, .return_bus_width_bytes = 64,
.dispclk_dppclk_vco_speed_mhz = 3600, .dispclk_dppclk_vco_speed_mhz = 3600,
.xfc_bus_transport_time_us = 4, .xfc_bus_transport_time_us = 4,