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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Ingo Molnar: "Misc fixes (mainly Andy's TLS fixes), plus a cleanup" * 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/tls: Disallow unusual TLS segments x86/tls: Validate TLS entries to protect espfix MAINTAINERS: Add me as x86 VDSO submaintainer x86/asm: Unify segment selector defines x86/asm: Guard against building the 32/64-bit versions of the asm-offsets*.c file directly x86_64, switch_to(): Load TLS descriptors before switching DS and ES x86/mm: Use min() instead of min_t() in the e820 printout code x86/mm: Fix zone ranges boot printout x86/doc: Update documentation after file shuffling
This commit is contained in:
commit
536e89ee53
@ -7,9 +7,12 @@ http://lkml.kernel.org/r/<20110529191055.GC9835%40elte.hu>
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The x86 architecture has quite a few different ways to jump into
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kernel code. Most of these entry points are registered in
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arch/x86/kernel/traps.c and implemented in arch/x86/kernel/entry_64.S
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and arch/x86/ia32/ia32entry.S.
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for 64-bit, arch/x86/kernel/entry_32.S for 32-bit and finally
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arch/x86/ia32/ia32entry.S which implements the 32-bit compatibility
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syscall entry points and thus provides for 32-bit processes the
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ability to execute syscalls when running on 64-bit kernels.
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The IDT vector assignments are listed in arch/x86/include/irq_vectors.h.
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The IDT vector assignments are listed in arch/x86/include/asm/irq_vectors.h.
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Some of these entries are:
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@ -10485,6 +10485,13 @@ L: linux-edac@vger.kernel.org
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S: Maintained
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F: arch/x86/kernel/cpu/mcheck/*
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X86 VDSO
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M: Andy Lutomirski <luto@amacapital.net>
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L: linux-kernel@vger.kernel.org
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/vdso
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S: Maintained
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F: arch/x86/vdso/
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XC2028/3028 TUNER DRIVER
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M: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
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L: linux-media@vger.kernel.org
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@ -70,7 +70,7 @@
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#define MAX_DMA_CHANNELS 8
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/* 16MB ISA DMA zone */
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#define MAX_DMA_PFN ((16 * 1024 * 1024) >> PAGE_SHIFT)
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#define MAX_DMA_PFN ((16UL * 1024 * 1024) >> PAGE_SHIFT)
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/* 4GB broken PCI/AGP hardware bus master zone */
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#define MAX_DMA32_PFN ((4UL * 1024 * 1024 * 1024) >> PAGE_SHIFT)
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@ -23,6 +23,15 @@
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#define GDT_ENTRY_BOOT_TSS (GDT_ENTRY_BOOT_CS + 2)
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#define __BOOT_TSS (GDT_ENTRY_BOOT_TSS * 8)
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#define SEGMENT_RPL_MASK 0x3 /*
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* Bottom two bits of selector give the ring
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* privilege level
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*/
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#define SEGMENT_TI_MASK 0x4 /* Bit 2 is table indicator (LDT/GDT) */
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#define USER_RPL 0x3 /* User mode is privilege level 3 */
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#define SEGMENT_LDT 0x4 /* LDT segment has TI set... */
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#define SEGMENT_GDT 0x0 /* ... GDT has it cleared */
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#ifdef CONFIG_X86_32
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/*
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* The layout of the per-CPU GDT under Linux:
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@ -125,16 +134,6 @@
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#define PNP_TS1 (GDT_ENTRY_PNPBIOS_TS1 * 8) /* transfer data segment */
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#define PNP_TS2 (GDT_ENTRY_PNPBIOS_TS2 * 8) /* another data segment */
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/* Bottom two bits of selector give the ring privilege level */
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#define SEGMENT_RPL_MASK 0x3
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/* Bit 2 is table indicator (LDT/GDT) */
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#define SEGMENT_TI_MASK 0x4
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/* User mode is privilege level 3 */
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#define USER_RPL 0x3
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/* LDT segment has TI set, GDT has it cleared */
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#define SEGMENT_LDT 0x4
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#define SEGMENT_GDT 0x0
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/*
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* Matching rules for certain types of segments.
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@ -192,17 +191,6 @@
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#define get_kernel_rpl() 0
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#endif
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/* User mode is privilege level 3 */
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#define USER_RPL 0x3
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/* LDT segment has TI set, GDT has it cleared */
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#define SEGMENT_LDT 0x4
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#define SEGMENT_GDT 0x0
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/* Bottom two bits of selector give the ring privilege level */
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#define SEGMENT_RPL_MASK 0x3
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/* Bit 2 is table indicator (LDT/GDT) */
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#define SEGMENT_TI_MASK 0x4
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#define IDT_ENTRIES 256
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#define NUM_EXCEPTION_VECTORS 32
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/* Bitmask of exception vectors which push an error code on the stack */
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@ -1,3 +1,7 @@
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#ifndef __LINUX_KBUILD_H
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# error "Please do not build this file directly, build asm-offsets.c instead"
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#endif
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#include <asm/ucontext.h>
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#include <linux/lguest.h>
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@ -1,3 +1,7 @@
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#ifndef __LINUX_KBUILD_H
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# error "Please do not build this file directly, build asm-offsets.c instead"
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#endif
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#include <asm/ia32.h>
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#define __SYSCALL_64(nr, sym, compat) [nr] = 1,
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@ -1114,8 +1114,8 @@ void __init memblock_find_dma_reserve(void)
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* at first, and assume boot_mem will not take below MAX_DMA_PFN
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*/
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for_each_mem_pfn_range(i, MAX_NUMNODES, &start_pfn, &end_pfn, NULL) {
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start_pfn = min_t(unsigned long, start_pfn, MAX_DMA_PFN);
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end_pfn = min_t(unsigned long, end_pfn, MAX_DMA_PFN);
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start_pfn = min(start_pfn, MAX_DMA_PFN);
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end_pfn = min(end_pfn, MAX_DMA_PFN);
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nr_pages += end_pfn - start_pfn;
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}
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@ -283,24 +283,9 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
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fpu = switch_fpu_prepare(prev_p, next_p, cpu);
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/*
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* Reload esp0, LDT and the page table pointer:
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*/
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/* Reload esp0 and ss1. */
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load_sp0(tss, next);
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/*
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* Switch DS and ES.
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* This won't pick up thread selector changes, but I guess that is ok.
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*/
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savesegment(es, prev->es);
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if (unlikely(next->es | prev->es))
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loadsegment(es, next->es);
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savesegment(ds, prev->ds);
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if (unlikely(next->ds | prev->ds))
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loadsegment(ds, next->ds);
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/* We must save %fs and %gs before load_TLS() because
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* %fs and %gs may be cleared by load_TLS().
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*
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@ -309,41 +294,101 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
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savesegment(fs, fsindex);
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savesegment(gs, gsindex);
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/*
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* Load TLS before restoring any segments so that segment loads
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* reference the correct GDT entries.
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*/
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load_TLS(next, cpu);
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/*
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* Leave lazy mode, flushing any hypercalls made here.
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* This must be done before restoring TLS segments so
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* the GDT and LDT are properly updated, and must be
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* done before math_state_restore, so the TS bit is up
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* to date.
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* Leave lazy mode, flushing any hypercalls made here. This
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* must be done after loading TLS entries in the GDT but before
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* loading segments that might reference them, and and it must
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* be done before math_state_restore, so the TS bit is up to
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* date.
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*/
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arch_end_context_switch(next_p);
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/* Switch DS and ES.
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*
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* Reading them only returns the selectors, but writing them (if
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* nonzero) loads the full descriptor from the GDT or LDT. The
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* LDT for next is loaded in switch_mm, and the GDT is loaded
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* above.
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*
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* We therefore need to write new values to the segment
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* registers on every context switch unless both the new and old
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* values are zero.
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*
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* Note that we don't need to do anything for CS and SS, as
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* those are saved and restored as part of pt_regs.
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*/
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savesegment(es, prev->es);
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if (unlikely(next->es | prev->es))
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loadsegment(es, next->es);
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savesegment(ds, prev->ds);
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if (unlikely(next->ds | prev->ds))
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loadsegment(ds, next->ds);
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/*
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* Switch FS and GS.
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*
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* Segment register != 0 always requires a reload. Also
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* reload when it has changed. When prev process used 64bit
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* base always reload to avoid an information leak.
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* These are even more complicated than FS and GS: they have
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* 64-bit bases are that controlled by arch_prctl. Those bases
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* only differ from the values in the GDT or LDT if the selector
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* is 0.
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*
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* Loading the segment register resets the hidden base part of
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* the register to 0 or the value from the GDT / LDT. If the
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* next base address zero, writing 0 to the segment register is
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* much faster than using wrmsr to explicitly zero the base.
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*
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* The thread_struct.fs and thread_struct.gs values are 0
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* if the fs and gs bases respectively are not overridden
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* from the values implied by fsindex and gsindex. They
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* are nonzero, and store the nonzero base addresses, if
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* the bases are overridden.
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*
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* (fs != 0 && fsindex != 0) || (gs != 0 && gsindex != 0) should
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* be impossible.
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*
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* Therefore we need to reload the segment registers if either
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* the old or new selector is nonzero, and we need to override
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* the base address if next thread expects it to be overridden.
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*
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* This code is unnecessarily slow in the case where the old and
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* new indexes are zero and the new base is nonzero -- it will
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* unnecessarily write 0 to the selector before writing the new
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* base address.
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*
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* Note: This all depends on arch_prctl being the only way that
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* user code can override the segment base. Once wrfsbase and
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* wrgsbase are enabled, most of this code will need to change.
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*/
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if (unlikely(fsindex | next->fsindex | prev->fs)) {
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loadsegment(fs, next->fsindex);
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/*
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* Check if the user used a selector != 0; if yes
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* clear 64bit base, since overloaded base is always
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* mapped to the Null selector
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* If user code wrote a nonzero value to FS, then it also
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* cleared the overridden base address.
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*
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* XXX: if user code wrote 0 to FS and cleared the base
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* address itself, we won't notice and we'll incorrectly
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* restore the prior base address next time we reschdule
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* the process.
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*/
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if (fsindex)
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prev->fs = 0;
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}
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/* when next process has a 64bit base use it */
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if (next->fs)
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wrmsrl(MSR_FS_BASE, next->fs);
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prev->fsindex = fsindex;
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if (unlikely(gsindex | next->gsindex | prev->gs)) {
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load_gs_index(next->gsindex);
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/* This works (and fails) the same way as fsindex above. */
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if (gsindex)
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prev->gs = 0;
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}
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@ -27,6 +27,43 @@ static int get_free_idx(void)
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return -ESRCH;
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}
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static bool tls_desc_okay(const struct user_desc *info)
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{
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if (LDT_empty(info))
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return true;
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/*
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* espfix is required for 16-bit data segments, but espfix
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* only works for LDT segments.
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*/
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if (!info->seg_32bit)
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return false;
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/* Only allow data segments in the TLS array. */
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if (info->contents > 1)
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return false;
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/*
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* Non-present segments with DPL 3 present an interesting attack
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* surface. The kernel should handle such segments correctly,
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* but TLS is very difficult to protect in a sandbox, so prevent
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* such segments from being created.
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*
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* If userspace needs to remove a TLS entry, it can still delete
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* it outright.
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*/
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if (info->seg_not_present)
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return false;
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#ifdef CONFIG_X86_64
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/* The L bit makes no sense for data. */
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if (info->lm)
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return false;
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#endif
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return true;
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}
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static void set_tls_desc(struct task_struct *p, int idx,
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const struct user_desc *info, int n)
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{
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@ -66,6 +103,9 @@ int do_set_thread_area(struct task_struct *p, int idx,
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if (copy_from_user(&info, u_info, sizeof(info)))
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return -EFAULT;
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if (!tls_desc_okay(&info))
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return -EINVAL;
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if (idx == -1)
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idx = info.entry_number;
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@ -192,6 +232,7 @@ int regset_tls_set(struct task_struct *target, const struct user_regset *regset,
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{
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struct user_desc infobuf[GDT_ENTRY_TLS_ENTRIES];
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const struct user_desc *info;
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int i;
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if (pos >= GDT_ENTRY_TLS_ENTRIES * sizeof(struct user_desc) ||
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(pos % sizeof(struct user_desc)) != 0 ||
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@ -205,6 +246,10 @@ int regset_tls_set(struct task_struct *target, const struct user_regset *regset,
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else
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info = infobuf;
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for (i = 0; i < count / sizeof(struct user_desc); i++)
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if (!tls_desc_okay(info + i))
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return -EINVAL;
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set_tls_desc(target,
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GDT_ENTRY_TLS_MIN + (pos / sizeof(struct user_desc)),
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info, count / sizeof(struct user_desc));
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@ -703,10 +703,10 @@ void __init zone_sizes_init(void)
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memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
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#ifdef CONFIG_ZONE_DMA
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max_zone_pfns[ZONE_DMA] = MAX_DMA_PFN;
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max_zone_pfns[ZONE_DMA] = min(MAX_DMA_PFN, max_low_pfn);
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#endif
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#ifdef CONFIG_ZONE_DMA32
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max_zone_pfns[ZONE_DMA32] = MAX_DMA32_PFN;
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max_zone_pfns[ZONE_DMA32] = min(MAX_DMA32_PFN, max_low_pfn);
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#endif
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max_zone_pfns[ZONE_NORMAL] = max_low_pfn;
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#ifdef CONFIG_HIGHMEM
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