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https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-11 13:04:03 +08:00
Merge branch 'remotes/lorenzo/pci/imx'
- Simplify imx7d_pcie_wait_for_phy_pll_lock() by using
regmap_read_poll_timeout() (Andrey Smirnov)
- Drop imx6_pcie_wait_for_link() in favor of the more generic
dw_pcie_wait_for_link() (Andrey Smirnov)
- Return -ETIMEDOUT instead of -EINVAL from
imx6_pcie_wait_for_speed_change() (Andrey Smirnov)
- Remove unused PCIE_PL_PFLR_* constants from imx6 (Andrey Smirnov)
- Use shared PHY debug register definitions in imx6 (Andrey Smirnov)
- Use BIT() in imx6 (Andrey Smirnov)
- Simplify imx6 PHY bit operations (Andrey Smirnov)
- Simplify imx6 pcie_phy_poll_ack() (Andrey Smirnov)
- Use data types that match actual imx6 PHY register width (Andrey
Smirnov)
- Mark imx6 suspend support with drvdata flags instead of checking
variants (Andrey Smirnov)
- Sleep instead of delay in imx6_pcie_enable_ref_clk() (Andrey Smirnov)
* remotes/lorenzo/pci/imx:
PCI: imx6: Use usleep_range() in imx6_pcie_enable_ref_clk()
PCI: imx6: Use flags to indicate support for suspend
PCI: imx6: Restrict PHY register data to 16-bit
PCI: imx6: Simplify pcie_phy_poll_ack()
PCI: imx6: Simplify bit operations in PHY functions
PCI: imx6: Make use of BIT() in constant definitions
PCI: dwc: imx6: Share PHY debug register definitions
PCI: imx6: Remove PCIE_PL_PFLR_* constants
PCI: imx6: Return -ETIMEOUT from imx6_pcie_wait_for_speed_change()
PCI: imx6: Drop imx6_pcie_wait_for_link()
PCI: imx6: Simplify imx7d_pcie_wait_for_phy_pll_lock()
This commit is contained in:
Bjorn Helgaas
commit
5349abcf8e
@ -52,6 +52,7 @@ enum imx6_pcie_variants {
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#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
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#define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE BIT(1)
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#define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND BIT(2)
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struct imx6_pcie_drvdata {
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enum imx6_pcie_variants variant;
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@ -89,9 +90,8 @@ struct imx6_pcie {
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};
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/* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
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#define PHY_PLL_LOCK_WAIT_MAX_RETRIES 2000
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#define PHY_PLL_LOCK_WAIT_USLEEP_MIN 50
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#define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200
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#define PHY_PLL_LOCK_WAIT_TIMEOUT (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX)
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/* PCIe Root Complex registers (memory-mapped) */
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#define PCIE_RC_IMX6_MSI_CAP 0x50
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@ -104,34 +104,29 @@ struct imx6_pcie {
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/* PCIe Port Logic registers (memory-mapped) */
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#define PL_OFFSET 0x700
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#define PCIE_PL_PFLR (PL_OFFSET + 0x08)
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#define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
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#define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
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#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
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#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
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#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
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#define PCIE_PHY_CTRL_DATA_LOC 0
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#define PCIE_PHY_CTRL_CAP_ADR_LOC 16
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#define PCIE_PHY_CTRL_CAP_DAT_LOC 17
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#define PCIE_PHY_CTRL_WR_LOC 18
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#define PCIE_PHY_CTRL_RD_LOC 19
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#define PCIE_PHY_CTRL_DATA(x) FIELD_PREP(GENMASK(15, 0), (x))
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#define PCIE_PHY_CTRL_CAP_ADR BIT(16)
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#define PCIE_PHY_CTRL_CAP_DAT BIT(17)
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#define PCIE_PHY_CTRL_WR BIT(18)
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#define PCIE_PHY_CTRL_RD BIT(19)
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#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
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#define PCIE_PHY_STAT_ACK_LOC 16
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#define PCIE_PHY_STAT_ACK BIT(16)
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#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
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/* PHY registers (not memory-mapped) */
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#define PCIE_PHY_ATEOVRD 0x10
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#define PCIE_PHY_ATEOVRD_EN (0x1 << 2)
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#define PCIE_PHY_ATEOVRD_EN BIT(2)
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#define PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT 0
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#define PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK 0x1
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#define PCIE_PHY_MPLL_OVRD_IN_LO 0x11
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#define PCIE_PHY_MPLL_MULTIPLIER_SHIFT 2
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#define PCIE_PHY_MPLL_MULTIPLIER_MASK 0x7f
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#define PCIE_PHY_MPLL_MULTIPLIER_OVRD (0x1 << 9)
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#define PCIE_PHY_MPLL_MULTIPLIER_OVRD BIT(9)
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#define PCIE_PHY_RX_ASIC_OUT 0x100D
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#define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0)
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@ -154,19 +149,19 @@ struct imx6_pcie {
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#define PCIE_PHY_CMN_REG26_ATT_MODE 0xBC
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#define PHY_RX_OVRD_IN_LO 0x1005
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#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
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#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
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#define PHY_RX_OVRD_IN_LO_RX_DATA_EN BIT(5)
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#define PHY_RX_OVRD_IN_LO_RX_PLL_EN BIT(3)
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static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
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static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
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{
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struct dw_pcie *pci = imx6_pcie->pci;
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u32 val;
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bool val;
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u32 max_iterations = 10;
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u32 wait_counter = 0;
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do {
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val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
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val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
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val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT) &
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PCIE_PHY_STAT_ACK;
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wait_counter++;
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if (val == exp_val)
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@ -184,27 +179,27 @@ static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
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u32 val;
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int ret;
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val = addr << PCIE_PHY_CTRL_DATA_LOC;
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val = PCIE_PHY_CTRL_DATA(addr);
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
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val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
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val |= PCIE_PHY_CTRL_CAP_ADR;
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
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ret = pcie_phy_poll_ack(imx6_pcie, 1);
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ret = pcie_phy_poll_ack(imx6_pcie, true);
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if (ret)
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return ret;
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val = addr << PCIE_PHY_CTRL_DATA_LOC;
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val = PCIE_PHY_CTRL_DATA(addr);
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
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return pcie_phy_poll_ack(imx6_pcie, 0);
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return pcie_phy_poll_ack(imx6_pcie, false);
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}
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/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
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static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
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static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data)
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{
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struct dw_pcie *pci = imx6_pcie->pci;
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u32 val, phy_ctl;
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u32 phy_ctl;
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int ret;
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ret = pcie_phy_wait_ack(imx6_pcie, addr);
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@ -212,23 +207,22 @@ static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
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return ret;
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/* assert Read signal */
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phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
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phy_ctl = PCIE_PHY_CTRL_RD;
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
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ret = pcie_phy_poll_ack(imx6_pcie, 1);
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ret = pcie_phy_poll_ack(imx6_pcie, true);
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if (ret)
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return ret;
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val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
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*data = val & 0xffff;
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*data = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
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/* deassert Read signal */
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
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return pcie_phy_poll_ack(imx6_pcie, 0);
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return pcie_phy_poll_ack(imx6_pcie, false);
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}
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static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
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static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
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{
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struct dw_pcie *pci = imx6_pcie->pci;
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u32 var;
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@ -240,41 +234,41 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
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if (ret)
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return ret;
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var = data << PCIE_PHY_CTRL_DATA_LOC;
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var = PCIE_PHY_CTRL_DATA(data);
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
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/* capture data */
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var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
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var |= PCIE_PHY_CTRL_CAP_DAT;
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
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ret = pcie_phy_poll_ack(imx6_pcie, 1);
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ret = pcie_phy_poll_ack(imx6_pcie, true);
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if (ret)
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return ret;
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/* deassert cap data */
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var = data << PCIE_PHY_CTRL_DATA_LOC;
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var = PCIE_PHY_CTRL_DATA(data);
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
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/* wait for ack de-assertion */
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ret = pcie_phy_poll_ack(imx6_pcie, 0);
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ret = pcie_phy_poll_ack(imx6_pcie, false);
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if (ret)
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return ret;
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/* assert wr signal */
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var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
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var = PCIE_PHY_CTRL_WR;
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
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/* wait for ack */
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ret = pcie_phy_poll_ack(imx6_pcie, 1);
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ret = pcie_phy_poll_ack(imx6_pcie, true);
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if (ret)
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return ret;
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/* deassert wr signal */
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var = data << PCIE_PHY_CTRL_DATA_LOC;
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var = PCIE_PHY_CTRL_DATA(data);
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dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
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/* wait for ack de-assertion */
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ret = pcie_phy_poll_ack(imx6_pcie, 0);
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ret = pcie_phy_poll_ack(imx6_pcie, false);
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if (ret)
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return ret;
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@ -285,7 +279,7 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
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static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
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{
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u32 tmp;
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u16 tmp;
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if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
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return;
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@ -455,7 +449,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
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* reset time is too short, cannot meet the requirement.
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* add one ~10us delay here.
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*/
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udelay(10);
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usleep_range(10, 100);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
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break;
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@ -488,20 +482,14 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
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static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
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{
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u32 val;
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unsigned int retries;
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struct device *dev = imx6_pcie->pci->dev;
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for (retries = 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES; retries++) {
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regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR22, &val);
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if (val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED)
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return;
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usleep_range(PHY_PLL_LOCK_WAIT_USLEEP_MIN,
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PHY_PLL_LOCK_WAIT_USLEEP_MAX);
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}
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dev_err(dev, "PCIe PLL lock timeout\n");
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if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
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IOMUXC_GPR22, val,
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val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED,
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PHY_PLL_LOCK_WAIT_USLEEP_MAX,
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PHY_PLL_LOCK_WAIT_TIMEOUT))
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dev_err(dev, "PCIe PLL lock timeout\n");
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}
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static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
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@ -687,7 +675,7 @@ static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
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{
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unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy);
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int mult, div;
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u32 val;
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u16 val;
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if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
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return 0;
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@ -730,21 +718,6 @@ static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
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return 0;
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}
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static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
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{
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struct dw_pcie *pci = imx6_pcie->pci;
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struct device *dev = pci->dev;
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/* check if the link is up or not */
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if (!dw_pcie_wait_for_link(pci))
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return 0;
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dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
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dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
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dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
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return -ETIMEDOUT;
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}
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static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
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{
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struct dw_pcie *pci = imx6_pcie->pci;
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@ -761,7 +734,7 @@ static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
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}
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dev_err(dev, "Speed change timeout\n");
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return -EINVAL;
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return -ETIMEDOUT;
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}
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static void imx6_pcie_ltssm_enable(struct device *dev)
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@ -803,7 +776,7 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
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/* Start LTSSM. */
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imx6_pcie_ltssm_enable(dev);
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ret = imx6_pcie_wait_for_link(imx6_pcie);
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ret = dw_pcie_wait_for_link(pci);
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if (ret)
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goto err_reset_phy;
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@ -841,7 +814,7 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
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}
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/* Make sure link training is finished as well! */
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ret = imx6_pcie_wait_for_link(imx6_pcie);
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ret = dw_pcie_wait_for_link(pci);
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if (ret) {
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dev_err(dev, "Failed to bring link up!\n");
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goto err_reset_phy;
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@ -856,8 +829,8 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
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err_reset_phy:
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dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
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dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
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dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
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dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),
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dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));
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imx6_pcie_reset_phy(imx6_pcie);
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return ret;
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}
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@ -993,17 +966,11 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
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}
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}
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static inline bool imx6_pcie_supports_suspend(struct imx6_pcie *imx6_pcie)
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{
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return (imx6_pcie->drvdata->variant == IMX7D ||
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imx6_pcie->drvdata->variant == IMX6SX);
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}
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static int imx6_pcie_suspend_noirq(struct device *dev)
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{
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struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
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if (!imx6_pcie_supports_suspend(imx6_pcie))
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if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
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return 0;
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imx6_pcie_pm_turnoff(imx6_pcie);
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@ -1019,7 +986,7 @@ static int imx6_pcie_resume_noirq(struct device *dev)
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struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
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struct pcie_port *pp = &imx6_pcie->pci->pp;
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if (!imx6_pcie_supports_suspend(imx6_pcie))
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if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
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return 0;
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imx6_pcie_assert_core_reset(imx6_pcie);
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@ -1249,7 +1216,8 @@ static const struct imx6_pcie_drvdata drvdata[] = {
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[IMX6SX] = {
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.variant = IMX6SX,
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.flags = IMX6_PCIE_FLAG_IMX6_PHY |
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IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
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IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
|
||||
IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
|
||||
},
|
||||
[IMX6QP] = {
|
||||
.variant = IMX6QP,
|
||||
@ -1258,6 +1226,7 @@ static const struct imx6_pcie_drvdata drvdata[] = {
|
||||
},
|
||||
[IMX7D] = {
|
||||
.variant = IMX7D,
|
||||
.flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
|
||||
},
|
||||
[IMX8MQ] = {
|
||||
.variant = IMX8MQ,
|
||||
|
||||
@ -14,12 +14,6 @@
|
||||
|
||||
#include "pcie-designware.h"
|
||||
|
||||
/* PCIe Port Logic registers */
|
||||
#define PLR_OFFSET 0x700
|
||||
#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
|
||||
#define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4)
|
||||
#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
|
||||
|
||||
int dw_pcie_read(void __iomem *addr, int size, u32 *val)
|
||||
{
|
||||
if (!IS_ALIGNED((uintptr_t)addr, size)) {
|
||||
@ -334,9 +328,9 @@ int dw_pcie_link_up(struct dw_pcie *pci)
|
||||
if (pci->ops->link_up)
|
||||
return pci->ops->link_up(pci);
|
||||
|
||||
val = readl(pci->dbi_base + PCIE_PHY_DEBUG_R1);
|
||||
return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
|
||||
(!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
|
||||
val = readl(pci->dbi_base + PCIE_PORT_DEBUG1);
|
||||
return ((val & PCIE_PORT_DEBUG1_LINK_UP) &&
|
||||
(!(val & PCIE_PORT_DEBUG1_LINK_IN_TRAINING)));
|
||||
}
|
||||
|
||||
void dw_pcie_setup(struct dw_pcie *pci)
|
||||
|
||||
@ -41,6 +41,9 @@
|
||||
#define PCIE_PORT_DEBUG0 0x728
|
||||
#define PORT_LOGIC_LTSSM_STATE_MASK 0x1f
|
||||
#define PORT_LOGIC_LTSSM_STATE_L0 0x11
|
||||
#define PCIE_PORT_DEBUG1 0x72C
|
||||
#define PCIE_PORT_DEBUG1_LINK_UP BIT(4)
|
||||
#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING BIT(29)
|
||||
|
||||
#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
|
||||
#define PORT_LOGIC_SPEED_CHANGE BIT(17)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user