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tg3: Qualify use of tp->pcix_cap
This patch makes sure the device is a PCIX device before attempting to use the pcix_cap device structure member. This is prep work for the following patch. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -5876,7 +5876,7 @@ static void tg3_restore_pci_state(struct tg3 *tp)
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}
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/* Make sure PCI-X relaxed ordering bit is clear. */
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if (tp->pcix_cap) {
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if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
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u16 pcix_cmd;
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pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
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@ -12190,6 +12190,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
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tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
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pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
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&pci_state_reg);
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pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
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if (pcie_cap != 0) {
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tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
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@ -12205,8 +12208,20 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
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tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
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}
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} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
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} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
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tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
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} else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
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(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
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tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
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if (!tp->pcix_cap) {
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printk(KERN_ERR PFX "Cannot find PCI-X "
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"capability, aborting.\n");
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return -EIO;
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}
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if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
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tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
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}
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/* If we have an AMD 762 or VIA K8T800 chipset, write
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* reordering to the mailbox registers done by the host
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@ -12231,29 +12246,18 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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cacheline_sz_reg);
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}
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if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
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(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
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tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
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if (!tp->pcix_cap) {
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printk(KERN_ERR PFX "Cannot find PCI-X "
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"capability, aborting.\n");
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return -EIO;
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}
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}
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if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
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/* 5700 BX chips need to have their TX producer index
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* mailboxes written twice to workaround a bug.
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*/
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tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
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pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
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&pci_state_reg);
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if (tp->pcix_cap && (pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
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tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
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/* If this is a 5700 BX chipset, and we are in PCI-X
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* mode, enable register write workaround.
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/* If we are in PCI-X mode, enable register write workaround.
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*
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* The workaround is to use indirect register accesses
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* for all chip writes not to mailbox registers.
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*/
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if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
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if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
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u32 pm_reg;
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tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
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@ -12278,12 +12282,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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}
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}
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/* 5700 BX chips need to have their TX producer index mailboxes
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* written twice to workaround a bug.
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*/
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if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
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tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
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if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
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tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
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if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
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