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ARM: at91: PIT: Follow the general coding rules
Replace all masks and bits definitions by matching calls to BIT and GENMASK. While we're at it, also fix a few style issues. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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@ -9,11 +9,12 @@
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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@ -22,17 +23,17 @@
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#include <mach/hardware.h>
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#define AT91_PIT_MR 0x00 /* Mode Register */
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#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
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#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
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#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
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#define AT91_PIT_PITIEN BIT(25) /* Timer Interrupt Enable */
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#define AT91_PIT_PITEN BIT(24) /* Timer Enabled */
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#define AT91_PIT_PIV GENMASK(19, 0) /* Periodic Interval Value */
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#define AT91_PIT_SR 0x04 /* Status Register */
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#define AT91_PIT_PITS (1 << 0) /* Timer Status */
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#define AT91_PIT_PITS BIT(0) /* Timer Status */
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#define AT91_PIT_PIVR 0x08 /* Periodic Interval Value Register */
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#define AT91_PIT_PIIR 0x0c /* Periodic Interval Image Register */
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#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
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#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
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#define AT91_PIT_PICNT GENMASK(31, 20) /* Interval Counter */
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#define AT91_PIT_CPIV GENMASK(19, 0) /* Inverval Value */
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#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
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#define PIT_PICNT(x) (((x) & AT91_PIT_PICNT) >> 20)
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