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Merge branch '1GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/t
nguy/next-queue Tony Nguyen says: ==================== 1GbE Intel Wired LAN Driver Updates 2021-07-16 Vinicius Costa Gomes says: Add support for steering traffic to specific RX queues using Flex Filters. As the name implies, Flex Filters are more flexible than using Layer-2, VLAN or MAC address filters, one of the reasons is that they allow "AND" operations more easily, e.g. when the user wants to steer some traffic based on the source MAC address and the packet ethertype. Future work include adding support for offloading tc-u32 filters to the hardware. The series is divided as follows: Patch 1/5, add the low level primitives for configuring Flex filters. Patch 2/5 and 3/5, allow ethtool to manage Flex filters. Patch 4/5, when specifying filters that have multiple predicates, use Flex filters. Patch 5/5, Adds support for exposing the i225 LEDs using the LED subsystem. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
5242b0c6b5
@ -335,6 +335,7 @@ config IGC
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tristate "Intel(R) Ethernet Controller I225-LM/I225-V support"
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default n
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depends on PCI
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depends on LEDS_CLASS
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help
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This driver supports Intel(R) Ethernet Controller I225-LM/I225-V
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family of adapters.
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@ -13,6 +13,7 @@
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#include <linux/ptp_clock_kernel.h>
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#include <linux/timecounter.h>
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#include <linux/net_tstamp.h>
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#include <linux/leds.h>
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#include "igc_hw.h"
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@ -33,6 +34,8 @@ void igc_ethtool_set_ops(struct net_device *);
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#define IGC_N_PEROUT 2
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#define IGC_N_SDP 4
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#define MAX_FLEX_FILTER 32
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enum igc_mac_filter_type {
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IGC_MAC_FILTER_TYPE_DST = 0,
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IGC_MAC_FILTER_TYPE_SRC
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@ -237,8 +240,17 @@ struct igc_adapter {
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struct timespec64 start;
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struct timespec64 period;
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} perout[IGC_N_PEROUT];
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/* LEDs */
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struct mutex led_mutex;
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struct led_classdev led0;
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struct led_classdev led1;
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struct led_classdev led2;
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};
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#define led_to_igc(ldev, led) \
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container_of(ldev, struct igc_adapter, led)
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void igc_up(struct igc_adapter *adapter);
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void igc_down(struct igc_adapter *adapter);
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int igc_open(struct net_device *netdev);
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@ -476,18 +488,28 @@ struct igc_q_vector {
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};
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enum igc_filter_match_flags {
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IGC_FILTER_FLAG_ETHER_TYPE = 0x1,
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IGC_FILTER_FLAG_VLAN_TCI = 0x2,
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IGC_FILTER_FLAG_SRC_MAC_ADDR = 0x4,
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IGC_FILTER_FLAG_DST_MAC_ADDR = 0x8,
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IGC_FILTER_FLAG_ETHER_TYPE = BIT(0),
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IGC_FILTER_FLAG_VLAN_TCI = BIT(1),
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IGC_FILTER_FLAG_SRC_MAC_ADDR = BIT(2),
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IGC_FILTER_FLAG_DST_MAC_ADDR = BIT(3),
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IGC_FILTER_FLAG_USER_DATA = BIT(4),
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IGC_FILTER_FLAG_VLAN_ETYPE = BIT(5),
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};
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struct igc_nfc_filter {
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u8 match_flags;
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u16 etype;
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__be16 vlan_etype;
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u16 vlan_tci;
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u8 src_addr[ETH_ALEN];
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u8 dst_addr[ETH_ALEN];
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u8 user_data[8];
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u8 user_mask[8];
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u8 flex_index;
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u8 rx_queue;
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u8 prio;
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u8 immediate_irq;
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u8 drop;
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};
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struct igc_nfc_rule {
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@ -495,12 +517,24 @@ struct igc_nfc_rule {
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struct igc_nfc_filter filter;
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u32 location;
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u16 action;
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bool flex;
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};
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/* IGC supports a total of 32 NFC rules: 16 MAC address based,, 8 VLAN priority
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* based, and 8 ethertype based.
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/* IGC supports a total of 32 NFC rules: 16 MAC address based, 8 VLAN priority
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* based, 8 ethertype based and 32 Flex filter based rules.
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*/
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#define IGC_MAX_RXNFC_RULES 32
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#define IGC_MAX_RXNFC_RULES 64
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struct igc_flex_filter {
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u8 index;
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u8 data[128];
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u8 mask[16];
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u8 length;
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u8 rx_queue;
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u8 prio;
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u8 immediate_irq;
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u8 drop;
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};
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/* igc_desc_unused - calculate if we have unused descriptors */
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static inline u16 igc_desc_unused(const struct igc_ring *ring)
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@ -17,11 +17,22 @@
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#define IGC_WUC_PME_EN 0x00000002 /* PME Enable */
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/* Wake Up Filter Control */
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#define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
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#define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
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#define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
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#define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
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#define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
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#define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
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#define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
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#define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
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#define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
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#define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
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#define IGC_WUFC_FLEX_HQ BIT(14) /* Flex Filters Host Queuing */
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#define IGC_WUFC_FLX0 BIT(16) /* Flexible Filter 0 Enable */
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#define IGC_WUFC_FLX1 BIT(17) /* Flexible Filter 1 Enable */
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#define IGC_WUFC_FLX2 BIT(18) /* Flexible Filter 2 Enable */
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#define IGC_WUFC_FLX3 BIT(19) /* Flexible Filter 3 Enable */
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#define IGC_WUFC_FLX4 BIT(20) /* Flexible Filter 4 Enable */
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#define IGC_WUFC_FLX5 BIT(21) /* Flexible Filter 5 Enable */
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#define IGC_WUFC_FLX6 BIT(22) /* Flexible Filter 6 Enable */
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#define IGC_WUFC_FLX7 BIT(23) /* Flexible Filter 7 Enable */
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#define IGC_WUFC_FILTER_MASK GENMASK(23, 14)
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#define IGC_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */
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@ -46,6 +57,37 @@
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/* Wake Up Packet Memory stores the first 128 bytes of the wake up packet */
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#define IGC_WUPM_BYTES 128
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/* Wakeup Filter Control Extended */
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#define IGC_WUFC_EXT_FLX8 BIT(8) /* Flexible Filter 8 Enable */
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#define IGC_WUFC_EXT_FLX9 BIT(9) /* Flexible Filter 9 Enable */
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#define IGC_WUFC_EXT_FLX10 BIT(10) /* Flexible Filter 10 Enable */
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#define IGC_WUFC_EXT_FLX11 BIT(11) /* Flexible Filter 11 Enable */
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#define IGC_WUFC_EXT_FLX12 BIT(12) /* Flexible Filter 12 Enable */
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#define IGC_WUFC_EXT_FLX13 BIT(13) /* Flexible Filter 13 Enable */
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#define IGC_WUFC_EXT_FLX14 BIT(14) /* Flexible Filter 14 Enable */
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#define IGC_WUFC_EXT_FLX15 BIT(15) /* Flexible Filter 15 Enable */
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#define IGC_WUFC_EXT_FLX16 BIT(16) /* Flexible Filter 16 Enable */
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#define IGC_WUFC_EXT_FLX17 BIT(17) /* Flexible Filter 17 Enable */
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#define IGC_WUFC_EXT_FLX18 BIT(18) /* Flexible Filter 18 Enable */
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#define IGC_WUFC_EXT_FLX19 BIT(19) /* Flexible Filter 19 Enable */
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#define IGC_WUFC_EXT_FLX20 BIT(20) /* Flexible Filter 20 Enable */
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#define IGC_WUFC_EXT_FLX21 BIT(21) /* Flexible Filter 21 Enable */
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#define IGC_WUFC_EXT_FLX22 BIT(22) /* Flexible Filter 22 Enable */
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#define IGC_WUFC_EXT_FLX23 BIT(23) /* Flexible Filter 23 Enable */
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#define IGC_WUFC_EXT_FLX24 BIT(24) /* Flexible Filter 24 Enable */
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#define IGC_WUFC_EXT_FLX25 BIT(25) /* Flexible Filter 25 Enable */
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#define IGC_WUFC_EXT_FLX26 BIT(26) /* Flexible Filter 26 Enable */
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#define IGC_WUFC_EXT_FLX27 BIT(27) /* Flexible Filter 27 Enable */
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#define IGC_WUFC_EXT_FLX28 BIT(28) /* Flexible Filter 28 Enable */
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#define IGC_WUFC_EXT_FLX29 BIT(29) /* Flexible Filter 29 Enable */
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#define IGC_WUFC_EXT_FLX30 BIT(30) /* Flexible Filter 30 Enable */
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#define IGC_WUFC_EXT_FLX31 BIT(31) /* Flexible Filter 31 Enable */
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#define IGC_WUFC_EXT_FILTER_MASK GENMASK(31, 8)
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/* Physical Func Reset Done Indication */
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#define IGC_CTRL_EXT_LINK_MODE_MASK 0x00C00000
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/* Loop limit on how long we wait for auto-negotiation to complete */
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#define COPPER_LINK_UP_LIMIT 10
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#define PHY_AUTO_NEG_LIMIT 45
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@ -102,6 +144,16 @@
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#define IGC_CTRL_SDP0_DIR 0x00400000 /* SDP0 Data direction */
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#define IGC_CTRL_SDP1_DIR 0x00800000 /* SDP1 Data direction */
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/* LED Control */
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#define IGC_LEDCTL_LED0_MODE_SHIFT 0
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#define IGC_LEDCTL_LED0_MODE_MASK GENMASK(3, 0)
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#define IGC_LEDCTL_LED1_MODE_SHIFT 8
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#define IGC_LEDCTL_LED1_MODE_MASK GENMASK(11, 8)
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#define IGC_LEDCTL_LED2_MODE_SHIFT 16
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#define IGC_LEDCTL_LED2_MODE_MASK GENMASK(19, 16)
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#define IGC_CONNSW_AUTOSENSE_EN 0x1
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/* As per the EAS the maximum supported size is 9.5KB (9728 bytes) */
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#define MAX_JUMBO_FRAME_SIZE 0x2600
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@ -979,6 +979,12 @@ static int igc_ethtool_get_nfc_rule(struct igc_adapter *adapter,
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eth_broadcast_addr(fsp->m_u.ether_spec.h_source);
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}
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if (rule->filter.match_flags & IGC_FILTER_FLAG_USER_DATA) {
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fsp->flow_type |= FLOW_EXT;
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memcpy(fsp->h_ext.data, rule->filter.user_data, sizeof(fsp->h_ext.data));
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memcpy(fsp->m_ext.data, rule->filter.user_mask, sizeof(fsp->m_ext.data));
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}
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mutex_unlock(&adapter->nfc_rule_lock);
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return 0;
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@ -1215,6 +1221,30 @@ static void igc_ethtool_init_nfc_rule(struct igc_nfc_rule *rule,
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ether_addr_copy(rule->filter.dst_addr,
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fsp->h_u.ether_spec.h_dest);
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}
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/* VLAN etype matching */
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if ((fsp->flow_type & FLOW_EXT) && fsp->h_ext.vlan_etype) {
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rule->filter.vlan_etype = fsp->h_ext.vlan_etype;
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rule->filter.match_flags |= IGC_FILTER_FLAG_VLAN_ETYPE;
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}
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/* Check for user defined data */
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if ((fsp->flow_type & FLOW_EXT) &&
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(fsp->h_ext.data[0] || fsp->h_ext.data[1])) {
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rule->filter.match_flags |= IGC_FILTER_FLAG_USER_DATA;
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memcpy(rule->filter.user_data, fsp->h_ext.data, sizeof(fsp->h_ext.data));
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memcpy(rule->filter.user_mask, fsp->m_ext.data, sizeof(fsp->m_ext.data));
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}
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/* When multiple filter options or user data or vlan etype is set, use a
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* flex filter.
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*/
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if ((rule->filter.match_flags & IGC_FILTER_FLAG_USER_DATA) ||
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(rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_ETYPE) ||
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(rule->filter.match_flags & (rule->filter.match_flags - 1)))
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rule->flex = true;
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else
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rule->flex = false;
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}
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/**
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@ -1244,11 +1274,6 @@ static int igc_ethtool_check_nfc_rule(struct igc_adapter *adapter,
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return -EINVAL;
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}
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if (flags & (flags - 1)) {
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netdev_dbg(dev, "Rule with multiple matches not supported\n");
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return -EOPNOTSUPP;
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}
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list_for_each_entry(tmp, &adapter->nfc_rule_list, list) {
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if (!memcmp(&rule->filter, &tmp->filter,
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sizeof(rule->filter)) &&
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@ -1280,12 +1305,6 @@ static int igc_ethtool_add_nfc_rule(struct igc_adapter *adapter,
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return -EOPNOTSUPP;
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}
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if ((fsp->flow_type & FLOW_EXT) &&
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fsp->m_ext.vlan_tci != htons(VLAN_PRIO_MASK)) {
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netdev_dbg(netdev, "VLAN mask not supported\n");
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return -EOPNOTSUPP;
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}
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if (fsp->ring_cookie >= adapter->num_rx_queues) {
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netdev_dbg(netdev, "Invalid action\n");
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return -EINVAL;
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@ -3075,11 +3075,320 @@ static void igc_del_etype_filter(struct igc_adapter *adapter, u16 etype)
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etype);
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}
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static int igc_flex_filter_select(struct igc_adapter *adapter,
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struct igc_flex_filter *input,
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u32 *fhft)
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{
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struct igc_hw *hw = &adapter->hw;
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u8 fhft_index;
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u32 fhftsl;
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if (input->index >= MAX_FLEX_FILTER) {
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dev_err(&adapter->pdev->dev, "Wrong Flex Filter index selected!\n");
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return -EINVAL;
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}
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/* Indirect table select register */
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fhftsl = rd32(IGC_FHFTSL);
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fhftsl &= ~IGC_FHFTSL_FTSL_MASK;
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switch (input->index) {
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case 0 ... 7:
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fhftsl |= 0x00;
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break;
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case 8 ... 15:
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fhftsl |= 0x01;
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break;
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case 16 ... 23:
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fhftsl |= 0x02;
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break;
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case 24 ... 31:
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fhftsl |= 0x03;
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break;
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}
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wr32(IGC_FHFTSL, fhftsl);
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/* Normalize index down to host table register */
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fhft_index = input->index % 8;
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*fhft = (fhft_index < 4) ? IGC_FHFT(fhft_index) :
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IGC_FHFT_EXT(fhft_index - 4);
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return 0;
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}
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static int igc_write_flex_filter_ll(struct igc_adapter *adapter,
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struct igc_flex_filter *input)
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{
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struct device *dev = &adapter->pdev->dev;
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struct igc_hw *hw = &adapter->hw;
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u8 *data = input->data;
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u8 *mask = input->mask;
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u32 queuing;
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u32 fhft;
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u32 wufc;
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int ret;
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int i;
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/* Length has to be aligned to 8. Otherwise the filter will fail. Bail
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* out early to avoid surprises later.
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*/
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if (input->length % 8 != 0) {
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dev_err(dev, "The length of a flex filter has to be 8 byte aligned!\n");
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return -EINVAL;
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}
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/* Select corresponding flex filter register and get base for host table. */
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ret = igc_flex_filter_select(adapter, input, &fhft);
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if (ret)
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return ret;
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/* When adding a filter globally disable flex filter feature. That is
|
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* recommended within the datasheet.
|
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*/
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wufc = rd32(IGC_WUFC);
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wufc &= ~IGC_WUFC_FLEX_HQ;
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wr32(IGC_WUFC, wufc);
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/* Configure filter */
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queuing = input->length & IGC_FHFT_LENGTH_MASK;
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queuing |= (input->rx_queue << IGC_FHFT_QUEUE_SHIFT) & IGC_FHFT_QUEUE_MASK;
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queuing |= (input->prio << IGC_FHFT_PRIO_SHIFT) & IGC_FHFT_PRIO_MASK;
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if (input->immediate_irq)
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queuing |= IGC_FHFT_IMM_INT;
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if (input->drop)
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queuing |= IGC_FHFT_DROP;
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wr32(fhft + 0xFC, queuing);
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/* Write data (128 byte) and mask (128 bit) */
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for (i = 0; i < 16; ++i) {
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const size_t data_idx = i * 8;
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const size_t row_idx = i * 16;
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u32 dw0 =
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(data[data_idx + 0] << 0) |
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(data[data_idx + 1] << 8) |
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(data[data_idx + 2] << 16) |
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(data[data_idx + 3] << 24);
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u32 dw1 =
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(data[data_idx + 4] << 0) |
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(data[data_idx + 5] << 8) |
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(data[data_idx + 6] << 16) |
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(data[data_idx + 7] << 24);
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u32 tmp;
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/* Write row: dw0, dw1 and mask */
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wr32(fhft + row_idx, dw0);
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wr32(fhft + row_idx + 4, dw1);
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/* mask is only valid for MASK(7, 0) */
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tmp = rd32(fhft + row_idx + 8);
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tmp &= ~GENMASK(7, 0);
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tmp |= mask[i];
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wr32(fhft + row_idx + 8, tmp);
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}
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|
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/* Enable filter. */
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wufc |= IGC_WUFC_FLEX_HQ;
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if (input->index > 8) {
|
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/* Filter 0-7 are enabled via WUFC. The other 24 filters are not. */
|
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u32 wufc_ext = rd32(IGC_WUFC_EXT);
|
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|
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wufc_ext |= (IGC_WUFC_EXT_FLX8 << (input->index - 8));
|
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wr32(IGC_WUFC_EXT, wufc_ext);
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} else {
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wufc |= (IGC_WUFC_FLX0 << input->index);
|
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}
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wr32(IGC_WUFC, wufc);
|
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|
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dev_dbg(&adapter->pdev->dev, "Added flex filter %u to HW.\n",
|
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input->index);
|
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|
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return 0;
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}
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|
||||
static void igc_flex_filter_add_field(struct igc_flex_filter *flex,
|
||||
const void *src, unsigned int offset,
|
||||
size_t len, const void *mask)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* data */
|
||||
memcpy(&flex->data[offset], src, len);
|
||||
|
||||
/* mask */
|
||||
for (i = 0; i < len; ++i) {
|
||||
const unsigned int idx = i + offset;
|
||||
const u8 *ptr = mask;
|
||||
|
||||
if (mask) {
|
||||
if (ptr[i] & 0xff)
|
||||
flex->mask[idx / 8] |= BIT(idx % 8);
|
||||
|
||||
continue;
|
||||
}
|
||||
|
||||
flex->mask[idx / 8] |= BIT(idx % 8);
|
||||
}
|
||||
}
|
||||
|
||||
static int igc_find_avail_flex_filter_slot(struct igc_adapter *adapter)
|
||||
{
|
||||
struct igc_hw *hw = &adapter->hw;
|
||||
u32 wufc, wufc_ext;
|
||||
int i;
|
||||
|
||||
wufc = rd32(IGC_WUFC);
|
||||
wufc_ext = rd32(IGC_WUFC_EXT);
|
||||
|
||||
for (i = 0; i < MAX_FLEX_FILTER; i++) {
|
||||
if (i < 8) {
|
||||
if (!(wufc & (IGC_WUFC_FLX0 << i)))
|
||||
return i;
|
||||
} else {
|
||||
if (!(wufc_ext & (IGC_WUFC_EXT_FLX8 << (i - 8))))
|
||||
return i;
|
||||
}
|
||||
}
|
||||
|
||||
return -ENOSPC;
|
||||
}
|
||||
|
||||
static bool igc_flex_filter_in_use(struct igc_adapter *adapter)
|
||||
{
|
||||
struct igc_hw *hw = &adapter->hw;
|
||||
u32 wufc, wufc_ext;
|
||||
|
||||
wufc = rd32(IGC_WUFC);
|
||||
wufc_ext = rd32(IGC_WUFC_EXT);
|
||||
|
||||
if (wufc & IGC_WUFC_FILTER_MASK)
|
||||
return true;
|
||||
|
||||
if (wufc_ext & IGC_WUFC_EXT_FILTER_MASK)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int igc_add_flex_filter(struct igc_adapter *adapter,
|
||||
struct igc_nfc_rule *rule)
|
||||
{
|
||||
struct igc_flex_filter flex = { };
|
||||
struct igc_nfc_filter *filter = &rule->filter;
|
||||
unsigned int eth_offset, user_offset;
|
||||
int ret, index;
|
||||
bool vlan;
|
||||
|
||||
index = igc_find_avail_flex_filter_slot(adapter);
|
||||
if (index < 0)
|
||||
return -ENOSPC;
|
||||
|
||||
/* Construct the flex filter:
|
||||
* -> dest_mac [6]
|
||||
* -> src_mac [6]
|
||||
* -> tpid [2]
|
||||
* -> vlan tci [2]
|
||||
* -> ether type [2]
|
||||
* -> user data [8]
|
||||
* -> = 26 bytes => 32 length
|
||||
*/
|
||||
flex.index = index;
|
||||
flex.length = 32;
|
||||
flex.rx_queue = rule->action;
|
||||
|
||||
vlan = rule->filter.vlan_tci || rule->filter.vlan_etype;
|
||||
eth_offset = vlan ? 16 : 12;
|
||||
user_offset = vlan ? 18 : 14;
|
||||
|
||||
/* Add destination MAC */
|
||||
if (rule->filter.match_flags & IGC_FILTER_FLAG_DST_MAC_ADDR)
|
||||
igc_flex_filter_add_field(&flex, &filter->dst_addr, 0,
|
||||
ETH_ALEN, NULL);
|
||||
|
||||
/* Add source MAC */
|
||||
if (rule->filter.match_flags & IGC_FILTER_FLAG_SRC_MAC_ADDR)
|
||||
igc_flex_filter_add_field(&flex, &filter->src_addr, 6,
|
||||
ETH_ALEN, NULL);
|
||||
|
||||
/* Add VLAN etype */
|
||||
if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_ETYPE)
|
||||
igc_flex_filter_add_field(&flex, &filter->vlan_etype, 12,
|
||||
sizeof(filter->vlan_etype),
|
||||
NULL);
|
||||
|
||||
/* Add VLAN TCI */
|
||||
if (rule->filter.match_flags & IGC_FILTER_FLAG_VLAN_TCI)
|
||||
igc_flex_filter_add_field(&flex, &filter->vlan_tci, 14,
|
||||
sizeof(filter->vlan_tci), NULL);
|
||||
|
||||
/* Add Ether type */
|
||||
if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE) {
|
||||
__be16 etype = cpu_to_be16(filter->etype);
|
||||
|
||||
igc_flex_filter_add_field(&flex, &etype, eth_offset,
|
||||
sizeof(etype), NULL);
|
||||
}
|
||||
|
||||
/* Add user data */
|
||||
if (rule->filter.match_flags & IGC_FILTER_FLAG_USER_DATA)
|
||||
igc_flex_filter_add_field(&flex, &filter->user_data,
|
||||
user_offset,
|
||||
sizeof(filter->user_data),
|
||||
filter->user_mask);
|
||||
|
||||
/* Add it down to the hardware and enable it. */
|
||||
ret = igc_write_flex_filter_ll(adapter, &flex);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
filter->flex_index = index;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void igc_del_flex_filter(struct igc_adapter *adapter,
|
||||
u16 reg_index)
|
||||
{
|
||||
struct igc_hw *hw = &adapter->hw;
|
||||
u32 wufc;
|
||||
|
||||
/* Just disable the filter. The filter table itself is kept
|
||||
* intact. Another flex_filter_add() should override the "old" data
|
||||
* then.
|
||||
*/
|
||||
if (reg_index > 8) {
|
||||
u32 wufc_ext = rd32(IGC_WUFC_EXT);
|
||||
|
||||
wufc_ext &= ~(IGC_WUFC_EXT_FLX8 << (reg_index - 8));
|
||||
wr32(IGC_WUFC_EXT, wufc_ext);
|
||||
} else {
|
||||
wufc = rd32(IGC_WUFC);
|
||||
|
||||
wufc &= ~(IGC_WUFC_FLX0 << reg_index);
|
||||
wr32(IGC_WUFC, wufc);
|
||||
}
|
||||
|
||||
if (igc_flex_filter_in_use(adapter))
|
||||
return;
|
||||
|
||||
/* No filters are in use, we may disable flex filters */
|
||||
wufc = rd32(IGC_WUFC);
|
||||
wufc &= ~IGC_WUFC_FLEX_HQ;
|
||||
wr32(IGC_WUFC, wufc);
|
||||
}
|
||||
|
||||
static int igc_enable_nfc_rule(struct igc_adapter *adapter,
|
||||
const struct igc_nfc_rule *rule)
|
||||
struct igc_nfc_rule *rule)
|
||||
{
|
||||
int err;
|
||||
|
||||
if (rule->flex) {
|
||||
return igc_add_flex_filter(adapter, rule);
|
||||
}
|
||||
|
||||
if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE) {
|
||||
err = igc_add_etype_filter(adapter, rule->filter.etype,
|
||||
rule->action);
|
||||
@ -3116,6 +3425,11 @@ static int igc_enable_nfc_rule(struct igc_adapter *adapter,
|
||||
static void igc_disable_nfc_rule(struct igc_adapter *adapter,
|
||||
const struct igc_nfc_rule *rule)
|
||||
{
|
||||
if (rule->flex) {
|
||||
igc_del_flex_filter(adapter, rule->filter.flex_index);
|
||||
return;
|
||||
}
|
||||
|
||||
if (rule->filter.match_flags & IGC_FILTER_FLAG_ETHER_TYPE)
|
||||
igc_del_etype_filter(adapter, rule->filter.etype);
|
||||
|
||||
@ -5816,6 +6130,134 @@ err_inval:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static void igc_select_led(struct igc_adapter *adapter, int led,
|
||||
u32 *mask, u32 *shift)
|
||||
{
|
||||
switch (led) {
|
||||
case 0:
|
||||
*mask = IGC_LEDCTL_LED0_MODE_MASK;
|
||||
*shift = IGC_LEDCTL_LED0_MODE_SHIFT;
|
||||
break;
|
||||
case 1:
|
||||
*mask = IGC_LEDCTL_LED1_MODE_MASK;
|
||||
*shift = IGC_LEDCTL_LED1_MODE_SHIFT;
|
||||
break;
|
||||
case 2:
|
||||
*mask = IGC_LEDCTL_LED2_MODE_MASK;
|
||||
*shift = IGC_LEDCTL_LED2_MODE_SHIFT;
|
||||
break;
|
||||
default:
|
||||
*mask = *shift = 0;
|
||||
dev_err(&adapter->pdev->dev, "Unknown led %d selected!", led);
|
||||
}
|
||||
}
|
||||
|
||||
static void igc_led_set(struct igc_adapter *adapter, int led, u16 brightness)
|
||||
{
|
||||
struct igc_hw *hw = &adapter->hw;
|
||||
u32 shift, mask, ledctl;
|
||||
|
||||
igc_select_led(adapter, led, &mask, &shift);
|
||||
|
||||
mutex_lock(&adapter->led_mutex);
|
||||
ledctl = rd32(IGC_LEDCTL);
|
||||
ledctl &= ~mask;
|
||||
ledctl |= brightness << shift;
|
||||
wr32(IGC_LEDCTL, ledctl);
|
||||
mutex_unlock(&adapter->led_mutex);
|
||||
}
|
||||
|
||||
static enum led_brightness igc_led_get(struct igc_adapter *adapter, int led)
|
||||
{
|
||||
struct igc_hw *hw = &adapter->hw;
|
||||
u32 shift, mask, ledctl;
|
||||
|
||||
igc_select_led(adapter, led, &mask, &shift);
|
||||
|
||||
mutex_lock(&adapter->led_mutex);
|
||||
ledctl = rd32(IGC_LEDCTL);
|
||||
mutex_unlock(&adapter->led_mutex);
|
||||
|
||||
return (ledctl & mask) >> shift;
|
||||
}
|
||||
|
||||
static void igc_led0_set(struct led_classdev *ldev, enum led_brightness b)
|
||||
{
|
||||
struct igc_adapter *adapter = led_to_igc(ldev, led0);
|
||||
|
||||
igc_led_set(adapter, 0, b);
|
||||
}
|
||||
|
||||
static enum led_brightness igc_led0_get(struct led_classdev *ldev)
|
||||
{
|
||||
struct igc_adapter *adapter = led_to_igc(ldev, led0);
|
||||
|
||||
return igc_led_get(adapter, 0);
|
||||
}
|
||||
|
||||
static void igc_led1_set(struct led_classdev *ldev, enum led_brightness b)
|
||||
{
|
||||
struct igc_adapter *adapter = led_to_igc(ldev, led1);
|
||||
|
||||
igc_led_set(adapter, 1, b);
|
||||
}
|
||||
|
||||
static enum led_brightness igc_led1_get(struct led_classdev *ldev)
|
||||
{
|
||||
struct igc_adapter *adapter = led_to_igc(ldev, led1);
|
||||
|
||||
return igc_led_get(adapter, 1);
|
||||
}
|
||||
|
||||
static void igc_led2_set(struct led_classdev *ldev, enum led_brightness b)
|
||||
{
|
||||
struct igc_adapter *adapter = led_to_igc(ldev, led2);
|
||||
|
||||
igc_led_set(adapter, 2, b);
|
||||
}
|
||||
|
||||
static enum led_brightness igc_led2_get(struct led_classdev *ldev)
|
||||
{
|
||||
struct igc_adapter *adapter = led_to_igc(ldev, led2);
|
||||
|
||||
return igc_led_get(adapter, 2);
|
||||
}
|
||||
|
||||
static int igc_led_setup(struct igc_adapter *adapter)
|
||||
{
|
||||
/* Setup */
|
||||
mutex_init(&adapter->led_mutex);
|
||||
|
||||
adapter->led0.name = "igc_led0";
|
||||
adapter->led0.max_brightness = 15;
|
||||
adapter->led0.brightness_set = igc_led0_set;
|
||||
adapter->led0.brightness_get = igc_led0_get;
|
||||
|
||||
adapter->led1.name = "igc_led1";
|
||||
adapter->led1.max_brightness = 15;
|
||||
adapter->led1.brightness_set = igc_led1_set;
|
||||
adapter->led1.brightness_get = igc_led1_get;
|
||||
|
||||
adapter->led2.name = "igc_led2";
|
||||
adapter->led2.max_brightness = 15;
|
||||
adapter->led2.brightness_set = igc_led2_set;
|
||||
adapter->led2.brightness_get = igc_led2_get;
|
||||
|
||||
/* Register leds */
|
||||
led_classdev_register(&adapter->pdev->dev, &adapter->led0);
|
||||
led_classdev_register(&adapter->pdev->dev, &adapter->led1);
|
||||
led_classdev_register(&adapter->pdev->dev, &adapter->led2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void igc_led_destroy(struct igc_adapter *adapter)
|
||||
{
|
||||
led_classdev_unregister(&adapter->led0);
|
||||
led_classdev_unregister(&adapter->led1);
|
||||
led_classdev_unregister(&adapter->led2);
|
||||
}
|
||||
|
||||
/**
|
||||
* igc_probe - Device Initialization Routine
|
||||
* @pdev: PCI device information struct
|
||||
@ -6043,6 +6485,8 @@ static int igc_probe(struct pci_dev *pdev,
|
||||
|
||||
pm_runtime_put_noidle(&pdev->dev);
|
||||
|
||||
igc_led_setup(adapter);
|
||||
|
||||
return 0;
|
||||
|
||||
err_register:
|
||||
@ -6084,6 +6528,8 @@ static void igc_remove(struct pci_dev *pdev)
|
||||
|
||||
igc_ptp_stop(adapter);
|
||||
|
||||
igc_led_destroy(adapter);
|
||||
|
||||
set_bit(__IGC_DOWN, &adapter->state);
|
||||
|
||||
del_timer_sync(&adapter->watchdog_timer);
|
||||
|
||||
@ -10,6 +10,8 @@
|
||||
#define IGC_EECD 0x00010 /* EEPROM/Flash Control - RW */
|
||||
#define IGC_CTRL_EXT 0x00018 /* Extended Device Control - RW */
|
||||
#define IGC_MDIC 0x00020 /* MDI Control - RW */
|
||||
#define IGC_LEDCTL 0x00E00 /* LED Control - RW */
|
||||
#define IGC_MDICNFG 0x00E04 /* MDC/MDIO Configuration - RW */
|
||||
#define IGC_CONNSW 0x00034 /* Copper/Fiber switch control - RW */
|
||||
#define IGC_VET 0x00038 /* VLAN Ether Type - RW */
|
||||
#define IGC_I225_PHPM 0x00E14 /* I225 PHY Power Management */
|
||||
@ -67,6 +69,9 @@
|
||||
|
||||
/* Filtering Registers */
|
||||
#define IGC_ETQF(_n) (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
|
||||
#define IGC_FHFT(_n) (0x09000 + (256 * (_n))) /* Flexible Host Filter */
|
||||
#define IGC_FHFT_EXT(_n) (0x09A00 + (256 * (_n))) /* Flexible Host Filter Extended */
|
||||
#define IGC_FHFTSL 0x05804 /* Flex Filter indirect table select */
|
||||
|
||||
/* ETQF register bit definitions */
|
||||
#define IGC_ETQF_FILTER_ENABLE BIT(26)
|
||||
@ -75,6 +80,19 @@
|
||||
#define IGC_ETQF_QUEUE_MASK 0x00070000
|
||||
#define IGC_ETQF_ETYPE_MASK 0x0000FFFF
|
||||
|
||||
/* FHFT register bit definitions */
|
||||
#define IGC_FHFT_LENGTH_MASK GENMASK(7, 0)
|
||||
#define IGC_FHFT_QUEUE_SHIFT 8
|
||||
#define IGC_FHFT_QUEUE_MASK GENMASK(10, 8)
|
||||
#define IGC_FHFT_PRIO_SHIFT 16
|
||||
#define IGC_FHFT_PRIO_MASK GENMASK(18, 16)
|
||||
#define IGC_FHFT_IMM_INT BIT(24)
|
||||
#define IGC_FHFT_DROP BIT(25)
|
||||
|
||||
/* FHFTSL register bit definitions */
|
||||
#define IGC_FHFTSL_FTSL_SHIFT 0
|
||||
#define IGC_FHFTSL_FTSL_MASK GENMASK(1, 0)
|
||||
|
||||
/* Redirection Table - RW Array */
|
||||
#define IGC_RETA(_i) (0x05C00 + ((_i) * 4))
|
||||
/* RSS Random Key - RW Array */
|
||||
@ -240,6 +258,7 @@
|
||||
#define IGC_WUFC 0x05808 /* Wakeup Filter Control - RW */
|
||||
#define IGC_WUS 0x05810 /* Wakeup Status - R/W1C */
|
||||
#define IGC_WUPL 0x05900 /* Wakeup Packet Length - RW */
|
||||
#define IGC_WUFC_EXT 0x0580C /* Wakeup Filter Control Register Extended - RW */
|
||||
|
||||
/* Wake Up packet memory */
|
||||
#define IGC_WUPM_REG(_i) (0x05A00 + ((_i) * 4))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user