korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-12-16 07:24:39 +08:00
Code Issues Packages Projects Releases Wiki Activity

clk: mediatek: update clock driver of MT2712

Browse Source 
According to 3rd ECO design change,
1. Add new fixed factor clock of audio.
2. Add the parent clocks for audio clock mux.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Weiyi Lu 2018-12-14 10:04:17 +08:00 committed by Stephen Boyd
parent c3424f59a0
commit 51ff86dd10
1 changed files with 6 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/clk/mediatek/clk-mt2712.c
View File

@ -223,6 +223,8 @@ static const struct mtk_fixed_factor top_divs[] = {
4),
FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1_ck", 1,
3),
FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2_ck", 1,
3),
};
static const char * const axi_parents[] = {
@ -594,7 +596,8 @@ static const char * const a1sys_hp_parents[] = {
"apll1_ck",
"apll1_d2",
"apll1_d4",
"apll1_d8"
"apll1_d8",
"apll1_d3"
};
static const char * const a2sys_hp_parents[] = {
@ -602,7 +605,8 @@ static const char * const a2sys_hp_parents[] = {
"apll2_ck",
"apll2_d2",
"apll2_d4",
"apll2_d8"
"apll2_d8",
"apll2_d3"
};
static const char * const asm_l_parents[] = {