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- Fix the APEI MCE callback handler to consult the hardware about the
granularity of the memory error instead of hard-coding it - Offline memory pages on Intel machines after 2 errors reported per page -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAmM7+ZAACgkQEsHwGGHe VUp3Rg/9HkwMcl8HOEShQoN1HvhDh68DeR0pgZpFjooBgilqFuPopWn7rwOsebza b6Z1XYg3pmWwkG35ztHedFP8WkRb8aZDJV7czpGxiaxtRUCuXpGZJk45CFzU+3l8 FD9XKryDf6rPSKmg6w/63FUPVXJXpM8+pAlEso9BVrb6xmUb3n6ul5A/kt3Z4OBZ beNDI54s7pfKXmCYze7VbK2nqyEM9fmDuPAhaicB/qhVEqxSWMNKDYDhHs1wt/Um dOlLC2paqcc9EaRhV/L/9Pvi1zasy7Q0+jSIXhgbag7EQmZRYQn3Pe0xqUJNhK2H ulm65Dy+AZ3y15+qBkBOgoNF/By5eMwJ+C9bucC6FWkPG0XMjDVGiphf+DPZmAHk msYSvyp++WidNYn/bXhbQv0epjheLoHj22lTvlHwLquI+eISuDV24DIcBQQpFFed S/8sMw3RqoOgAd3LHr1NGcd/7eF+b/Lc1mtUx7qhg/W0V2cYVTGIcNJMAJ8USHMy IxFiB+8x7ps0lRJGlaApylLQOGAhS9WxpH2UUIKIoURrmCi9Pf8OaHzfIA5jYK+t xEQTzZE5ZUB0V5mvNhAWTm9HvlaW1WNbokt0vElAEJ9WAjRfMVYKya7shlAK2MYI nrM3eqlUwOqTGLGCA7IhCS9Re7M5ZKZk5nsLygnYsadntqCmN0c= =5tV9 -----END PGP SIGNATURE----- Merge tag 'ras_core_for_v6.1_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 RAS updates from Borislav Petkov: - Fix the APEI MCE callback handler to consult the hardware about the granularity of the memory error instead of hard-coding it - Offline memory pages on Intel machines after 2 errors reported per page * tag 'ras_core_for_v6.1_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/mce: Retrieve poison range from hardware RAS/CEC: Reduce offline page threshold for Intel systems
This commit is contained in:
commit
51eaa866a5
@ -29,15 +29,26 @@
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void apei_mce_report_mem_error(int severity, struct cper_sec_mem_err *mem_err)
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{
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struct mce m;
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int lsb;
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if (!(mem_err->validation_bits & CPER_MEM_VALID_PA))
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return;
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/*
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* Even if the ->validation_bits are set for address mask,
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* to be extra safe, check and reject an error radius '0',
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* and fall back to the default page size.
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*/
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if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
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lsb = find_first_bit((void *)&mem_err->physical_addr_mask, PAGE_SHIFT);
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else
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lsb = PAGE_SHIFT;
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mce_setup(&m);
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m.bank = -1;
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/* Fake a memory read error with unknown channel */
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m.status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_ADDRV | MCI_STATUS_MISCV | 0x9f;
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m.misc = (MCI_MISC_ADDR_PHYS << 6) | PAGE_SHIFT;
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m.misc = (MCI_MISC_ADDR_PHYS << 6) | lsb;
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if (severity >= GHES_SEV_RECOVERABLE)
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m.status |= MCI_STATUS_UC;
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@ -556,6 +556,14 @@ static int __init cec_init(void)
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if (ce_arr.disabled)
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return -ENODEV;
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/*
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* Intel systems may avoid uncorrectable errors
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* if pages with corrected errors are aggressively
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* taken offline.
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*/
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if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
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action_threshold = 2;
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ce_arr.array = (void *)get_zeroed_page(GFP_KERNEL);
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if (!ce_arr.array) {
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pr_err("Error allocating CE array page!\n");
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