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drm/i915/icl: Interrupt handling
v2: Rebase.
v3:
* Remove DPF, it has been removed from SKL+.
* Fix -internal rebase wrt. execlists interrupt handling.
v4: Rebase.
v5:
* Updated for POR changes. (Daniele Ceraolo Spurio)
* Merged with irq handling fixes by Daniele Ceraolo Spurio:
* Simplify the code by using gen8_cs_irq_handler.
* Fix interrupt handling for the upstream kernel.
v6:
* Remove early bringup debug messages (Tvrtko)
* Add NB about arbitrary spin wait timeout (Tvrtko)
v7 (from Paulo):
* Don't try to write RO bits to registers.
* Don't check for PCH types that don't exist. PCH interrupts are not
here yet.
v9:
* squashed in selector and shared register handling (Daniele)
* skip writing of irq if data is not valid (Daniele)
* use time_after32 (Chris)
* use I915_MAX_VCS and I915_MAX_VECS (Daniele)
* remove fake pm interrupt handling for later patch (Mika)
v10:
* Direct processing of banks. clear banks early (Chris)
* remove poll on valid bit, only clear valid bit (Mika)
* use raw accessors, better naming (Chris)
v11:
* adapt to raw_reg_[read|write]
* bring back polling the valid bit (Daniele)
v12:
* continue if unset intr_dw (Daniele)
* comment the usage of gen8_de_irq_handler bits (Daniele)
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180228101153.7224-2-mika.kuoppala@linux.intel.com
This commit is contained in:
Mika Kuoppala
parent
022d3093a9
commit
51951ae7ed
@ -415,6 +415,9 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
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if (READ_ONCE(rps->interrupts_enabled))
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return;
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if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
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return;
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spin_lock_irq(&dev_priv->irq_lock);
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WARN_ON_ONCE(rps->pm_iir);
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WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
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@ -431,6 +434,9 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
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if (!READ_ONCE(rps->interrupts_enabled))
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return;
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if (WARN_ON_ONCE(IS_GEN11(dev_priv)))
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return;
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spin_lock_irq(&dev_priv->irq_lock);
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rps->interrupts_enabled = false;
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@ -2755,6 +2761,156 @@ static void __fini_wedge(struct wedge_me *w)
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(W)->i915; \
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__fini_wedge((W)))
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static __always_inline void
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gen11_cs_irq_handler(struct intel_engine_cs * const engine, const u32 iir)
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{
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gen8_cs_irq_handler(engine, iir, 0);
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}
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static void
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gen11_gt_engine_irq_handler(struct drm_i915_private * const i915,
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const unsigned int bank,
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const unsigned int engine_n,
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const u16 iir)
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{
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struct intel_engine_cs ** const engine = i915->engine;
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switch (bank) {
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case 0:
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switch (engine_n) {
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case GEN11_RCS0:
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return gen11_cs_irq_handler(engine[RCS], iir);
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case GEN11_BCS:
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return gen11_cs_irq_handler(engine[BCS], iir);
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}
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case 1:
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switch (engine_n) {
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case GEN11_VCS(0):
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return gen11_cs_irq_handler(engine[_VCS(0)], iir);
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case GEN11_VCS(1):
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return gen11_cs_irq_handler(engine[_VCS(1)], iir);
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case GEN11_VCS(2):
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return gen11_cs_irq_handler(engine[_VCS(2)], iir);
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case GEN11_VCS(3):
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return gen11_cs_irq_handler(engine[_VCS(3)], iir);
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case GEN11_VECS(0):
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return gen11_cs_irq_handler(engine[_VECS(0)], iir);
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case GEN11_VECS(1):
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return gen11_cs_irq_handler(engine[_VECS(1)], iir);
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}
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}
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}
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static u32
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gen11_gt_engine_intr(struct drm_i915_private * const i915,
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const unsigned int bank, const unsigned int bit)
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{
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void __iomem * const regs = i915->regs;
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u32 timeout_ts;
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u32 ident;
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raw_reg_write(regs, GEN11_IIR_REG_SELECTOR(bank), BIT(bit));
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/*
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* NB: Specs do not specify how long to spin wait,
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* so we do ~100us as an educated guess.
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*/
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timeout_ts = (local_clock() >> 10) + 100;
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do {
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ident = raw_reg_read(regs, GEN11_INTR_IDENTITY_REG(bank));
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} while (!(ident & GEN11_INTR_DATA_VALID) &&
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!time_after32(local_clock() >> 10, timeout_ts));
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if (unlikely(!(ident & GEN11_INTR_DATA_VALID))) {
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DRM_ERROR("INTR_IDENTITY_REG%u:%u 0x%08x not valid!\n",
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bank, bit, ident);
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return 0;
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}
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raw_reg_write(regs, GEN11_INTR_IDENTITY_REG(bank),
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GEN11_INTR_DATA_VALID);
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return ident & GEN11_INTR_ENGINE_MASK;
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}
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static void
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gen11_gt_irq_handler(struct drm_i915_private * const i915,
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const u32 master_ctl)
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{
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void __iomem * const regs = i915->regs;
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unsigned int bank;
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for (bank = 0; bank < 2; bank++) {
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unsigned long intr_dw;
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unsigned int bit;
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if (!(master_ctl & GEN11_GT_DW_IRQ(bank)))
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continue;
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intr_dw = raw_reg_read(regs, GEN11_GT_INTR_DW(bank));
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if (unlikely(!intr_dw)) {
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DRM_ERROR("GT_INTR_DW%u blank!\n", bank);
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continue;
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}
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for_each_set_bit(bit, &intr_dw, 32) {
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const u16 iir = gen11_gt_engine_intr(i915, bank, bit);
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if (unlikely(!iir))
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continue;
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gen11_gt_engine_irq_handler(i915, bank, bit, iir);
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}
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/* Clear must be after shared has been served for engine */
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raw_reg_write(regs, GEN11_GT_INTR_DW(bank), intr_dw);
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}
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}
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static irqreturn_t gen11_irq_handler(int irq, void *arg)
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{
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struct drm_i915_private * const i915 = to_i915(arg);
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void __iomem * const regs = i915->regs;
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u32 master_ctl;
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if (!intel_irqs_enabled(i915))
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return IRQ_NONE;
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master_ctl = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
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master_ctl &= ~GEN11_MASTER_IRQ;
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if (!master_ctl)
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return IRQ_NONE;
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/* Disable interrupts. */
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raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
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/* Find, clear, then process each source of interrupt. */
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gen11_gt_irq_handler(i915, master_ctl);
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/* IRQs are synced during runtime_suspend, we don't require a wakeref */
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if (master_ctl & GEN11_DISPLAY_IRQ) {
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const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
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disable_rpm_wakeref_asserts(i915);
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/*
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* GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
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* for the display related bits.
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*/
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gen8_de_irq_handler(i915, disp_ctl);
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enable_rpm_wakeref_asserts(i915);
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}
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/* Acknowledge and enable interrupts. */
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raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl);
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return IRQ_HANDLED;
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}
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/**
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* i915_reset_device - do process context error handling work
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* @dev_priv: i915 device private
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@ -3180,6 +3336,42 @@ static void gen8_irq_reset(struct drm_device *dev)
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ibx_irq_reset(dev_priv);
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}
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static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv)
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{
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/* Disable RCS, BCS, VCS and VECS class engines. */
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I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, 0);
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I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, 0);
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/* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
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I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~0);
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I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~0);
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I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~0);
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I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~0);
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I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~0);
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}
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static void gen11_irq_reset(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int pipe;
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I915_WRITE(GEN11_GFX_MSTR_IRQ, 0);
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POSTING_READ(GEN11_GFX_MSTR_IRQ);
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gen11_gt_irq_reset(dev_priv);
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I915_WRITE(GEN11_DISPLAY_INT_CTL, 0);
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for_each_pipe(dev_priv, pipe)
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if (intel_display_power_is_enabled(dev_priv,
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POWER_DOMAIN_PIPE(pipe)))
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GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
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GEN3_IRQ_RESET(GEN8_DE_PORT_);
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GEN3_IRQ_RESET(GEN8_DE_MISC_);
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GEN3_IRQ_RESET(GEN8_PCU_);
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}
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void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
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u8 pipe_mask)
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{
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@ -3677,6 +3869,41 @@ static int gen8_irq_postinstall(struct drm_device *dev)
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return 0;
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}
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static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv)
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{
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const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT;
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BUILD_BUG_ON(irqs & 0xffff0000);
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/* Enable RCS, BCS, VCS and VECS class interrupts. */
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I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 | irqs);
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I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, irqs << 16 | irqs);
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/* Unmask irqs on RCS, BCS, VCS and VECS engines. */
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I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~(irqs << 16));
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I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~(irqs << 16));
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I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~(irqs | irqs << 16));
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I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~(irqs | irqs << 16));
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I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~(irqs | irqs << 16));
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dev_priv->pm_imr = 0xffffffff; /* TODO */
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}
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static int gen11_irq_postinstall(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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gen11_gt_irq_postinstall(dev_priv);
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gen8_de_irq_postinstall(dev_priv);
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I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
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I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
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POSTING_READ(GEN11_GFX_MSTR_IRQ);
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return 0;
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}
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static int cherryview_irq_postinstall(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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@ -4125,6 +4352,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
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dev->driver->enable_vblank = i965_enable_vblank;
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dev->driver->disable_vblank = i965_disable_vblank;
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dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
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} else if (INTEL_GEN(dev_priv) >= 11) {
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dev->driver->irq_handler = gen11_irq_handler;
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dev->driver->irq_preinstall = gen11_irq_reset;
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dev->driver->irq_postinstall = gen11_irq_postinstall;
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dev->driver->irq_uninstall = gen11_irq_reset;
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dev->driver->enable_vblank = gen8_enable_vblank;
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dev->driver->disable_vblank = gen8_disable_vblank;
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dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
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} else if (INTEL_GEN(dev_priv) >= 8) {
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dev->driver->irq_handler = gen8_irq_handler;
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dev->driver->irq_preinstall = gen8_irq_reset;
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@ -8026,7 +8026,10 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
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dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */
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intel_disable_gt_powersave(dev_priv);
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gen6_reset_rps_interrupts(dev_priv);
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if (INTEL_GEN(dev_priv) < 11)
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gen6_reset_rps_interrupts(dev_priv);
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else
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WARN_ON_ONCE(1);
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}
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static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
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@ -8139,6 +8142,8 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)
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cherryview_enable_rps(dev_priv);
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} else if (IS_VALLEYVIEW(dev_priv)) {
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valleyview_enable_rps(dev_priv);
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} else if (WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11)) {
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/* TODO */
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} else if (INTEL_GEN(dev_priv) >= 9) {
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gen9_enable_rps(dev_priv);
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} else if (IS_BROADWELL(dev_priv)) {
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