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clk: st: STiH407: Support for clockgenC0
The patch added support for DT registration of ClockGenC0 It includes 2 c32 type PLL and a 660 Quadfs. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Olivier Bideau <olivier.bideau@st.com> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -255,6 +255,49 @@ static const struct clkgen_quadfs_data st_fs660c32_F_416 = {
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.get_rate = clk_fs660c32_dig_get_rate,
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};
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static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
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.nrst_present = true,
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.nrst = { CLKGEN_FIELD(0x2f0, 0x1, 0),
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CLKGEN_FIELD(0x2f0, 0x1, 1),
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CLKGEN_FIELD(0x2f0, 0x1, 2),
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CLKGEN_FIELD(0x2f0, 0x1, 3) },
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.npda = CLKGEN_FIELD(0x2f0, 0x1, 12),
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.nsb = { CLKGEN_FIELD(0x2f0, 0x1, 8),
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CLKGEN_FIELD(0x2f0, 0x1, 9),
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CLKGEN_FIELD(0x2f0, 0x1, 10),
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CLKGEN_FIELD(0x2f0, 0x1, 11) },
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.nsdiv_present = true,
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.nsdiv = { CLKGEN_FIELD(0x304, 0x1, 24),
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CLKGEN_FIELD(0x308, 0x1, 24),
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CLKGEN_FIELD(0x30c, 0x1, 24),
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CLKGEN_FIELD(0x310, 0x1, 24) },
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.mdiv = { CLKGEN_FIELD(0x304, 0x1f, 15),
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CLKGEN_FIELD(0x308, 0x1f, 15),
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CLKGEN_FIELD(0x30c, 0x1f, 15),
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CLKGEN_FIELD(0x310, 0x1f, 15) },
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.en = { CLKGEN_FIELD(0x2fc, 0x1, 0),
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CLKGEN_FIELD(0x2fc, 0x1, 1),
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CLKGEN_FIELD(0x2fc, 0x1, 2),
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CLKGEN_FIELD(0x2fc, 0x1, 3) },
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.ndiv = CLKGEN_FIELD(0x2f4, 0x7, 16),
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.pe = { CLKGEN_FIELD(0x304, 0x7fff, 0),
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CLKGEN_FIELD(0x308, 0x7fff, 0),
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CLKGEN_FIELD(0x30c, 0x7fff, 0),
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CLKGEN_FIELD(0x310, 0x7fff, 0) },
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.sdiv = { CLKGEN_FIELD(0x304, 0xf, 20),
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CLKGEN_FIELD(0x308, 0xf, 20),
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CLKGEN_FIELD(0x30c, 0xf, 20),
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CLKGEN_FIELD(0x310, 0xf, 20) },
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.lockstatus_present = true,
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.lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
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.powerup_polarity = 1,
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.standby_polarity = 1,
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.pll_ops = &st_quadfs_pll_c32_ops,
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.rtbl = fs660c32_rtbl,
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.rtbl_cnt = ARRAY_SIZE(fs660c32_rtbl),
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.get_rate = clk_fs660c32_dig_get_rate,
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};
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/**
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* DOC: A Frequency Synthesizer that multiples its input clock by a fixed factor
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*
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@ -938,6 +981,14 @@ static struct of_device_id quadfs_of_match[] = {
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.compatible = "st,stih416-quadfs660-F",
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.data = &st_fs660c32_F_416
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},
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{
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.compatible = "st,stih407-quadfs660-C",
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.data = &st_fs660c32_C_407
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},
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{
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.compatible = "st,stih407-quadfs660-D",
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.data = &st_fs660c32_D_407
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},
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{}
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};
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@ -192,6 +192,30 @@ static const struct clkgen_pll_data st_pll3200c32_407_a0 = {
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.ops = &stm_pll3200c32_ops,
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};
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static const struct clkgen_pll_data st_pll3200c32_407_c0_0 = {
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/* 407 C0 PLL0 */
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.pdn_status = CLKGEN_FIELD(0x2a0, 0x1, 8),
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.locked_status = CLKGEN_FIELD(0x2a0, 0x1, 24),
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.ndiv = CLKGEN_FIELD(0x2a4, C32_NDIV_MASK, 16),
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.idf = CLKGEN_FIELD(0x2a4, C32_IDF_MASK, 0x0),
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.num_odfs = 1,
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.odf = { CLKGEN_FIELD(0x2b4, C32_ODF_MASK, 0) },
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.odf_gate = { CLKGEN_FIELD(0x2b4, 0x1, 6) },
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.ops = &stm_pll3200c32_ops,
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};
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static const struct clkgen_pll_data st_pll3200c32_407_c0_1 = {
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/* 407 C0 PLL1 */
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.pdn_status = CLKGEN_FIELD(0x2c8, 0x1, 8),
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.locked_status = CLKGEN_FIELD(0x2c8, 0x1, 24),
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.ndiv = CLKGEN_FIELD(0x2cc, C32_NDIV_MASK, 16),
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.idf = CLKGEN_FIELD(0x2cc, C32_IDF_MASK, 0x0),
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.num_odfs = 1,
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.odf = { CLKGEN_FIELD(0x2dc, C32_ODF_MASK, 0) },
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.odf_gate = { CLKGEN_FIELD(0x2dc, 0x1, 6) },
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.ops = &stm_pll3200c32_ops,
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};
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/**
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* DOC: Clock Generated by PLL, rate set and enabled by bootloader
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*
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@ -586,6 +610,14 @@ static struct of_device_id c32_pll_of_match[] = {
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.compatible = "st,stih407-plls-c32-a0",
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.data = &st_pll3200c32_407_a0,
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},
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{
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.compatible = "st,stih407-plls-c32-c0_0",
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.data = &st_pll3200c32_407_c0_0,
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},
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{
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.compatible = "st,stih407-plls-c32-c0_1",
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.data = &st_pll3200c32_407_c0_1,
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},
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{}
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};
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