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sb_edac: add support for Haswell based systems
Haswell memory controllers are very similar to Ivy Bridge and Sandy Bridge ones. This patch adds support to Haswell based systems. [m.chehab@samsung.com: Fix CodingStyle issues] Cc: Tony Luck <tony.luck@intel.com> Signed-off-by: Aristeu Rozanski <aris@redhat.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
This commit is contained in:
Aristeu Rozanski
Mauro Carvalho Chehab
parent
c41afdca29
commit
50d1bb9367
@ -245,12 +245,12 @@ config EDAC_I7300
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Clarksboro MCH (Intel 7300 chipset).
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config EDAC_SBRIDGE
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tristate "Intel Sandy-Bridge/Ivy-Bridge Integrated MC"
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tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
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depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
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depends on PCI_MMCONFIG
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help
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Support for error detection and correction the Intel
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Sandy Bridge and Ivy Bridge Integrated Memory Controllers.
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Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
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config EDAC_MPC85XX
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tristate "Freescale MPC83xx / MPC85xx"
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@ -99,6 +99,7 @@ static const u32 ibridge_dram_rule[] = {
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#define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3)
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#define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1)
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#define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0)
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#define A7MODE(reg) GET_BITFIELD(reg, 26, 26)
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static char *get_dram_attr(u32 reg)
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{
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@ -164,6 +165,8 @@ static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
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#define TOLM 0x80
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#define TOHM 0x84
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#define HASWELL_TOHM_0 0xd4
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#define HASWELL_TOHM_1 0xd8
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#define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff)
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#define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff)
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@ -286,6 +289,7 @@ static const u32 correrrthrsld[] = {
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enum type {
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SANDY_BRIDGE,
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IVY_BRIDGE,
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HASWELL,
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};
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struct sbridge_pvt;
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@ -303,6 +307,7 @@ struct sbridge_info {
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u8 max_interleave;
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u8 (*get_node_id)(struct sbridge_pvt *pvt);
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enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt);
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struct pci_dev *pci_vtd;
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};
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struct sbridge_channel {
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@ -334,6 +339,7 @@ struct sbridge_pvt {
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struct pci_dev *pci_sad0, *pci_sad1;
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struct pci_dev *pci_ha0, *pci_ha1;
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struct pci_dev *pci_br0, *pci_br1;
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struct pci_dev *pci_ha1_ta;
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struct pci_dev *pci_tad[NUM_CHANNELS];
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struct sbridge_dev *sbridge_dev;
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@ -452,12 +458,80 @@ static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
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{0,} /* 0 terminated list. */
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};
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/* Haswell support */
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/* EN processor:
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* - 1 IMC
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* - 3 DDR3 channels, 2 DPC per channel
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* EP processor:
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* - 1 or 2 IMC
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* - 4 DDR4 channels, 3 DPC per channel
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* EP 4S processor:
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* - 2 IMC
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* - 4 DDR4 channels, 3 DPC per channel
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* EX processor:
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* - 2 IMC
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* - each IMC interfaces with a SMI 2 channel
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* - each SMI channel interfaces with a scalable memory buffer
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* - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
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*/
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#define HASWELL_DDRCRCLKCONTROLS 0xa10
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#define HASWELL_HASYSDEFEATURE2 0x84
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC 0x2f28
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0 0x2fa0
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1 0x2f60
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA 0x2fa8
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL 0x2f71
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA 0x2f68
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL 0x2f79
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0 0x2ffc
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1 0x2ffd
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0 0x2faa
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1 0x2fab
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2 0x2fac
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3 0x2fad
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0 0x2f6a
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1 0x2f6b
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2 0x2f6c
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3 0x2f6d
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#define PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0 0x2fbd
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static const struct pci_id_descr pci_dev_descr_haswell[] = {
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/* first item must be the HA */
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, 1) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1, 0) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2, 1) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3, 1) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0, 1) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA, 1) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_THERMAL, 1) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0, 1) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1, 1) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD2, 1) },
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{ PCI_DESCR(PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD3, 1) },
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};
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static const struct pci_id_table pci_dev_descr_haswell_table[] = {
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PCI_ID_TABLE_ENTRY(pci_dev_descr_haswell),
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{0,} /* 0 terminated list. */
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};
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/*
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* pci_device_id table for which devices we are looking for
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*/
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static const struct pci_device_id sbridge_pci_tbl[] = {
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0)},
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{0,} /* 0 terminated list. */
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};
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@ -466,13 +540,17 @@ static const struct pci_device_id sbridge_pci_tbl[] = {
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Ancillary status routines
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****************************************************************************/
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static inline int numrank(u32 mtr)
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static inline int numrank(enum type type, u32 mtr)
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{
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int ranks = (1 << RANK_CNT_BITS(mtr));
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int max = 4;
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if (ranks > 4) {
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edac_dbg(0, "Invalid number of ranks: %d (max = 4) raw value = %x (%04x)\n",
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ranks, (unsigned int)RANK_CNT_BITS(mtr), mtr);
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if (type == HASWELL)
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max = 8;
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if (ranks > max) {
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edac_dbg(0, "Invalid number of ranks: %d (max = %i) raw value = %x (%04x)\n",
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ranks, max, (unsigned int)RANK_CNT_BITS(mtr), mtr);
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return -EINVAL;
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}
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@ -606,6 +684,38 @@ static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
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return mtype;
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}
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static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
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{
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u32 reg;
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bool registered = false;
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enum mem_type mtype = MEM_UNKNOWN;
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if (!pvt->pci_ddrio)
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goto out;
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pci_read_config_dword(pvt->pci_ddrio,
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HASWELL_DDRCRCLKCONTROLS, ®);
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/* Is_Rdimm */
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if (GET_BITFIELD(reg, 16, 16))
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registered = true;
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pci_read_config_dword(pvt->pci_ta, MCMTR, ®);
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if (GET_BITFIELD(reg, 14, 14)) {
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if (registered)
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mtype = MEM_RDDR4;
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else
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mtype = MEM_DDR4;
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} else {
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if (registered)
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mtype = MEM_RDDR3;
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else
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mtype = MEM_DDR3;
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}
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out:
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return mtype;
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}
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static u8 get_node_id(struct sbridge_pvt *pvt)
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{
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u32 reg;
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@ -613,6 +723,40 @@ static u8 get_node_id(struct sbridge_pvt *pvt)
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return GET_BITFIELD(reg, 0, 2);
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}
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static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
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{
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u32 reg;
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pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®);
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return GET_BITFIELD(reg, 0, 3);
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}
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static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
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{
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u32 reg;
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pci_read_config_dword(pvt->info.pci_vtd, TOLM, ®);
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return (GET_BITFIELD(reg, 26, 31) << 26) | 0x1ffffff;
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}
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static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
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{
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u64 rc;
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u32 reg;
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pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®);
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rc = GET_BITFIELD(reg, 26, 31);
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pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®);
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rc = ((reg << 6) | rc) << 26;
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return rc | 0x1ffffff;
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}
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static u64 haswell_rir_limit(u32 reg)
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{
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return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1;
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}
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static inline u8 sad_pkg_socket(u8 pkg)
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{
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/* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */
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@ -642,7 +786,10 @@ static struct pci_dev *get_pdev_same_bus(u8 bus, u32 id)
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/**
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* check_if_ecc_is_active() - Checks if ECC is active
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* bus: Device bus
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* @bus: Device bus
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* @type: Memory controller type
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* returns: 0 in case ECC is active, -ENODEV if it can't be determined or
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* disabled
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*/
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static int check_if_ecc_is_active(const u8 bus, enum type type)
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{
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@ -651,6 +798,8 @@ static int check_if_ecc_is_active(const u8 bus, enum type type)
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if (type == IVY_BRIDGE)
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id = PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA;
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else if (type == HASWELL)
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id = PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA;
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else
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id = PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA;
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@ -680,7 +829,11 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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enum edac_type mode;
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enum mem_type mtype;
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pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®);
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if (pvt->info.type == HASWELL)
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pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®);
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else
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pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®);
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pvt->sbridge_dev->source_id = SOURCE_ID(reg);
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pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
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@ -717,15 +870,17 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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}
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mtype = pvt->info.get_memory_type(pvt);
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if (mtype == MEM_RDDR3)
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if (mtype == MEM_RDDR3 || mtype == MEM_RDDR4)
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edac_dbg(0, "Memory is registered\n");
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else if (mtype == MEM_UNKNOWN)
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edac_dbg(0, "Cannot determine memory type\n");
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else
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edac_dbg(0, "Memory is unregistered\n");
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/* On all supported DDR3 DIMM types, there are 8 banks available */
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banks = 8;
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if (mtype == MEM_DDR4 || MEM_RDDR4)
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banks = 16;
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else
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banks = 8;
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for (i = 0; i < NUM_CHANNELS; i++) {
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u32 mtr;
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@ -739,11 +894,10 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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if (IS_DIMM_PRESENT(mtr)) {
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pvt->channel[i].dimms++;
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ranks = numrank(mtr);
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ranks = numrank(pvt->info.type, mtr);
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rows = numrow(mtr);
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cols = numcol(mtr);
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/* DDR3 has 8 I/O banks */
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size = ((u64)rows * cols * banks * ranks) >> (20 - 3);
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npages = MiB_TO_PAGES(size);
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@ -754,7 +908,17 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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dimm->nr_pages = npages;
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dimm->grain = 32;
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dimm->dtype = (banks == 8) ? DEV_X8 : DEV_X4;
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switch (banks) {
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case 16:
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dimm->dtype = DEV_X16;
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break;
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case 8:
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dimm->dtype = DEV_X8;
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break;
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case 4:
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dimm->dtype = DEV_X4;
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break;
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}
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dimm->mtype = mtype;
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dimm->edac_mode = mode;
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snprintf(dimm->label, sizeof(dimm->label),
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@ -948,9 +1112,9 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
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struct pci_dev *pci_ha;
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int n_rir, n_sads, n_tads, sad_way, sck_xch;
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int sad_interl, idx, base_ch;
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int interleave_mode;
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int interleave_mode, shiftup = 0;
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unsigned sad_interleave[pvt->info.max_interleave];
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u32 reg;
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u32 reg, dram_rule;
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u8 ch_way, sck_way, pkg, sad_ha = 0;
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u32 tad_offset;
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u32 rir_way;
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@ -997,8 +1161,9 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
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sprintf(msg, "Can't discover the memory socket");
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return -EINVAL;
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}
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*area_type = get_dram_attr(reg);
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interleave_mode = INTERLEAVE_MODE(reg);
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dram_rule = reg;
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*area_type = get_dram_attr(dram_rule);
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interleave_mode = INTERLEAVE_MODE(dram_rule);
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pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
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®);
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@ -1043,6 +1208,36 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
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*socket = sad_interleave[idx];
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edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
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idx, sad_way, *socket);
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} else if (pvt->info.type == HASWELL) {
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int bits, a7mode = A7MODE(dram_rule);
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if (a7mode) {
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/* A7 mode swaps P9 with P6 */
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bits = GET_BITFIELD(addr, 7, 8) << 1;
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bits |= GET_BITFIELD(addr, 9, 9);
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} else
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bits = GET_BITFIELD(addr, 7, 9);
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if (interleave_mode) {
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/* interleave mode will XOR {8,7,6} with {18,17,16} */
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idx = GET_BITFIELD(addr, 16, 18);
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idx ^= bits;
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} else
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idx = bits;
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pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
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*socket = sad_pkg_socket(pkg);
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sad_ha = sad_pkg_ha(pkg);
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if (a7mode) {
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/* MCChanShiftUpEnable */
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pci_read_config_dword(pvt->pci_ha0,
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HASWELL_HASYSDEFEATURE2, ®);
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shiftup = GET_BITFIELD(reg, 22, 22);
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}
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edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n",
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idx, *socket, sad_ha, shiftup);
|
||||
} else {
|
||||
/* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
|
||||
idx = (addr >> 6) & 7;
|
||||
@ -1100,7 +1295,7 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
|
||||
if (ch_way == 3)
|
||||
idx = addr >> 6;
|
||||
else
|
||||
idx = addr >> (6 + sck_way);
|
||||
idx = (addr >> (6 + sck_way + shiftup)) & 0x3;
|
||||
idx = idx % ch_way;
|
||||
|
||||
/*
|
||||
@ -1207,6 +1402,7 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
|
||||
return -EINVAL;
|
||||
}
|
||||
rir_way = RIR_WAY(reg);
|
||||
|
||||
if (pvt->is_close_pg)
|
||||
idx = (ch_addr >> 6);
|
||||
else
|
||||
@ -1561,6 +1757,106 @@ error:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int haswell_mci_bind_devs(struct mem_ctl_info *mci,
|
||||
struct sbridge_dev *sbridge_dev)
|
||||
{
|
||||
struct sbridge_pvt *pvt = mci->pvt_info;
|
||||
struct pci_dev *pdev, *tmp;
|
||||
int i;
|
||||
bool mode_2ha = false;
|
||||
|
||||
tmp = pci_get_device(PCI_VENDOR_ID_INTEL,
|
||||
PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1, NULL);
|
||||
if (tmp) {
|
||||
mode_2ha = true;
|
||||
pci_dev_put(tmp);
|
||||
}
|
||||
|
||||
/* there's only one device per system; not tied to any bus */
|
||||
if (pvt->info.pci_vtd == NULL)
|
||||
/* result will be checked later */
|
||||
pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
|
||||
PCI_DEVICE_ID_INTEL_HASWELL_IMC_VTD_MISC,
|
||||
NULL);
|
||||
|
||||
for (i = 0; i < sbridge_dev->n_devs; i++) {
|
||||
pdev = sbridge_dev->pdev[i];
|
||||
if (!pdev)
|
||||
continue;
|
||||
|
||||
switch (pdev->device) {
|
||||
case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD0:
|
||||
pvt->pci_sad0 = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_HASWELL_IMC_CBO_SAD1:
|
||||
pvt->pci_sad1 = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
|
||||
pvt->pci_ha0 = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TA:
|
||||
pvt->pci_ta = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_THERMAL:
|
||||
pvt->pci_ras = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD0:
|
||||
pvt->pci_tad[0] = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD1:
|
||||
pvt->pci_tad[1] = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD2:
|
||||
if (!mode_2ha)
|
||||
pvt->pci_tad[2] = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0_TAD3:
|
||||
if (!mode_2ha)
|
||||
pvt->pci_tad[3] = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_HASWELL_IMC_DDRIO0:
|
||||
pvt->pci_ddrio = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1:
|
||||
pvt->pci_ha1 = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TA:
|
||||
pvt->pci_ha1_ta = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD0:
|
||||
if (mode_2ha)
|
||||
pvt->pci_tad[2] = pdev;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA1_TAD1:
|
||||
if (mode_2ha)
|
||||
pvt->pci_tad[3] = pdev;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
|
||||
sbridge_dev->bus,
|
||||
PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
|
||||
pdev);
|
||||
}
|
||||
|
||||
/* Check if everything were registered */
|
||||
if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_sad1 ||
|
||||
!pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd)
|
||||
goto enodev;
|
||||
|
||||
for (i = 0; i < NUM_CHANNELS; i++) {
|
||||
if (!pvt->pci_tad[i])
|
||||
goto enodev;
|
||||
}
|
||||
return 0;
|
||||
|
||||
enodev:
|
||||
sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
Error check routines
|
||||
****************************************************************************/
|
||||
@ -1912,7 +2208,8 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
|
||||
mci->edac_check = sbridge_check_error;
|
||||
|
||||
pvt->info.type = type;
|
||||
if (type == IVY_BRIDGE) {
|
||||
switch (type) {
|
||||
case IVY_BRIDGE:
|
||||
pvt->info.rankcfgr = IB_RANK_CFG_A;
|
||||
pvt->info.get_tolm = ibridge_get_tolm;
|
||||
pvt->info.get_tohm = ibridge_get_tohm;
|
||||
@ -1930,7 +2227,8 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
|
||||
rc = ibridge_mci_bind_devs(mci, sbridge_dev);
|
||||
if (unlikely(rc < 0))
|
||||
goto fail0;
|
||||
} else {
|
||||
break;
|
||||
case SANDY_BRIDGE:
|
||||
pvt->info.rankcfgr = SB_RANK_CFG_A;
|
||||
pvt->info.get_tolm = sbridge_get_tolm;
|
||||
pvt->info.get_tohm = sbridge_get_tohm;
|
||||
@ -1948,8 +2246,27 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
|
||||
rc = sbridge_mci_bind_devs(mci, sbridge_dev);
|
||||
if (unlikely(rc < 0))
|
||||
goto fail0;
|
||||
}
|
||||
break;
|
||||
case HASWELL:
|
||||
/* rankcfgr isn't used */
|
||||
pvt->info.get_tolm = haswell_get_tolm;
|
||||
pvt->info.get_tohm = haswell_get_tohm;
|
||||
pvt->info.dram_rule = ibridge_dram_rule;
|
||||
pvt->info.get_memory_type = haswell_get_memory_type;
|
||||
pvt->info.get_node_id = haswell_get_node_id;
|
||||
pvt->info.rir_limit = haswell_rir_limit;
|
||||
pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
|
||||
pvt->info.interleave_list = ibridge_interleave_list;
|
||||
pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
|
||||
pvt->info.interleave_pkg = ibridge_interleave_pkg;
|
||||
mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell Socket#%d", mci->mc_idx);
|
||||
|
||||
/* Store pci devices at mci for faster access */
|
||||
rc = haswell_mci_bind_devs(mci, sbridge_dev);
|
||||
if (unlikely(rc < 0))
|
||||
goto fail0;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Get dimm basic config and the memory layout */
|
||||
get_dimm_config(mci);
|
||||
@ -1984,10 +2301,10 @@ fail0:
|
||||
|
||||
static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
{
|
||||
int rc;
|
||||
int rc = -ENODEV;
|
||||
u8 mc, num_mc = 0;
|
||||
struct sbridge_dev *sbridge_dev;
|
||||
enum type type;
|
||||
enum type type = SANDY_BRIDGE;
|
||||
|
||||
/* get the pci devices we want to reserve for our use */
|
||||
mutex_lock(&sbridge_edac_lock);
|
||||
@ -2001,12 +2318,19 @@ static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
}
|
||||
probed++;
|
||||
|
||||
if (pdev->device == PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA) {
|
||||
switch (pdev->device) {
|
||||
case PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA:
|
||||
rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_ibridge_table);
|
||||
type = IVY_BRIDGE;
|
||||
} else {
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA:
|
||||
rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_sbridge_table);
|
||||
type = SANDY_BRIDGE;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_HASWELL_IMC_HA0:
|
||||
rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_haswell_table);
|
||||
type = HASWELL;
|
||||
break;
|
||||
}
|
||||
if (unlikely(rc < 0))
|
||||
goto fail0;
|
||||
@ -2015,6 +2339,7 @@ static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
||||
list_for_each_entry(sbridge_dev, &sbridge_edac_list, list) {
|
||||
edac_dbg(0, "Registering MC#%d (%d of %d)\n",
|
||||
mc, mc + 1, num_mc);
|
||||
|
||||
sbridge_dev->mc = mc++;
|
||||
rc = sbridge_register_mci(sbridge_dev, type);
|
||||
if (unlikely(rc < 0))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user