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Microchip clock update for 6.1
Microchip AT91: - add generic clocks for U(S)ART available on SAMA5D2 SoCs Microchip Polarfire: - reset controller support for Polarfire clocks - .round_rate and .set rate support for clk-mpfs - code cleanup for clk-mpfs - PLL support for PolarFire SoC's Clock Conditioning Circuitry -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQTsZ8eserC1pmhwqDmejrg/N2X7/QUCYyLpfAAKCRCejrg/N2X7 /S2hAQDJSv3LHIHdlJ2m0GBLnLUhlX8q0KvqEoymP4ORFBNR3AD9ErfvxfXdMdUM YIIGytahkRzkdNulIgm0/wpuwiRDOQQ= =mVG6 -----END PGP SIGNATURE----- Merge tag 'clk-microchip-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip Pull Microchip clk driver updates from Claudiu Beznea: Microchip AT91: - add generic clocks for U(S)ART available on SAMA5D2 SoCs Microchip Polarfire: - reset controller support for Polarfire clocks - .round_rate and .set rate support for clk-mpfs - code cleanup for clk-mpfs - PLL support for PolarFire SoC's Clock Conditioning Circuitry * tag 'clk-microchip-6.1' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: clk: at91: sama5d2: Add Generic Clocks for UART/USART clk: microchip: add PolarFire SoC fabric clock support dt-bindings: clk: add PolarFire SoC fabric clock ids dt-bindings: clk: document PolarFire SoC fabric clocks dt-bindings: clk: rename mpfs-clkcfg binding clk: microchip: mpfs: update module authorship & licencing clk: microchip: mpfs: convert periph_clk to clk_gate clk: microchip: mpfs: convert cfg_clk to clk_divider clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo() clk: microchip: mpfs: simplify control reg access clk: microchip: mpfs: move id & offset out of clock structs clk: microchip: mpfs: add MSS pll's set & round rate MAINTAINERS: add polarfire soc reset controller reset: add polarfire soc reset support clk: microchip: mpfs: add reset controller dt-bindings: clk: microchip: mpfs: add reset controller support clk: microchip: mpfs: make the rtc's ahb clock critical clk: microchip: mpfs: fix clk_cfg array bounds violation
This commit is contained in:
Stephen Boyd
commit
50cf94b419
@ -0,0 +1,80 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/microchip,mpfs-ccc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip PolarFire SoC Fabric Clock Conditioning Circuitry
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maintainers:
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- Conor Dooley <conor.dooley@microchip.com>
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description: |
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Microchip PolarFire SoC has 4 Clock Conditioning Circuitry blocks. Each of
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these blocks contains two PLLs and 2 DLLs & are located in the four corners of
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the FPGA. For more information see "PolarFire SoC FPGA Clocking Resources" at:
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https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html
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properties:
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compatible:
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const: microchip,mpfs-ccc
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reg:
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items:
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- description: PLL0's control registers
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- description: PLL1's control registers
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- description: DLL0's control registers
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- description: DLL1's control registers
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clocks:
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description:
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The CCC PLL's have two input clocks. It is required that even if the input
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clocks are identical that both are provided.
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minItems: 2
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items:
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- description: PLL0's refclk0
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- description: PLL0's refclk1
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- description: PLL1's refclk0
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- description: PLL1's refclk1
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- description: DLL0's refclk
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- description: DLL1's refclk
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clock-names:
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minItems: 2
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items:
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- const: pll0_ref0
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- const: pll0_ref1
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- const: pll1_ref0
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- const: pll1_ref1
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- const: dll0_ref
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- const: dll1_ref
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'#clock-cells':
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const: 1
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description: |
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell.
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See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
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PolarFire clock IDs.
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@38100000 {
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compatible = "microchip,mpfs-ccc";
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reg = <0x38010000 0x1000>, <0x38020000 0x1000>,
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<0x39010000 0x1000>, <0x39020000 0x1000>;
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#clock-cells = <1>;
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clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
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<&refclk_ccc>, <&refclk_ccc>;
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clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
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"dll0_ref", "dll1_ref";
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};
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@ -1,7 +1,7 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml#
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$id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip PolarFire Clock Control Module Binding
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@ -40,8 +40,21 @@ properties:
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const: 1
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description: |
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h
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for the full list of PolarFire clock IDs.
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ID in its "clocks" phandle cell.
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See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
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PolarFire clock IDs.
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resets:
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maxItems: 1
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'#reset-cells':
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description:
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The AHB/AXI peripherals on the PolarFire SoC have reset support, so from
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CLK_ENVM to CLK_CFM. The reset consumer should specify the desired
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peripheral via the clock ID in its "resets" phandle cell.
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See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of
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PolarFire clock IDs.
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const: 1
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required:
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- compatible
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@ -17532,6 +17532,7 @@ F: drivers/char/hw_random/mpfs-rng.c
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F: drivers/clk/microchip/clk-mpfs.c
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F: drivers/mailbox/mailbox-mpfs.c
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F: drivers/pci/controller/pcie-microchip-host.c
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F: drivers/reset/reset-mpfs.c
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F: drivers/rtc/rtc-mpfs.c
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F: drivers/soc/microchip/
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F: drivers/spi/spi-microchip-core.c
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@ -120,6 +120,16 @@ static const struct {
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struct clk_range r;
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int chg_pid;
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} sama5d2_gck[] = {
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{ .n = "flx0_gclk", .id = 19, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
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{ .n = "flx1_gclk", .id = 20, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
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{ .n = "flx2_gclk", .id = 21, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
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{ .n = "flx3_gclk", .id = 22, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
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{ .n = "flx4_gclk", .id = 23, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
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{ .n = "uart0_gclk", .id = 24, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
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{ .n = "uart1_gclk", .id = 25, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
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{ .n = "uart2_gclk", .id = 26, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
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{ .n = "uart3_gclk", .id = 27, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
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{ .n = "uart4_gclk", .id = 28, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, },
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{ .n = "sdmmc0_gclk", .id = 31, .chg_pid = INT_MIN, },
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{ .n = "sdmmc1_gclk", .id = 32, .chg_pid = INT_MIN, },
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{ .n = "tcb0_gclk", .id = 35, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
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@ -6,5 +6,6 @@ config COMMON_CLK_PIC32
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config MCHP_CLK_MPFS
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bool "Clk driver for PolarFire SoC"
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depends on (RISCV && SOC_MICROCHIP_POLARFIRE) || COMPILE_TEST
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select AUXILIARY_BUS
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help
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Supports Clock Configuration for PolarFire SoC
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@ -2,3 +2,4 @@
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obj-$(CONFIG_COMMON_CLK_PIC32) += clk-core.o
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obj-$(CONFIG_PIC32MZDA) += clk-pic32mzda.o
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obj-$(CONFIG_MCHP_CLK_MPFS) += clk-mpfs.o
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obj-$(CONFIG_MCHP_CLK_MPFS) += clk-mpfs-ccc.o
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290
drivers/clk/microchip/clk-mpfs-ccc.c
Normal file
290
drivers/clk/microchip/clk-mpfs-ccc.c
Normal file
@ -0,0 +1,290 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Author: Conor Dooley <conor.dooley@microchip.com>
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*
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* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
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*/
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#include "asm-generic/errno-base.h"
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/clock/microchip,mpfs-clock.h>
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/* address offset of control registers */
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#define MPFS_CCC_PLL_CR 0x04u
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#define MPFS_CCC_REF_CR 0x08u
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#define MPFS_CCC_SSCG_2_CR 0x2Cu
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#define MPFS_CCC_POSTDIV01_CR 0x10u
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#define MPFS_CCC_POSTDIV23_CR 0x14u
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#define MPFS_CCC_FBDIV_SHIFT 0x00u
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#define MPFS_CCC_FBDIV_WIDTH 0x0Cu
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#define MPFS_CCC_POSTDIV0_SHIFT 0x08u
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#define MPFS_CCC_POSTDIV1_SHIFT 0x18u
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#define MPFS_CCC_POSTDIV2_SHIFT MPFS_CCC_POSTDIV0_SHIFT
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#define MPFS_CCC_POSTDIV3_SHIFT MPFS_CCC_POSTDIV1_SHIFT
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#define MPFS_CCC_POSTDIV_WIDTH 0x06u
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#define MPFS_CCC_REFCLK_SEL BIT(6)
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#define MPFS_CCC_REFDIV_SHIFT 0x08u
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#define MPFS_CCC_REFDIV_WIDTH 0x06u
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#define MPFS_CCC_FIXED_DIV 4
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#define MPFS_CCC_OUTPUTS_PER_PLL 4
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#define MPFS_CCC_REFS_PER_PLL 2
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struct mpfs_ccc_data {
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void __iomem **pll_base;
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struct device *dev;
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struct clk_hw_onecell_data hw_data;
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};
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struct mpfs_ccc_pll_hw_clock {
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void __iomem *base;
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const char *name;
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const struct clk_parent_data *parents;
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unsigned int id;
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u32 reg_offset;
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u32 shift;
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u32 width;
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u32 flags;
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struct clk_hw hw;
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struct clk_init_data init;
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};
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#define to_mpfs_ccc_clk(_hw) container_of(_hw, struct mpfs_ccc_pll_hw_clock, hw)
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/*
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* mpfs_ccc_lock prevents anything else from writing to a fabric ccc
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* while a software locked register is being written.
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*/
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static DEFINE_SPINLOCK(mpfs_ccc_lock);
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static const struct clk_parent_data mpfs_ccc_pll0_refs[] = {
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{ .fw_name = "pll0_ref0" },
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{ .fw_name = "pll0_ref1" },
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};
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static const struct clk_parent_data mpfs_ccc_pll1_refs[] = {
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{ .fw_name = "pll1_ref0" },
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{ .fw_name = "pll1_ref1" },
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};
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static unsigned long mpfs_ccc_pll_recalc_rate(struct clk_hw *hw, unsigned long prate)
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{
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struct mpfs_ccc_pll_hw_clock *ccc_hw = to_mpfs_ccc_clk(hw);
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void __iomem *mult_addr = ccc_hw->base + ccc_hw->reg_offset;
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void __iomem *ref_div_addr = ccc_hw->base + MPFS_CCC_REF_CR;
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u32 mult, ref_div;
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mult = readl_relaxed(mult_addr) >> MPFS_CCC_FBDIV_SHIFT;
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mult &= clk_div_mask(MPFS_CCC_FBDIV_WIDTH);
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ref_div = readl_relaxed(ref_div_addr) >> MPFS_CCC_REFDIV_SHIFT;
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ref_div &= clk_div_mask(MPFS_CCC_REFDIV_WIDTH);
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return prate * mult / (ref_div * MPFS_CCC_FIXED_DIV);
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}
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static u8 mpfs_ccc_pll_get_parent(struct clk_hw *hw)
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{
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struct mpfs_ccc_pll_hw_clock *ccc_hw = to_mpfs_ccc_clk(hw);
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void __iomem *pll_cr_addr = ccc_hw->base + MPFS_CCC_PLL_CR;
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return !!(readl_relaxed(pll_cr_addr) & MPFS_CCC_REFCLK_SEL);
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}
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static const struct clk_ops mpfs_ccc_pll_ops = {
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.recalc_rate = mpfs_ccc_pll_recalc_rate,
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.get_parent = mpfs_ccc_pll_get_parent,
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};
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#define CLK_CCC_PLL(_id, _parents, _shift, _width, _flags, _offset) { \
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.id = _id, \
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.shift = _shift, \
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.width = _width, \
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.reg_offset = _offset, \
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.flags = _flags, \
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.parents = _parents, \
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}
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static struct mpfs_ccc_pll_hw_clock mpfs_ccc_pll_clks[] = {
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CLK_CCC_PLL(CLK_CCC_PLL0, mpfs_ccc_pll0_refs, MPFS_CCC_FBDIV_SHIFT,
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MPFS_CCC_FBDIV_WIDTH, 0, MPFS_CCC_SSCG_2_CR),
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CLK_CCC_PLL(CLK_CCC_PLL1, mpfs_ccc_pll1_refs, MPFS_CCC_FBDIV_SHIFT,
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MPFS_CCC_FBDIV_WIDTH, 0, MPFS_CCC_SSCG_2_CR),
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};
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struct mpfs_ccc_out_hw_clock {
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struct clk_divider divider;
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struct clk_init_data init;
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unsigned int id;
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u32 reg_offset;
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};
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#define CLK_CCC_OUT(_id, _shift, _width, _flags, _offset) { \
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.id = _id, \
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.divider.shift = _shift, \
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.divider.width = _width, \
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.reg_offset = _offset, \
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.divider.flags = _flags, \
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.divider.lock = &mpfs_ccc_lock, \
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}
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static struct mpfs_ccc_out_hw_clock mpfs_ccc_pll0out_clks[] = {
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CLK_CCC_OUT(CLK_CCC_PLL0_OUT0, MPFS_CCC_POSTDIV0_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
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CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR),
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CLK_CCC_OUT(CLK_CCC_PLL0_OUT1, MPFS_CCC_POSTDIV1_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
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CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR),
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CLK_CCC_OUT(CLK_CCC_PLL0_OUT2, MPFS_CCC_POSTDIV2_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
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CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR),
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CLK_CCC_OUT(CLK_CCC_PLL0_OUT3, MPFS_CCC_POSTDIV3_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
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CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR),
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};
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static struct mpfs_ccc_out_hw_clock mpfs_ccc_pll1out_clks[] = {
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CLK_CCC_OUT(CLK_CCC_PLL1_OUT0, MPFS_CCC_POSTDIV0_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
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CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR),
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CLK_CCC_OUT(CLK_CCC_PLL1_OUT1, MPFS_CCC_POSTDIV1_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
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CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV01_CR),
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CLK_CCC_OUT(CLK_CCC_PLL1_OUT2, MPFS_CCC_POSTDIV2_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
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CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR),
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CLK_CCC_OUT(CLK_CCC_PLL1_OUT3, MPFS_CCC_POSTDIV3_SHIFT, MPFS_CCC_POSTDIV_WIDTH,
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CLK_DIVIDER_ONE_BASED, MPFS_CCC_POSTDIV23_CR),
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};
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static struct mpfs_ccc_out_hw_clock *mpfs_ccc_pllout_clks[] = {
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mpfs_ccc_pll0out_clks, mpfs_ccc_pll1out_clks
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};
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static int mpfs_ccc_register_outputs(struct device *dev, struct mpfs_ccc_out_hw_clock *out_hws,
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unsigned int num_clks, struct mpfs_ccc_data *data,
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struct mpfs_ccc_pll_hw_clock *parent)
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{
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int ret;
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for (unsigned int i = 0; i < num_clks; i++) {
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struct mpfs_ccc_out_hw_clock *out_hw = &out_hws[i];
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char *name = devm_kzalloc(dev, 23, GFP_KERNEL);
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||||
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snprintf(name, 23, "%s_out%u", parent->name, i);
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out_hw->divider.hw.init = CLK_HW_INIT_HW(name, &parent->hw, &clk_divider_ops, 0);
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out_hw->divider.reg = data->pll_base[i / MPFS_CCC_OUTPUTS_PER_PLL] +
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out_hw->reg_offset;
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||||
ret = devm_clk_hw_register(dev, &out_hw->divider.hw);
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if (ret)
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return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
|
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out_hw->id);
|
||||
|
||||
data->hw_data.hws[out_hw->id] = &out_hw->divider.hw;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define CLK_HW_INIT_PARENTS_DATA_FIXED_SIZE(_name, _parents, _ops, _flags) \
|
||||
(&(struct clk_init_data) { \
|
||||
.flags = _flags, \
|
||||
.name = _name, \
|
||||
.parent_data = _parents, \
|
||||
.num_parents = MPFS_CCC_REFS_PER_PLL, \
|
||||
.ops = _ops, \
|
||||
})
|
||||
|
||||
static int mpfs_ccc_register_plls(struct device *dev, struct mpfs_ccc_pll_hw_clock *pll_hws,
|
||||
unsigned int num_clks, struct mpfs_ccc_data *data)
|
||||
{
|
||||
int ret;
|
||||
|
||||
for (unsigned int i = 0; i < num_clks; i++) {
|
||||
struct mpfs_ccc_pll_hw_clock *pll_hw = &pll_hws[i];
|
||||
char *name = devm_kzalloc(dev, 18, GFP_KERNEL);
|
||||
|
||||
pll_hw->base = data->pll_base[i];
|
||||
snprintf(name, 18, "ccc%s_pll%u", strchrnul(dev->of_node->full_name, '@'), i);
|
||||
pll_hw->name = (const char *)name;
|
||||
pll_hw->hw.init = CLK_HW_INIT_PARENTS_DATA_FIXED_SIZE(pll_hw->name,
|
||||
pll_hw->parents,
|
||||
&mpfs_ccc_pll_ops, 0);
|
||||
|
||||
ret = devm_clk_hw_register(dev, &pll_hw->hw);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "failed to register ccc id: %d\n",
|
||||
pll_hw->id);
|
||||
|
||||
data->hw_data.hws[pll_hw->id] = &pll_hw->hw;
|
||||
|
||||
ret = mpfs_ccc_register_outputs(dev, mpfs_ccc_pllout_clks[i],
|
||||
MPFS_CCC_OUTPUTS_PER_PLL, data, pll_hw);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mpfs_ccc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct mpfs_ccc_data *clk_data;
|
||||
void __iomem *pll_base[ARRAY_SIZE(mpfs_ccc_pll_clks)];
|
||||
unsigned int num_clks;
|
||||
int ret;
|
||||
|
||||
num_clks = ARRAY_SIZE(mpfs_ccc_pll_clks) + ARRAY_SIZE(mpfs_ccc_pll0out_clks) +
|
||||
ARRAY_SIZE(mpfs_ccc_pll1out_clks);
|
||||
|
||||
clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hw_data.hws, num_clks),
|
||||
GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
|
||||
pll_base[0] = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(pll_base[0]))
|
||||
return PTR_ERR(pll_base[0]);
|
||||
|
||||
pll_base[1] = devm_platform_ioremap_resource(pdev, 1);
|
||||
if (IS_ERR(pll_base[1]))
|
||||
return PTR_ERR(pll_base[1]);
|
||||
|
||||
clk_data->pll_base = pll_base;
|
||||
clk_data->hw_data.num = num_clks;
|
||||
clk_data->dev = &pdev->dev;
|
||||
|
||||
ret = mpfs_ccc_register_plls(clk_data->dev, mpfs_ccc_pll_clks,
|
||||
ARRAY_SIZE(mpfs_ccc_pll_clks), clk_data);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return devm_of_clk_add_hw_provider(clk_data->dev, of_clk_hw_onecell_get,
|
||||
&clk_data->hw_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id mpfs_ccc_of_match_table[] = {
|
||||
{ .compatible = "microchip,mpfs-ccc", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mpfs_ccc_of_match_table);
|
||||
|
||||
static struct platform_driver mpfs_ccc_driver = {
|
||||
.probe = mpfs_ccc_probe,
|
||||
.driver = {
|
||||
.name = "microchip-mpfs-ccc",
|
||||
.of_match_table = mpfs_ccc_of_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init clk_ccc_init(void)
|
||||
{
|
||||
return platform_driver_register(&mpfs_ccc_driver);
|
||||
}
|
||||
core_initcall(clk_ccc_init);
|
||||
|
||||
static void __exit clk_ccc_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&mpfs_ccc_driver);
|
||||
}
|
||||
module_exit(clk_ccc_exit);
|
||||
|
||||
MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Conditioning Circuitry Driver");
|
||||
MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
@ -1,14 +1,17 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Daire McNamara,<daire.mcnamara@microchip.com>
|
||||
* Copyright (C) 2020 Microchip Technology Inc. All rights reserved.
|
||||
* PolarFire SoC MSS/core complex clock control
|
||||
*
|
||||
* Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
|
||||
*/
|
||||
#include <linux/auxiliary_bus.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <dt-bindings/clock/microchip,mpfs-clock.h>
|
||||
#include <soc/microchip/mpfs.h>
|
||||
|
||||
/* address offset of control registers */
|
||||
#define REG_MSSPLL_REF_CR 0x08u
|
||||
@ -28,6 +31,7 @@
|
||||
#define MSSPLL_FIXED_DIV 4u
|
||||
|
||||
struct mpfs_clock_data {
|
||||
struct device *dev;
|
||||
void __iomem *base;
|
||||
void __iomem *msspll_base;
|
||||
struct clk_hw_onecell_data hw_data;
|
||||
@ -46,37 +50,18 @@ struct mpfs_msspll_hw_clock {
|
||||
|
||||
#define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw)
|
||||
|
||||
struct mpfs_cfg_clock {
|
||||
const struct clk_div_table *table;
|
||||
struct mpfs_cfg_hw_clock {
|
||||
struct clk_divider cfg;
|
||||
struct clk_init_data init;
|
||||
unsigned int id;
|
||||
u32 reg_offset;
|
||||
u8 shift;
|
||||
u8 width;
|
||||
u8 flags;
|
||||
};
|
||||
|
||||
struct mpfs_cfg_hw_clock {
|
||||
struct mpfs_cfg_clock cfg;
|
||||
void __iomem *sys_base;
|
||||
struct clk_hw hw;
|
||||
struct clk_init_data init;
|
||||
};
|
||||
|
||||
#define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw)
|
||||
|
||||
struct mpfs_periph_clock {
|
||||
unsigned int id;
|
||||
u8 shift;
|
||||
};
|
||||
|
||||
struct mpfs_periph_hw_clock {
|
||||
struct mpfs_periph_clock periph;
|
||||
void __iomem *sys_base;
|
||||
struct clk_hw hw;
|
||||
struct clk_gate periph;
|
||||
unsigned int id;
|
||||
};
|
||||
|
||||
#define to_mpfs_periph_clk(_hw) container_of(_hw, struct mpfs_periph_hw_clock, hw)
|
||||
|
||||
/*
|
||||
* mpfs_clk_lock prevents anything else from writing to the
|
||||
* mpfs clk block while a software locked register is being written.
|
||||
@ -126,8 +111,62 @@ static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned lon
|
||||
return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv);
|
||||
}
|
||||
|
||||
static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate)
|
||||
{
|
||||
struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
|
||||
void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
|
||||
void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
|
||||
u32 mult, ref_div;
|
||||
unsigned long rate_before_ctrl;
|
||||
|
||||
mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT;
|
||||
mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
|
||||
ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
|
||||
ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
|
||||
|
||||
rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult;
|
||||
|
||||
return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH,
|
||||
msspll_hw->flags);
|
||||
}
|
||||
|
||||
static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
|
||||
{
|
||||
struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw);
|
||||
void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;
|
||||
void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;
|
||||
void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR;
|
||||
u32 mult, ref_div, postdiv;
|
||||
int divider_setting;
|
||||
unsigned long rate_before_ctrl, flags;
|
||||
|
||||
mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT;
|
||||
mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH);
|
||||
ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT;
|
||||
ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH);
|
||||
|
||||
rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult;
|
||||
divider_setting = divider_get_val(rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH,
|
||||
msspll_hw->flags);
|
||||
|
||||
if (divider_setting < 0)
|
||||
return divider_setting;
|
||||
|
||||
spin_lock_irqsave(&mpfs_clk_lock, flags);
|
||||
|
||||
postdiv = readl_relaxed(postdiv_addr);
|
||||
postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT);
|
||||
writel_relaxed(postdiv, postdiv_addr);
|
||||
|
||||
spin_unlock_irqrestore(&mpfs_clk_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops mpfs_clk_msspll_ops = {
|
||||
.recalc_rate = mpfs_clk_msspll_recalc_rate,
|
||||
.round_rate = mpfs_clk_msspll_round_rate,
|
||||
.set_rate = mpfs_clk_msspll_set_rate,
|
||||
};
|
||||
|
||||
#define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \
|
||||
@ -144,25 +183,17 @@ static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = {
|
||||
MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR),
|
||||
};
|
||||
|
||||
static int mpfs_clk_register_msspll(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hw,
|
||||
void __iomem *base)
|
||||
{
|
||||
msspll_hw->base = base;
|
||||
|
||||
return devm_clk_hw_register(dev, &msspll_hw->hw);
|
||||
}
|
||||
|
||||
static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_clock *msspll_hws,
|
||||
unsigned int num_clks, struct mpfs_clock_data *data)
|
||||
{
|
||||
void __iomem *base = data->msspll_base;
|
||||
unsigned int i;
|
||||
int ret;
|
||||
|
||||
for (i = 0; i < num_clks; i++) {
|
||||
struct mpfs_msspll_hw_clock *msspll_hw = &msspll_hws[i];
|
||||
|
||||
ret = mpfs_clk_register_msspll(dev, msspll_hw, base);
|
||||
msspll_hw->base = data->msspll_base;
|
||||
ret = devm_clk_hw_register(dev, &msspll_hw->hw);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "failed to register msspll id: %d\n",
|
||||
CLK_MSSPLL);
|
||||
@ -177,68 +208,22 @@ static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_c
|
||||
* "CFG" clocks
|
||||
*/
|
||||
|
||||
static unsigned long mpfs_cfg_clk_recalc_rate(struct clk_hw *hw, unsigned long prate)
|
||||
{
|
||||
struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
|
||||
struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
|
||||
void __iomem *base_addr = cfg_hw->sys_base;
|
||||
u32 val;
|
||||
|
||||
val = readl_relaxed(base_addr + cfg->reg_offset) >> cfg->shift;
|
||||
val &= clk_div_mask(cfg->width);
|
||||
|
||||
return divider_recalc_rate(hw, prate, val, cfg->table, cfg->flags, cfg->width);
|
||||
}
|
||||
|
||||
static long mpfs_cfg_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate)
|
||||
{
|
||||
struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
|
||||
struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
|
||||
|
||||
return divider_round_rate(hw, rate, prate, cfg->table, cfg->width, 0);
|
||||
}
|
||||
|
||||
static int mpfs_cfg_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)
|
||||
{
|
||||
struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
|
||||
struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
|
||||
void __iomem *base_addr = cfg_hw->sys_base;
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
int divider_setting;
|
||||
|
||||
divider_setting = divider_get_val(rate, prate, cfg->table, cfg->width, 0);
|
||||
|
||||
if (divider_setting < 0)
|
||||
return divider_setting;
|
||||
|
||||
spin_lock_irqsave(&mpfs_clk_lock, flags);
|
||||
val = readl_relaxed(base_addr + cfg->reg_offset);
|
||||
val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift);
|
||||
val |= divider_setting << cfg->shift;
|
||||
writel_relaxed(val, base_addr + cfg->reg_offset);
|
||||
|
||||
spin_unlock_irqrestore(&mpfs_clk_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops mpfs_clk_cfg_ops = {
|
||||
.recalc_rate = mpfs_cfg_clk_recalc_rate,
|
||||
.round_rate = mpfs_cfg_clk_round_rate,
|
||||
.set_rate = mpfs_cfg_clk_set_rate,
|
||||
};
|
||||
|
||||
#define CLK_CFG(_id, _name, _parent, _shift, _width, _table, _flags, _offset) { \
|
||||
.cfg.id = _id, \
|
||||
.id = _id, \
|
||||
.cfg.shift = _shift, \
|
||||
.cfg.width = _width, \
|
||||
.cfg.table = _table, \
|
||||
.cfg.reg_offset = _offset, \
|
||||
.reg_offset = _offset, \
|
||||
.cfg.flags = _flags, \
|
||||
.hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_cfg_ops, 0), \
|
||||
.cfg.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \
|
||||
.cfg.lock = &mpfs_clk_lock, \
|
||||
}
|
||||
|
||||
#define CLK_CPU_OFFSET 0u
|
||||
#define CLK_AXI_OFFSET 1u
|
||||
#define CLK_AHB_OFFSET 2u
|
||||
#define CLK_RTCREF_OFFSET 3u
|
||||
|
||||
static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = {
|
||||
CLK_CFG(CLK_CPU, "clk_cpu", "clk_msspll", 0, 2, mpfs_div_cpu_axi_table, 0,
|
||||
REG_CLOCK_CONFIG_CR),
|
||||
@ -247,42 +232,34 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = {
|
||||
CLK_CFG(CLK_AHB, "clk_ahb", "clk_msspll", 4, 2, mpfs_div_ahb_table, 0,
|
||||
REG_CLOCK_CONFIG_CR),
|
||||
{
|
||||
.cfg.id = CLK_RTCREF,
|
||||
.id = CLK_RTCREF,
|
||||
.cfg.shift = 0,
|
||||
.cfg.width = 12,
|
||||
.cfg.table = mpfs_div_rtcref_table,
|
||||
.cfg.reg_offset = REG_RTC_CLOCK_CR,
|
||||
.reg_offset = REG_RTC_CLOCK_CR,
|
||||
.cfg.flags = CLK_DIVIDER_ONE_BASED,
|
||||
.hw.init =
|
||||
CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &mpfs_clk_cfg_ops, 0),
|
||||
.cfg.hw.init =
|
||||
CLK_HW_INIT_PARENTS_DATA("clk_rtcref", mpfs_ext_ref, &clk_divider_ops, 0),
|
||||
}
|
||||
};
|
||||
|
||||
static int mpfs_clk_register_cfg(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hw,
|
||||
void __iomem *sys_base)
|
||||
{
|
||||
cfg_hw->sys_base = sys_base;
|
||||
|
||||
return devm_clk_hw_register(dev, &cfg_hw->hw);
|
||||
}
|
||||
|
||||
static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *cfg_hws,
|
||||
unsigned int num_clks, struct mpfs_clock_data *data)
|
||||
{
|
||||
void __iomem *sys_base = data->base;
|
||||
unsigned int i, id;
|
||||
int ret;
|
||||
|
||||
for (i = 0; i < num_clks; i++) {
|
||||
struct mpfs_cfg_hw_clock *cfg_hw = &cfg_hws[i];
|
||||
|
||||
ret = mpfs_clk_register_cfg(dev, cfg_hw, sys_base);
|
||||
cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset;
|
||||
ret = devm_clk_hw_register(dev, &cfg_hw->cfg.hw);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
|
||||
cfg_hw->cfg.id);
|
||||
cfg_hw->id);
|
||||
|
||||
id = cfg_hw->cfg.id;
|
||||
data->hw_data.hws[id] = &cfg_hw->hw;
|
||||
id = cfg_hw->id;
|
||||
data->hw_data.hws[id] = &cfg_hw->cfg.hw;
|
||||
}
|
||||
|
||||
return 0;
|
||||
@ -292,77 +269,15 @@ static int mpfs_clk_register_cfgs(struct device *dev, struct mpfs_cfg_hw_clock *
|
||||
* peripheral clocks - devices connected to axi or ahb buses.
|
||||
*/
|
||||
|
||||
static int mpfs_periph_clk_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
|
||||
struct mpfs_periph_clock *periph = &periph_hw->periph;
|
||||
void __iomem *base_addr = periph_hw->sys_base;
|
||||
u32 reg, val;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&mpfs_clk_lock, flags);
|
||||
|
||||
reg = readl_relaxed(base_addr + REG_SUBBLK_RESET_CR);
|
||||
val = reg & ~(1u << periph->shift);
|
||||
writel_relaxed(val, base_addr + REG_SUBBLK_RESET_CR);
|
||||
|
||||
reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR);
|
||||
val = reg | (1u << periph->shift);
|
||||
writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR);
|
||||
|
||||
spin_unlock_irqrestore(&mpfs_clk_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mpfs_periph_clk_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
|
||||
struct mpfs_periph_clock *periph = &periph_hw->periph;
|
||||
void __iomem *base_addr = periph_hw->sys_base;
|
||||
u32 reg, val;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&mpfs_clk_lock, flags);
|
||||
|
||||
reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR);
|
||||
val = reg & ~(1u << periph->shift);
|
||||
writel_relaxed(val, base_addr + REG_SUBBLK_CLOCK_CR);
|
||||
|
||||
spin_unlock_irqrestore(&mpfs_clk_lock, flags);
|
||||
}
|
||||
|
||||
static int mpfs_periph_clk_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct mpfs_periph_hw_clock *periph_hw = to_mpfs_periph_clk(hw);
|
||||
struct mpfs_periph_clock *periph = &periph_hw->periph;
|
||||
void __iomem *base_addr = periph_hw->sys_base;
|
||||
u32 reg;
|
||||
|
||||
reg = readl_relaxed(base_addr + REG_SUBBLK_RESET_CR);
|
||||
if ((reg & (1u << periph->shift)) == 0u) {
|
||||
reg = readl_relaxed(base_addr + REG_SUBBLK_CLOCK_CR);
|
||||
if (reg & (1u << periph->shift))
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops mpfs_periph_clk_ops = {
|
||||
.enable = mpfs_periph_clk_enable,
|
||||
.disable = mpfs_periph_clk_disable,
|
||||
.is_enabled = mpfs_periph_clk_is_enabled,
|
||||
};
|
||||
|
||||
#define CLK_PERIPH(_id, _name, _parent, _shift, _flags) { \
|
||||
.periph.id = _id, \
|
||||
.periph.shift = _shift, \
|
||||
.hw.init = CLK_HW_INIT_HW(_name, _parent, &mpfs_periph_clk_ops, \
|
||||
.id = _id, \
|
||||
.periph.bit_idx = _shift, \
|
||||
.periph.hw.init = CLK_HW_INIT_HW(_name, _parent, &clk_gate_ops, \
|
||||
_flags), \
|
||||
.periph.lock = &mpfs_clk_lock, \
|
||||
}
|
||||
|
||||
#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT].hw)
|
||||
#define PARENT_CLK(PARENT) (&mpfs_cfg_clks[CLK_##PARENT##_OFFSET].cfg.hw)
|
||||
|
||||
/*
|
||||
* Critical clocks:
|
||||
@ -370,6 +285,8 @@ static const struct clk_ops mpfs_periph_clk_ops = {
|
||||
* trap handler
|
||||
* - CLK_MMUART0: reserved by the hss
|
||||
* - CLK_DDRC: provides clock to the ddr subsystem
|
||||
* - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop
|
||||
* if the AHB interface clock is disabled
|
||||
* - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect)
|
||||
* clock domain crossers which provide the interface to the FPGA fabric. Disabling them
|
||||
* causes the FPGA fabric to go into reset.
|
||||
@ -394,7 +311,7 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {
|
||||
CLK_PERIPH(CLK_CAN0, "clk_periph_can0", PARENT_CLK(AHB), 14, 0),
|
||||
CLK_PERIPH(CLK_CAN1, "clk_periph_can1", PARENT_CLK(AHB), 15, 0),
|
||||
CLK_PERIPH(CLK_USB, "clk_periph_usb", PARENT_CLK(AHB), 16, 0),
|
||||
CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, 0),
|
||||
CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, CLK_IS_CRITICAL),
|
||||
CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", PARENT_CLK(AHB), 19, 0),
|
||||
CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", PARENT_CLK(AHB), 20, 0),
|
||||
CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0),
|
||||
@ -408,36 +325,116 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {
|
||||
CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0),
|
||||
};
|
||||
|
||||
static int mpfs_clk_register_periph(struct device *dev, struct mpfs_periph_hw_clock *periph_hw,
|
||||
void __iomem *sys_base)
|
||||
{
|
||||
periph_hw->sys_base = sys_base;
|
||||
|
||||
return devm_clk_hw_register(dev, &periph_hw->hw);
|
||||
}
|
||||
|
||||
static int mpfs_clk_register_periphs(struct device *dev, struct mpfs_periph_hw_clock *periph_hws,
|
||||
int num_clks, struct mpfs_clock_data *data)
|
||||
{
|
||||
void __iomem *sys_base = data->base;
|
||||
unsigned int i, id;
|
||||
int ret;
|
||||
|
||||
for (i = 0; i < num_clks; i++) {
|
||||
struct mpfs_periph_hw_clock *periph_hw = &periph_hws[i];
|
||||
|
||||
ret = mpfs_clk_register_periph(dev, periph_hw, sys_base);
|
||||
periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR;
|
||||
ret = devm_clk_hw_register(dev, &periph_hw->periph.hw);
|
||||
if (ret)
|
||||
return dev_err_probe(dev, ret, "failed to register clock id: %d\n",
|
||||
periph_hw->periph.id);
|
||||
periph_hw->id);
|
||||
|
||||
id = periph_hws[i].periph.id;
|
||||
data->hw_data.hws[id] = &periph_hw->hw;
|
||||
id = periph_hws[i].id;
|
||||
data->hw_data.hws[id] = &periph_hw->periph.hw;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Peripheral clock resets
|
||||
*/
|
||||
|
||||
#if IS_ENABLED(CONFIG_RESET_CONTROLLER)
|
||||
|
||||
u32 mpfs_reset_read(struct device *dev)
|
||||
{
|
||||
struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent);
|
||||
|
||||
return readl_relaxed(clock_data->base + REG_SUBBLK_RESET_CR);
|
||||
}
|
||||
EXPORT_SYMBOL_NS_GPL(mpfs_reset_read, MCHP_CLK_MPFS);
|
||||
|
||||
void mpfs_reset_write(struct device *dev, u32 val)
|
||||
{
|
||||
struct mpfs_clock_data *clock_data = dev_get_drvdata(dev->parent);
|
||||
|
||||
writel_relaxed(val, clock_data->base + REG_SUBBLK_RESET_CR);
|
||||
}
|
||||
EXPORT_SYMBOL_NS_GPL(mpfs_reset_write, MCHP_CLK_MPFS);
|
||||
|
||||
static void mpfs_reset_unregister_adev(void *_adev)
|
||||
{
|
||||
struct auxiliary_device *adev = _adev;
|
||||
|
||||
auxiliary_device_delete(adev);
|
||||
}
|
||||
|
||||
static void mpfs_reset_adev_release(struct device *dev)
|
||||
{
|
||||
struct auxiliary_device *adev = to_auxiliary_dev(dev);
|
||||
|
||||
auxiliary_device_uninit(adev);
|
||||
|
||||
kfree(adev);
|
||||
}
|
||||
|
||||
static struct auxiliary_device *mpfs_reset_adev_alloc(struct mpfs_clock_data *clk_data)
|
||||
{
|
||||
struct auxiliary_device *adev;
|
||||
int ret;
|
||||
|
||||
adev = kzalloc(sizeof(*adev), GFP_KERNEL);
|
||||
if (!adev)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
adev->name = "reset-mpfs";
|
||||
adev->dev.parent = clk_data->dev;
|
||||
adev->dev.release = mpfs_reset_adev_release;
|
||||
adev->id = 666u;
|
||||
|
||||
ret = auxiliary_device_init(adev);
|
||||
if (ret) {
|
||||
kfree(adev);
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
return adev;
|
||||
}
|
||||
|
||||
static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data)
|
||||
{
|
||||
struct auxiliary_device *adev;
|
||||
int ret;
|
||||
|
||||
adev = mpfs_reset_adev_alloc(clk_data);
|
||||
if (IS_ERR(adev))
|
||||
return PTR_ERR(adev);
|
||||
|
||||
ret = auxiliary_device_add(adev);
|
||||
if (ret) {
|
||||
auxiliary_device_uninit(adev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
return devm_add_action_or_reset(clk_data->dev, mpfs_reset_unregister_adev, adev);
|
||||
}
|
||||
|
||||
#else /* !CONFIG_RESET_CONTROLLER */
|
||||
|
||||
static int mpfs_reset_controller_register(struct mpfs_clock_data *clk_data)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* !CONFIG_RESET_CONTROLLER */
|
||||
|
||||
static int mpfs_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
@ -462,6 +459,8 @@ static int mpfs_clk_probe(struct platform_device *pdev)
|
||||
return PTR_ERR(clk_data->msspll_base);
|
||||
|
||||
clk_data->hw_data.num = num_clks;
|
||||
clk_data->dev = dev;
|
||||
dev_set_drvdata(dev, clk_data);
|
||||
|
||||
ret = mpfs_clk_register_mssplls(dev, mpfs_msspll_clks, ARRAY_SIZE(mpfs_msspll_clks),
|
||||
clk_data);
|
||||
@ -481,14 +480,14 @@ static int mpfs_clk_probe(struct platform_device *pdev)
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return ret;
|
||||
return mpfs_reset_controller_register(clk_data);
|
||||
}
|
||||
|
||||
static const struct of_device_id mpfs_clk_of_match_table[] = {
|
||||
{ .compatible = "microchip,mpfs-clkcfg", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mpfs_clk_match_table);
|
||||
MODULE_DEVICE_TABLE(of, mpfs_clk_of_match_table);
|
||||
|
||||
static struct platform_driver mpfs_clk_driver = {
|
||||
.probe = mpfs_clk_probe,
|
||||
@ -511,4 +510,7 @@ static void __exit clk_mpfs_exit(void)
|
||||
module_exit(clk_mpfs_exit);
|
||||
|
||||
MODULE_DESCRIPTION("Microchip PolarFire SoC Clock Driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Padmarao Begari <padmarao.begari@microchip.com>");
|
||||
MODULE_AUTHOR("Daire McNamara <daire.mcnamara@microchip.com>");
|
||||
MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
||||
@ -152,6 +152,13 @@ config RESET_PISTACHIO
|
||||
help
|
||||
This enables the reset driver for ImgTec Pistachio SoCs.
|
||||
|
||||
config RESET_POLARFIRE_SOC
|
||||
bool "Microchip PolarFire SoC (MPFS) Reset Driver"
|
||||
depends on AUXILIARY_BUS && MCHP_CLK_MPFS
|
||||
default MCHP_CLK_MPFS
|
||||
help
|
||||
This driver supports peripheral reset for the Microchip PolarFire SoC
|
||||
|
||||
config RESET_QCOM_AOSS
|
||||
tristate "Qcom AOSS Reset Driver"
|
||||
depends on ARCH_QCOM || COMPILE_TEST
|
||||
|
||||
@ -22,6 +22,7 @@ obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
|
||||
obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
|
||||
obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
|
||||
obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
|
||||
obj-$(CONFIG_RESET_POLARFIRE_SOC) += reset-mpfs.o
|
||||
obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o
|
||||
obj-$(CONFIG_RESET_QCOM_PDC) += reset-qcom-pdc.o
|
||||
obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
|
||||
@ -40,4 +41,3 @@ obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
|
||||
obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o
|
||||
obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o
|
||||
obj-$(CONFIG_ARCH_ZYNQMP) += reset-zynqmp.o
|
||||
|
||||
|
||||
157
drivers/reset/reset-mpfs.c
Normal file
157
drivers/reset/reset-mpfs.c
Normal file
@ -0,0 +1,157 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* PolarFire SoC (MPFS) Peripheral Clock Reset Controller
|
||||
*
|
||||
* Author: Conor Dooley <conor.dooley@microchip.com>
|
||||
* Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries.
|
||||
*
|
||||
*/
|
||||
#include <linux/auxiliary_bus.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <dt-bindings/clock/microchip,mpfs-clock.h>
|
||||
#include <soc/microchip/mpfs.h>
|
||||
|
||||
/*
|
||||
* The ENVM reset is the lowest bit in the register & I am using the CLK_FOO
|
||||
* defines in the dt to make things easier to configure - so this is accounting
|
||||
* for the offset of 3 there.
|
||||
*/
|
||||
#define MPFS_PERIPH_OFFSET CLK_ENVM
|
||||
#define MPFS_NUM_RESETS 30u
|
||||
#define MPFS_SLEEP_MIN_US 100
|
||||
#define MPFS_SLEEP_MAX_US 200
|
||||
|
||||
/* block concurrent access to the soft reset register */
|
||||
static DEFINE_SPINLOCK(mpfs_reset_lock);
|
||||
|
||||
/*
|
||||
* Peripheral clock resets
|
||||
*/
|
||||
|
||||
static int mpfs_assert(struct reset_controller_dev *rcdev, unsigned long id)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
|
||||
spin_lock_irqsave(&mpfs_reset_lock, flags);
|
||||
|
||||
reg = mpfs_reset_read(rcdev->dev);
|
||||
reg |= BIT(id);
|
||||
mpfs_reset_write(rcdev->dev, reg);
|
||||
|
||||
spin_unlock_irqrestore(&mpfs_reset_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mpfs_deassert(struct reset_controller_dev *rcdev, unsigned long id)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
|
||||
spin_lock_irqsave(&mpfs_reset_lock, flags);
|
||||
|
||||
reg = mpfs_reset_read(rcdev->dev);
|
||||
reg &= ~BIT(id);
|
||||
mpfs_reset_write(rcdev->dev, reg);
|
||||
|
||||
spin_unlock_irqrestore(&mpfs_reset_lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mpfs_status(struct reset_controller_dev *rcdev, unsigned long id)
|
||||
{
|
||||
u32 reg = mpfs_reset_read(rcdev->dev);
|
||||
|
||||
/*
|
||||
* It is safe to return here as MPFS_NUM_RESETS makes sure the sign bit
|
||||
* is never hit.
|
||||
*/
|
||||
return (reg & BIT(id));
|
||||
}
|
||||
|
||||
static int mpfs_reset(struct reset_controller_dev *rcdev, unsigned long id)
|
||||
{
|
||||
mpfs_assert(rcdev, id);
|
||||
|
||||
usleep_range(MPFS_SLEEP_MIN_US, MPFS_SLEEP_MAX_US);
|
||||
|
||||
mpfs_deassert(rcdev, id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct reset_control_ops mpfs_reset_ops = {
|
||||
.reset = mpfs_reset,
|
||||
.assert = mpfs_assert,
|
||||
.deassert = mpfs_deassert,
|
||||
.status = mpfs_status,
|
||||
};
|
||||
|
||||
static int mpfs_reset_xlate(struct reset_controller_dev *rcdev,
|
||||
const struct of_phandle_args *reset_spec)
|
||||
{
|
||||
unsigned int index = reset_spec->args[0];
|
||||
|
||||
/*
|
||||
* CLK_RESERVED does not map to a clock, but it does map to a reset,
|
||||
* so it has to be accounted for here. It is the reset for the fabric,
|
||||
* so if this reset gets called - do not reset it.
|
||||
*/
|
||||
if (index == CLK_RESERVED) {
|
||||
dev_err(rcdev->dev, "Resetting the fabric is not supported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (index < MPFS_PERIPH_OFFSET || index >= (MPFS_PERIPH_OFFSET + rcdev->nr_resets)) {
|
||||
dev_err(rcdev->dev, "Invalid reset index %u\n", index);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return index - MPFS_PERIPH_OFFSET;
|
||||
}
|
||||
|
||||
static int mpfs_reset_probe(struct auxiliary_device *adev,
|
||||
const struct auxiliary_device_id *id)
|
||||
{
|
||||
struct device *dev = &adev->dev;
|
||||
struct reset_controller_dev *rcdev;
|
||||
|
||||
rcdev = devm_kzalloc(dev, sizeof(*rcdev), GFP_KERNEL);
|
||||
if (!rcdev)
|
||||
return -ENOMEM;
|
||||
|
||||
rcdev->dev = dev;
|
||||
rcdev->dev->parent = dev->parent;
|
||||
rcdev->ops = &mpfs_reset_ops;
|
||||
rcdev->of_node = dev->parent->of_node;
|
||||
rcdev->of_reset_n_cells = 1;
|
||||
rcdev->of_xlate = mpfs_reset_xlate;
|
||||
rcdev->nr_resets = MPFS_NUM_RESETS;
|
||||
|
||||
return devm_reset_controller_register(dev, rcdev);
|
||||
}
|
||||
|
||||
static const struct auxiliary_device_id mpfs_reset_ids[] = {
|
||||
{
|
||||
.name = "clk_mpfs.reset-mpfs",
|
||||
},
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(auxiliary, mpfs_reset_ids);
|
||||
|
||||
static struct auxiliary_driver mpfs_reset_driver = {
|
||||
.probe = mpfs_reset_probe,
|
||||
.id_table = mpfs_reset_ids,
|
||||
};
|
||||
|
||||
module_auxiliary_driver(mpfs_reset_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Microchip PolarFire SoC Reset Driver");
|
||||
MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_IMPORT_NS(MCHP_CLK_MPFS);
|
||||
@ -45,4 +45,27 @@
|
||||
#define CLK_RTCREF 33
|
||||
#define CLK_MSSPLL 34
|
||||
|
||||
/* Clock Conditioning Circuitry Clock IDs */
|
||||
|
||||
#define CLK_CCC_PLL0 0
|
||||
#define CLK_CCC_PLL1 1
|
||||
#define CLK_CCC_DLL0 2
|
||||
#define CLK_CCC_DLL1 3
|
||||
|
||||
#define CLK_CCC_PLL0_OUT0 4
|
||||
#define CLK_CCC_PLL0_OUT1 5
|
||||
#define CLK_CCC_PLL0_OUT2 6
|
||||
#define CLK_CCC_PLL0_OUT3 7
|
||||
|
||||
#define CLK_CCC_PLL1_OUT0 8
|
||||
#define CLK_CCC_PLL1_OUT1 9
|
||||
#define CLK_CCC_PLL1_OUT2 10
|
||||
#define CLK_CCC_PLL1_OUT3 11
|
||||
|
||||
#define CLK_CCC_DLL0_OUT0 12
|
||||
#define CLK_CCC_DLL0_OUT1 13
|
||||
|
||||
#define CLK_CCC_DLL1_OUT0 14
|
||||
#define CLK_CCC_DLL1_OUT1 15
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */
|
||||
|
||||
@ -40,4 +40,12 @@ struct mpfs_sys_controller *mpfs_sys_controller_get(struct device *dev);
|
||||
|
||||
#endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */
|
||||
|
||||
#if IS_ENABLED(CONFIG_MCHP_CLK_MPFS)
|
||||
|
||||
u32 mpfs_reset_read(struct device *dev);
|
||||
|
||||
void mpfs_reset_write(struct device *dev, u32 val);
|
||||
|
||||
#endif /* if IS_ENABLED(CONFIG_MCHP_CLK_MPFS) */
|
||||
|
||||
#endif /* __SOC_MPFS_H__ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user