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net: stmmac: dwmac-stm32: add management of stm32mp13 for stm32

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Add Ethernet support for STM32MP13.
STM32MP13 is STM32 SOC with 2 GMACs instances.
GMAC IP version is SNPS 4.20.
GMAC IP configure with 1 RX and 1 TX queue.
DMA HW capability register supported
RX Checksum Offload Engine supported
TX Checksum insertion supported
Wake-Up On Lan supported
TSO supported

Signed-off-by: Christophe Roullier <christophe.roullier@foss.st.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Christophe Roullier 2024-06-11 10:36:06 +02:00 committed by Paolo Abeni
parent 4f37dc467f
commit 50bbc03931
1 changed files with 28 additions and 4 deletions
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32
drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c
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@ -104,6 +104,7 @@ struct stm32_ops {
int (*parse_data)(struct stm32_dwmac *dwmac,
struct device *dev);
bool clk_rx_enable_in_suspend;
bool is_mp13;
u32 syscfg_clr_off;
};
@ -224,11 +225,18 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat)
{
struct stm32_dwmac *dwmac = plat_dat->bsp_priv;
u32 reg = dwmac->mode_reg;
int val;
int val = 0;
switch (plat_dat->mac_interface) {
case PHY_INTERFACE_MODE_MII:
val = SYSCFG_PMCR_ETH_SEL_MII;
/*
* STM32MP15xx supports both MII and GMII, STM32MP13xx MII only.
* SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and
* acts as a selector between 0:GMII and 1:MII. As STM32MP13xx
* supports only MII, ETH_SELMII is not present.
*/
if (!dwmac->ops->is_mp13) /* Select MII mode on STM32MP15xx */
val |= SYSCFG_PMCR_ETH_SEL_MII;
break;
case PHY_INTERFACE_MODE_GMII:
val = SYSCFG_PMCR_ETH_SEL_GMII;
@ -359,8 +367,12 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac,
dwmac->mode_mask = SYSCFG_MP1_ETH_MASK;
err = of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask);
if (err)
dev_dbg(dev, "Warning sysconfig register mask not set\n");
if (err) {
if (dwmac->ops->is_mp13)
dev_err(dev, "Sysconfig register mask must be set (%d)\n", err);
else
dev_dbg(dev, "Warning sysconfig register mask not set\n");
}
return err;
}
@ -560,12 +572,24 @@ static struct stm32_ops stm32mp1_dwmac_data = {
.resume = stm32mp1_resume,
.parse_data = stm32mp1_parse_data,
.syscfg_clr_off = 0x44,
.is_mp13 = false,
.clk_rx_enable_in_suspend = true
};
static struct stm32_ops stm32mp13_dwmac_data = {
.set_mode = stm32mp1_set_mode,
.suspend = stm32mp1_suspend,
.resume = stm32mp1_resume,
.parse_data = stm32mp1_parse_data,
.syscfg_clr_off = 0x08,
.is_mp13 = true,
.clk_rx_enable_in_suspend = true
};
static const struct of_device_id stm32_dwmac_match[] = {
{ .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data},
{ .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data},
{ .compatible = "st,stm32mp13-dwmac", .data = &stm32mp13_dwmac_data},
{ }
};
MODULE_DEVICE_TABLE(of, stm32_dwmac_match);