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phy: qcom-qmp: Add USB QMP PHY support for IPQ8074
Add QMP USB PHY found in IPQ8074 Co-developed-by: Balaji Prakash J <bjagadee@codeaurora.org> Signed-off-by: Balaji Prakash J <bjagadee@codeaurora.org> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Tested-by: Sricharan R <sricharan@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/1591625479-4483-4-git-send-email-sivaprak@codeaurora.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Sivaprakash Murugesan
Vinod Koul
parent
ba971c2ff5
commit
507156f5a9
@ -198,6 +198,81 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = {
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[QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET,
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};
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static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
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QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
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QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
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QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
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QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
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QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
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/* PLL and Loop filter settings */
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QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
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QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
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QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
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QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
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QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
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QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
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QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
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QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
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/* SSC settings */
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
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QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
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};
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static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
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QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
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QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
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QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
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QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
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QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
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QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
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};
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static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
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QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
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};
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static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
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QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
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@ -1593,6 +1668,30 @@ static const char * const qmp_phy_vreg_l[] = {
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"vdda-phy", "vdda-pll",
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};
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static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
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.type = PHY_TYPE_USB3,
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.nlanes = 1,
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.serdes_tbl = ipq8074_usb3_serdes_tbl,
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.serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
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.tx_tbl = msm8996_usb3_tx_tbl,
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.tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
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.rx_tbl = ipq8074_usb3_rx_tbl,
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.rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
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.pcs_tbl = ipq8074_usb3_pcs_tbl,
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.pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
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.clk_list = msm8996_phy_clk_l,
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.num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
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.reset_list = msm8996_usb3phy_reset_l,
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.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
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.vreg_list = qmp_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
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.regs = usb3phy_regs_layout,
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.start_ctrl = SERDES_START | PCS_START,
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.pwrdn_ctrl = SW_PWRDN,
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};
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static const struct qmp_phy_cfg msm8996_pciephy_cfg = {
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.type = PHY_TYPE_PCIE,
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.nlanes = 3,
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@ -2699,6 +2798,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id)
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static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
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{
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.compatible = "qcom,ipq8074-qmp-usb3-phy",
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.data = &ipq8074_usb3phy_cfg,
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}, {
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.compatible = "qcom,msm8996-qmp-pcie-phy",
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.data = &msm8996_pciephy_cfg,
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}, {
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