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iwlwifi: virtualize SRAM access
Different transports implement the access to the SRAM in different ways. Virtualize it. Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Johannes Berg <johannes.berg@intel.com>
This commit is contained in:
parent
7a65d17053
commit
4fd442db98
@ -157,7 +157,7 @@ static ssize_t iwl_dbgfs_sram_read(struct file *file,
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sram = priv->dbgfs_sram_offset & ~0x3;
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/* read the first u32 from sram */
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val = iwl_read_targ_mem(priv->trans, sram);
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val = iwl_trans_read_mem32(priv->trans, sram);
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for (; len; len--) {
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/* put the address at the start of every line */
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@ -176,7 +176,7 @@ static ssize_t iwl_dbgfs_sram_read(struct file *file,
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if (++offset == 4) {
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sram += 4;
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offset = 0;
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val = iwl_read_targ_mem(priv->trans, sram);
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val = iwl_trans_read_mem32(priv->trans, sram);
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}
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/* put in extra spaces and split lines for human readability */
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@ -479,7 +479,7 @@ static int iwlagn_mac_resume(struct ieee80211_hw *hw)
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}
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if (priv->wowlan_sram)
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_iwl_read_targ_mem_dwords(
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iwl_trans_read_mem(
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priv->trans, 0x800000,
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priv->wowlan_sram,
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img->sec[IWL_UCODE_SECTION_DATA].len / 4);
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@ -408,7 +408,8 @@ static void iwl_continuous_event_trace(struct iwl_priv *priv)
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base = priv->device_pointers.log_event_table;
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if (iwlagn_hw_valid_rtc_data_addr(base)) {
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iwl_read_targ_mem_bytes(priv->trans, base, &read, sizeof(read));
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iwl_trans_read_mem_bytes(priv->trans, base,
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&read, sizeof(read));
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capacity = read.capacity;
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mode = read.mode;
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num_wraps = read.wrap_counter;
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@ -1627,7 +1628,7 @@ static void iwl_dump_nic_error_log(struct iwl_priv *priv)
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}
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/*TODO: Update dbgfs with ISR error stats obtained below */
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iwl_read_targ_mem_bytes(trans, base, &table, sizeof(table));
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iwl_trans_read_mem_bytes(trans, base, &table, sizeof(table));
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if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
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IWL_ERR(trans, "Start IWL Error Log Dump:\n");
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@ -1835,10 +1836,10 @@ int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
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}
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/* event log header */
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capacity = iwl_read_targ_mem(trans, base);
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mode = iwl_read_targ_mem(trans, base + (1 * sizeof(u32)));
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num_wraps = iwl_read_targ_mem(trans, base + (2 * sizeof(u32)));
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next_entry = iwl_read_targ_mem(trans, base + (3 * sizeof(u32)));
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capacity = iwl_trans_read_mem32(trans, base);
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mode = iwl_trans_read_mem32(trans, base + (1 * sizeof(u32)));
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num_wraps = iwl_trans_read_mem32(trans, base + (2 * sizeof(u32)));
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next_entry = iwl_trans_read_mem32(trans, base + (3 * sizeof(u32)));
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if (capacity > logsize) {
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IWL_ERR(priv, "Log capacity %d is bogus, limit to %d "
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@ -226,59 +226,3 @@ void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask)
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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}
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EXPORT_SYMBOL_GPL(iwl_clear_bits_prph);
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void _iwl_read_targ_mem_dwords(struct iwl_trans *trans, u32 addr,
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void *buf, int dwords)
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{
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unsigned long flags;
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int offs;
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u32 *vals = buf;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (likely(iwl_trans_grab_nic_access(trans, false))) {
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iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
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for (offs = 0; offs < dwords; offs++)
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vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
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iwl_trans_release_nic_access(trans);
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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}
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EXPORT_SYMBOL_GPL(_iwl_read_targ_mem_dwords);
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u32 iwl_read_targ_mem(struct iwl_trans *trans, u32 addr)
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{
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u32 value;
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_iwl_read_targ_mem_dwords(trans, addr, &value, 1);
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return value;
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}
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EXPORT_SYMBOL_GPL(iwl_read_targ_mem);
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int _iwl_write_targ_mem_dwords(struct iwl_trans *trans, u32 addr,
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const void *buf, int dwords)
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{
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unsigned long flags;
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int offs, result = 0;
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const u32 *vals = buf;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (likely(iwl_trans_grab_nic_access(trans, false))) {
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iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
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for (offs = 0; offs < dwords; offs++)
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iwl_write32(trans, HBUS_TARG_MEM_WDAT, vals[offs]);
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iwl_trans_release_nic_access(trans);
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} else {
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result = -EBUSY;
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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return result;
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}
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EXPORT_SYMBOL_GPL(_iwl_write_targ_mem_dwords);
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int iwl_write_targ_mem(struct iwl_trans *trans, u32 addr, u32 val)
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{
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return _iwl_write_targ_mem_dwords(trans, addr, &val, 1);
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}
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EXPORT_SYMBOL_GPL(iwl_write_targ_mem);
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@ -74,19 +74,4 @@ void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs,
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u32 bits, u32 mask);
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void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask);
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void _iwl_read_targ_mem_dwords(struct iwl_trans *trans, u32 addr,
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void *buf, int dwords);
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#define iwl_read_targ_mem_bytes(trans, addr, buf, bufsize) \
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do { \
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BUILD_BUG_ON((bufsize) % sizeof(u32)); \
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_iwl_read_targ_mem_dwords(trans, addr, buf, \
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(bufsize) / sizeof(u32));\
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} while (0)
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int _iwl_write_targ_mem_dwords(struct iwl_trans *trans, u32 addr,
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const void *buf, int dwords);
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u32 iwl_read_targ_mem(struct iwl_trans *trans, u32 addr);
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int iwl_write_targ_mem(struct iwl_trans *trans, u32 addr, u32 val);
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#endif
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@ -476,9 +476,8 @@ static int iwl_test_indirect_read(struct iwl_test *tst, u32 addr, u32 size)
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iwl_trans_release_nic_access(trans);
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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} else { /* target memory (SRAM) */
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_iwl_read_targ_mem_dwords(trans, addr,
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tst->mem.addr,
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tst->mem.size / 4);
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iwl_trans_read_mem(trans, addr, tst->mem.addr,
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tst->mem.size / 4);
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}
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tst->mem.nchunks =
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@ -522,7 +521,7 @@ static int iwl_test_indirect_write(struct iwl_test *tst, u32 addr,
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*(u32 *)(buf+i));
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}
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} else if (iwl_test_valid_hw_addr(tst, addr)) {
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_iwl_write_targ_mem_dwords(trans, addr, buf, size / 4);
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iwl_trans_write_mem(trans, addr, buf, size / 4);
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} else {
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return -EINVAL;
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}
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@ -390,6 +390,8 @@ struct iwl_trans;
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* @read32: read a u32 register at offset ofs from the BAR
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* @read_prph: read a DWORD from a periphery register
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* @write_prph: write a DWORD to a periphery register
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* @read_mem: read device's SRAM in DWORD
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* @write_mem: write device's SRAM in DWORD
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* @configure: configure parameters required by the transport layer from
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* the op_mode. May be called several times before start_fw, can't be
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* called after that.
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@ -430,6 +432,10 @@ struct iwl_trans_ops {
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u32 (*read32)(struct iwl_trans *trans, u32 ofs);
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u32 (*read_prph)(struct iwl_trans *trans, u32 ofs);
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void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val);
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int (*read_mem)(struct iwl_trans *trans, u32 addr,
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void *buf, int dwords);
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int (*write_mem)(struct iwl_trans *trans, u32 addr,
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void *buf, int dwords);
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void (*configure)(struct iwl_trans *trans,
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const struct iwl_trans_config *trans_cfg);
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void (*set_pmi)(struct iwl_trans *trans, bool state);
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@ -645,7 +651,7 @@ static inline int iwl_trans_wait_tx_queue_empty(struct iwl_trans *trans)
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}
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static inline int iwl_trans_dbgfs_register(struct iwl_trans *trans,
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struct dentry *dir)
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struct dentry *dir)
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{
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return trans->ops->dbgfs_register(trans, dir);
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}
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@ -688,6 +694,41 @@ static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs,
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return trans->ops->write_prph(trans, ofs, val);
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}
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static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr,
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void *buf, int dwords)
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{
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return trans->ops->read_mem(trans, addr, buf, dwords);
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}
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#define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \
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do { \
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if (__builtin_constant_p(bufsize)) \
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BUILD_BUG_ON((bufsize) % sizeof(u32)); \
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iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\
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} while (0)
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static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr)
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{
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u32 value;
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if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1)))
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return 0xa5a5a5a5;
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return value;
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}
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static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr,
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void *buf, int dwords)
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{
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return trans->ops->write_mem(trans, addr, buf, dwords);
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}
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static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr,
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u32 val)
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{
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return iwl_trans_write_mem(trans, addr, &val, 1);
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}
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static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state)
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{
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trans->ops->set_pmi(trans, state);
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@ -820,6 +820,45 @@ static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans)
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mmiowb();
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}
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static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
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void *buf, int dwords)
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{
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unsigned long flags;
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int offs, ret = 0;
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u32 *vals = buf;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (likely(iwl_trans_grab_nic_access(trans, false))) {
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iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
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for (offs = 0; offs < dwords; offs++)
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vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
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iwl_trans_release_nic_access(trans);
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} else {
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ret = -EBUSY;
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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return ret;
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}
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static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
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void *buf, int dwords)
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{
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unsigned long flags;
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int offs, ret = 0;
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u32 *vals = buf;
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spin_lock_irqsave(&trans->reg_lock, flags);
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if (likely(iwl_trans_grab_nic_access(trans, false))) {
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iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
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for (offs = 0; offs < dwords; offs++)
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iwl_write32(trans, HBUS_TARG_MEM_WDAT, vals[offs]);
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iwl_trans_release_nic_access(trans);
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} else {
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ret = -EBUSY;
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}
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spin_unlock_irqrestore(&trans->reg_lock, flags);
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return ret;
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}
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#define IWL_FLUSH_WAIT_MS 2000
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@ -1298,6 +1337,8 @@ static const struct iwl_trans_ops trans_ops_pcie = {
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.read32 = iwl_trans_pcie_read32,
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.read_prph = iwl_trans_pcie_read_prph,
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.write_prph = iwl_trans_pcie_write_prph,
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.read_mem = iwl_trans_pcie_read_mem,
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.write_mem = iwl_trans_pcie_write_mem,
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.configure = iwl_trans_pcie_configure,
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.set_pmi = iwl_trans_pcie_set_pmi,
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.grab_nic_access = iwl_trans_pcie_grab_nic_access,
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@ -160,7 +160,7 @@ static void iwl_pcie_txq_stuck_timer(unsigned long data)
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IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
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txq->q.read_ptr, txq->q.write_ptr);
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iwl_read_targ_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
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iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
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iwl_print_hex_error(trans, buf, sizeof(buf));
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@ -173,9 +173,9 @@ static void iwl_pcie_txq_stuck_timer(unsigned long data)
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u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
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bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
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u32 tbl_dw =
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iwl_read_targ_mem(trans,
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trans_pcie->scd_base_addr +
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SCD_TRANS_TBL_OFFSET_QUEUE(i));
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iwl_trans_read_mem32(trans,
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trans_pcie->scd_base_addr +
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SCD_TRANS_TBL_OFFSET_QUEUE(i));
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if (i & 0x1)
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tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
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@ -659,16 +659,16 @@ void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
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/* reset conext data memory */
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for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
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a += 4)
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iwl_write_targ_mem(trans, a, 0);
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iwl_trans_write_mem32(trans, a, 0);
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/* reset tx status memory */
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for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
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a += 4)
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iwl_write_targ_mem(trans, a, 0);
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iwl_trans_write_mem32(trans, a, 0);
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for (; a < trans_pcie->scd_base_addr +
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SCD_TRANS_TBL_OFFSET_QUEUE(
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trans->cfg->base_params->num_of_queues);
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a += 4)
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iwl_write_targ_mem(trans, a, 0);
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iwl_trans_write_mem32(trans, a, 0);
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iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
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trans_pcie->scd_bc_tbls.dma >> 10);
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@ -1005,14 +1005,14 @@ static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
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tbl_dw_addr = trans_pcie->scd_base_addr +
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SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
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tbl_dw = iwl_read_targ_mem(trans, tbl_dw_addr);
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tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
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if (txq_id & 0x1)
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tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
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else
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tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
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iwl_write_targ_mem(trans, tbl_dw_addr, tbl_dw);
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iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
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return 0;
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}
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@ -1071,9 +1071,9 @@ void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo,
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iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
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/* Set up Tx window size and frame limit for this queue */
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iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
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iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
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SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
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iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
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iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
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SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
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((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
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SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
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@ -1104,8 +1104,8 @@ void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id)
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iwl_pcie_txq_set_inactive(trans, txq_id);
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_iwl_write_targ_mem_dwords(trans, stts_addr,
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zero_val, ARRAY_SIZE(zero_val));
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iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
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ARRAY_SIZE(zero_val));
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iwl_pcie_txq_unmap(trans, txq_id);
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