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net/mlx5: Introduce physical port TC/prio access functions
Add access functions to set and query a physical port TC groups and prio parameters. Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -405,3 +405,79 @@ int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx)
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return 0;
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}
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EXPORT_SYMBOL_GPL(mlx5_query_port_pfc);
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int mlx5_max_tc(struct mlx5_core_dev *mdev)
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{
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u8 num_tc = MLX5_CAP_GEN(mdev, max_tc) ? : 8;
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return num_tc - 1;
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}
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int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc)
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{
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u32 in[MLX5_ST_SZ_DW(qtct_reg)];
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u32 out[MLX5_ST_SZ_DW(qtct_reg)];
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int err;
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int i;
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memset(in, 0, sizeof(in));
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for (i = 0; i < 8; i++) {
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if (prio_tc[i] > mlx5_max_tc(mdev))
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return -EINVAL;
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MLX5_SET(qtct_reg, in, prio, i);
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MLX5_SET(qtct_reg, in, tclass, prio_tc[i]);
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err = mlx5_core_access_reg(mdev, in, sizeof(in), out,
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sizeof(out), MLX5_REG_QTCT, 0, 1);
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if (err)
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return err;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(mlx5_set_port_prio_tc);
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static int mlx5_set_port_qetcr_reg(struct mlx5_core_dev *mdev, u32 *in,
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int inlen)
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{
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u32 out[MLX5_ST_SZ_DW(qtct_reg)];
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if (!MLX5_CAP_GEN(mdev, ets))
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return -ENOTSUPP;
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return mlx5_core_access_reg(mdev, in, inlen, out, sizeof(out),
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MLX5_REG_QETCR, 0, 1);
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}
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int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group)
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{
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u32 in[MLX5_ST_SZ_DW(qetc_reg)];
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int i;
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memset(in, 0, sizeof(in));
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for (i = 0; i <= mlx5_max_tc(mdev); i++) {
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MLX5_SET(qetc_reg, in, tc_configuration[i].g, 1);
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MLX5_SET(qetc_reg, in, tc_configuration[i].group, tc_group[i]);
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}
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return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
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}
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EXPORT_SYMBOL_GPL(mlx5_set_port_tc_group);
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int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw)
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{
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u32 in[MLX5_ST_SZ_DW(qetc_reg)];
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int i;
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memset(in, 0, sizeof(in));
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for (i = 0; i <= mlx5_max_tc(mdev); i++) {
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MLX5_SET(qetc_reg, in, tc_configuration[i].b, 1);
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MLX5_SET(qetc_reg, in, tc_configuration[i].bw_allocation, tc_bw[i]);
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}
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return mlx5_set_port_qetcr_reg(mdev, in, sizeof(in));
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}
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EXPORT_SYMBOL_GPL(mlx5_set_port_tc_bw_alloc);
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@ -99,6 +99,8 @@ enum {
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};
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enum {
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MLX5_REG_QETCR = 0x4005,
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MLX5_REG_QTCT = 0x400a,
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MLX5_REG_PCAP = 0x5001,
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MLX5_REG_PMTU = 0x5003,
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MLX5_REG_PTYS = 0x5004,
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@ -729,7 +729,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
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u8 reserved_at_1bf[0x3];
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u8 log_max_msg[0x5];
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u8 reserved_at_1c7[0x18];
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u8 reserved_at_1c7[0x4];
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u8 max_tc[0x4];
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u8 reserved_at_1cf[0x10];
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u8 stat_rate_support[0x10];
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u8 reserved_at_1ef[0xc];
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@ -7061,4 +7063,49 @@ struct mlx5_ifc_modify_flow_table_in_bits {
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u8 reserved_at_100[0x100];
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};
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struct mlx5_ifc_ets_tcn_config_reg_bits {
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u8 g[0x1];
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u8 b[0x1];
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u8 r[0x1];
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u8 reserved_at_3[0x9];
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u8 group[0x4];
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u8 reserved_at_10[0x9];
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u8 bw_allocation[0x7];
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u8 reserved_at_20[0xc];
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u8 max_bw_units[0x4];
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u8 reserved_at_30[0x8];
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u8 max_bw_value[0x8];
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};
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struct mlx5_ifc_ets_global_config_reg_bits {
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u8 reserved_at_0[0x2];
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u8 r[0x1];
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u8 reserved_at_3[0x1d];
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u8 reserved_at_20[0xc];
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u8 max_bw_units[0x4];
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u8 reserved_at_30[0x8];
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u8 max_bw_value[0x8];
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};
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struct mlx5_ifc_qetc_reg_bits {
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u8 reserved_at_0[0x8];
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u8 port_number[0x8];
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u8 reserved_at_10[0x30];
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struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
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struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
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};
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struct mlx5_ifc_qtct_reg_bits {
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u8 reserved_at_0[0x8];
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u8 port_number[0x8];
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u8 reserved_at_10[0xd];
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u8 prio[0x3];
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u8 reserved_at_20[0x1d];
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u8 tclass[0x3];
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};
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#endif /* MLX5_IFC_H */
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@ -70,4 +70,10 @@ int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx);
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int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx,
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u8 *pfc_en_rx);
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int mlx5_max_tc(struct mlx5_core_dev *mdev);
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int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc);
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int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group);
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int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw);
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#endif /* __MLX5_PORT_H__ */
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