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[ARM] 3789/4: Fix VFP emulation to ignore VECITR for scalar instruction
VECITR in Floating-Point Exception register indicates the number of remaining short vector iterations after a potential exception was detected. In case of exception caused by scalar instructions, VECITR is NOT updated. Therefore emulation for VFP must ignore VECITR field and treat "veclen" as zero when recognizing scalar instructing. Signed-off-by: Gen Fukatsu <fukatsu.gen@jp.panasonic.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Gen FUKATSU
Russell King
parent
f8c440b209
commit
4cc9bd2eaa
@ -355,3 +355,14 @@ u32 vfp_estimate_sqrt_significand(u32 exponent, u32 significand);
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* we check for an error.
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*/
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#define VFP_EXCEPTION_ERROR ((u32)-1 & ~VFP_NAN_FLAG)
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/*
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* A flag to tell vfp instruction type
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*/
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#define OP_SCALAR (1 << 0)
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#define OP_SD (1 << 1)
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struct op {
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u32 (* const fn)(int dd, int dn, int dm, u32 fpscr);
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u32 flags;
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};
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@ -659,22 +659,22 @@ static u32 vfp_double_ftosiz(int dd, int unused, int dm, u32 fpscr)
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}
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static u32 (* const fop_extfns[32])(int dd, int unused, int dm, u32 fpscr) = {
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[FEXT_TO_IDX(FEXT_FCPY)] = vfp_double_fcpy,
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[FEXT_TO_IDX(FEXT_FABS)] = vfp_double_fabs,
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[FEXT_TO_IDX(FEXT_FNEG)] = vfp_double_fneg,
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[FEXT_TO_IDX(FEXT_FSQRT)] = vfp_double_fsqrt,
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[FEXT_TO_IDX(FEXT_FCMP)] = vfp_double_fcmp,
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[FEXT_TO_IDX(FEXT_FCMPE)] = vfp_double_fcmpe,
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[FEXT_TO_IDX(FEXT_FCMPZ)] = vfp_double_fcmpz,
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[FEXT_TO_IDX(FEXT_FCMPEZ)] = vfp_double_fcmpez,
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[FEXT_TO_IDX(FEXT_FCVT)] = vfp_double_fcvts,
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[FEXT_TO_IDX(FEXT_FUITO)] = vfp_double_fuito,
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[FEXT_TO_IDX(FEXT_FSITO)] = vfp_double_fsito,
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[FEXT_TO_IDX(FEXT_FTOUI)] = vfp_double_ftoui,
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[FEXT_TO_IDX(FEXT_FTOUIZ)] = vfp_double_ftouiz,
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[FEXT_TO_IDX(FEXT_FTOSI)] = vfp_double_ftosi,
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[FEXT_TO_IDX(FEXT_FTOSIZ)] = vfp_double_ftosiz,
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static struct op fops_ext[32] = {
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[FEXT_TO_IDX(FEXT_FCPY)] = {vfp_double_fcpy, 0},
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[FEXT_TO_IDX(FEXT_FABS)] = {vfp_double_fabs, 0},
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[FEXT_TO_IDX(FEXT_FNEG)] = {vfp_double_fneg, 0},
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[FEXT_TO_IDX(FEXT_FSQRT)] = {vfp_double_fsqrt, 0},
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[FEXT_TO_IDX(FEXT_FCMP)] = {vfp_double_fcmp, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FCMPE)] = {vfp_double_fcmpe, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FCMPZ)] = {vfp_double_fcmpz, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FCMPEZ)] = {vfp_double_fcmpez, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FCVT)] = {vfp_double_fcvts, (OP_SD|OP_SCALAR)},
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[FEXT_TO_IDX(FEXT_FUITO)] = {vfp_double_fuito, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FSITO)] = {vfp_double_fsito, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FTOUI)] = {vfp_double_ftoui, (OP_SD|OP_SCALAR)},
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[FEXT_TO_IDX(FEXT_FTOUIZ)] = {vfp_double_ftouiz, (OP_SD|OP_SCALAR)},
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[FEXT_TO_IDX(FEXT_FTOSI)] = {vfp_double_ftosi, (OP_SD|OP_SCALAR)},
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[FEXT_TO_IDX(FEXT_FTOSIZ)] = {vfp_double_ftosiz, (OP_SD|OP_SCALAR)},
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};
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@ -1108,16 +1108,16 @@ static u32 vfp_double_fdiv(int dd, int dn, int dm, u32 fpscr)
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return FPSCR_IOC;
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}
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static u32 (* const fop_fns[16])(int dd, int dn, int dm, u32 fpscr) = {
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[FOP_TO_IDX(FOP_FMAC)] = vfp_double_fmac,
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[FOP_TO_IDX(FOP_FNMAC)] = vfp_double_fnmac,
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[FOP_TO_IDX(FOP_FMSC)] = vfp_double_fmsc,
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[FOP_TO_IDX(FOP_FNMSC)] = vfp_double_fnmsc,
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[FOP_TO_IDX(FOP_FMUL)] = vfp_double_fmul,
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[FOP_TO_IDX(FOP_FNMUL)] = vfp_double_fnmul,
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[FOP_TO_IDX(FOP_FADD)] = vfp_double_fadd,
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[FOP_TO_IDX(FOP_FSUB)] = vfp_double_fsub,
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[FOP_TO_IDX(FOP_FDIV)] = vfp_double_fdiv,
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static struct op fops[16] = {
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[FOP_TO_IDX(FOP_FMAC)] = {vfp_double_fmac, 0},
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[FOP_TO_IDX(FOP_FNMAC)] = {vfp_double_fnmac, 0},
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[FOP_TO_IDX(FOP_FMSC)] = {vfp_double_fmsc, 0},
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[FOP_TO_IDX(FOP_FNMSC)] = {vfp_double_fnmsc, 0},
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[FOP_TO_IDX(FOP_FMUL)] = {vfp_double_fmul, 0},
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[FOP_TO_IDX(FOP_FNMUL)] = {vfp_double_fnmul, 0},
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[FOP_TO_IDX(FOP_FADD)] = {vfp_double_fadd, 0},
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[FOP_TO_IDX(FOP_FSUB)] = {vfp_double_fsub, 0},
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[FOP_TO_IDX(FOP_FDIV)] = {vfp_double_fdiv, 0},
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};
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#define FREG_BANK(x) ((x) & 0x0c)
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@ -1131,39 +1131,39 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr)
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unsigned int dn = vfp_get_dn(inst);
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unsigned int dm = vfp_get_dm(inst);
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unsigned int vecitr, veclen, vecstride;
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u32 (*fop)(int, int, s32, u32);
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struct op *fop;
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veclen = fpscr & FPSCR_LENGTH_MASK;
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vecstride = (1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK)) * 2;
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fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)];
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/*
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* fcvtds takes an sN register number as destination, not dN.
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* It also always operates on scalars.
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*/
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if ((inst & FEXT_MASK) == FEXT_FCVT) {
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veclen = 0;
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if (fop->flags & OP_SD)
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dest = vfp_get_sd(inst);
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} else
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else
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dest = vfp_get_dd(inst);
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/*
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* If destination bank is zero, vector length is always '1'.
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* ARM DDI0100F C5.1.3, C5.3.2.
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*/
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if (FREG_BANK(dest) == 0)
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if ((fop->flags & OP_SCALAR) || (FREG_BANK(dest) == 0))
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veclen = 0;
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else
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veclen = fpscr & FPSCR_LENGTH_MASK;
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pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride,
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(veclen >> FPSCR_LENGTH_BIT) + 1);
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fop = (op == FOP_EXT) ? fop_extfns[FEXT_TO_IDX(inst)] : fop_fns[FOP_TO_IDX(op)];
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if (!fop)
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if (!fop->fn)
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goto invalid;
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for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) {
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u32 except;
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if (op == FOP_EXT && (inst & FEXT_MASK) == FEXT_FCVT)
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if (op == FOP_EXT && (fop->flags & OP_SD))
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pr_debug("VFP: itr%d (s%u) = op[%u] (d%u)\n",
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vecitr >> FPSCR_LENGTH_BIT,
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dest, dn, dm);
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@ -1176,7 +1176,7 @@ u32 vfp_double_cpdo(u32 inst, u32 fpscr)
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vecitr >> FPSCR_LENGTH_BIT,
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dest, dn, FOP_TO_IDX(op), dm);
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except = fop(dest, dn, dm, fpscr);
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except = fop->fn(dest, dn, dm, fpscr);
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pr_debug("VFP: itr%d: exceptions=%08x\n",
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vecitr >> FPSCR_LENGTH_BIT, except);
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@ -702,22 +702,22 @@ static u32 vfp_single_ftosiz(int sd, int unused, s32 m, u32 fpscr)
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return vfp_single_ftosi(sd, unused, m, FPSCR_ROUND_TOZERO);
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}
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static u32 (* const fop_extfns[32])(int sd, int unused, s32 m, u32 fpscr) = {
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[FEXT_TO_IDX(FEXT_FCPY)] = vfp_single_fcpy,
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[FEXT_TO_IDX(FEXT_FABS)] = vfp_single_fabs,
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[FEXT_TO_IDX(FEXT_FNEG)] = vfp_single_fneg,
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[FEXT_TO_IDX(FEXT_FSQRT)] = vfp_single_fsqrt,
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[FEXT_TO_IDX(FEXT_FCMP)] = vfp_single_fcmp,
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[FEXT_TO_IDX(FEXT_FCMPE)] = vfp_single_fcmpe,
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[FEXT_TO_IDX(FEXT_FCMPZ)] = vfp_single_fcmpz,
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[FEXT_TO_IDX(FEXT_FCMPEZ)] = vfp_single_fcmpez,
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[FEXT_TO_IDX(FEXT_FCVT)] = vfp_single_fcvtd,
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[FEXT_TO_IDX(FEXT_FUITO)] = vfp_single_fuito,
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[FEXT_TO_IDX(FEXT_FSITO)] = vfp_single_fsito,
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[FEXT_TO_IDX(FEXT_FTOUI)] = vfp_single_ftoui,
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[FEXT_TO_IDX(FEXT_FTOUIZ)] = vfp_single_ftouiz,
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[FEXT_TO_IDX(FEXT_FTOSI)] = vfp_single_ftosi,
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[FEXT_TO_IDX(FEXT_FTOSIZ)] = vfp_single_ftosiz,
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static struct op fops_ext[32] = {
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[FEXT_TO_IDX(FEXT_FCPY)] = {vfp_single_fcpy, 0},
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[FEXT_TO_IDX(FEXT_FABS)] = {vfp_single_fabs, 0},
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[FEXT_TO_IDX(FEXT_FNEG)] = {vfp_single_fneg, 0},
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[FEXT_TO_IDX(FEXT_FSQRT)] = {vfp_single_fsqrt, 0},
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[FEXT_TO_IDX(FEXT_FCMP)] = {vfp_single_fcmp, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FCMPE)] = {vfp_single_fcmpe, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FCMPZ)] = {vfp_single_fcmpz, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FCMPEZ)] = {vfp_single_fcmpez, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FCVT)] = {vfp_single_fcvtd, (OP_SD|OP_SCALAR)},
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[FEXT_TO_IDX(FEXT_FUITO)] = {vfp_single_fuito, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FSITO)] = {vfp_single_fsito, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FTOUI)] = {vfp_single_ftoui, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FTOUIZ)] = {vfp_single_ftouiz, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FTOSI)] = {vfp_single_ftosi, OP_SCALAR},
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[FEXT_TO_IDX(FEXT_FTOSIZ)] = {vfp_single_ftosiz, OP_SCALAR},
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};
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@ -1151,16 +1151,16 @@ static u32 vfp_single_fdiv(int sd, int sn, s32 m, u32 fpscr)
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return FPSCR_IOC;
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}
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static u32 (* const fop_fns[16])(int sd, int sn, s32 m, u32 fpscr) = {
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[FOP_TO_IDX(FOP_FMAC)] = vfp_single_fmac,
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[FOP_TO_IDX(FOP_FNMAC)] = vfp_single_fnmac,
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[FOP_TO_IDX(FOP_FMSC)] = vfp_single_fmsc,
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[FOP_TO_IDX(FOP_FNMSC)] = vfp_single_fnmsc,
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[FOP_TO_IDX(FOP_FMUL)] = vfp_single_fmul,
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[FOP_TO_IDX(FOP_FNMUL)] = vfp_single_fnmul,
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[FOP_TO_IDX(FOP_FADD)] = vfp_single_fadd,
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[FOP_TO_IDX(FOP_FSUB)] = vfp_single_fsub,
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[FOP_TO_IDX(FOP_FDIV)] = vfp_single_fdiv,
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static struct op fops[16] = {
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[FOP_TO_IDX(FOP_FMAC)] = {vfp_single_fmac, 0},
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[FOP_TO_IDX(FOP_FNMAC)] = {vfp_single_fnmac, 0},
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[FOP_TO_IDX(FOP_FMSC)] = {vfp_single_fmsc, 0},
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[FOP_TO_IDX(FOP_FNMSC)] = {vfp_single_fnmsc, 0},
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[FOP_TO_IDX(FOP_FMUL)] = {vfp_single_fmul, 0},
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[FOP_TO_IDX(FOP_FNMUL)] = {vfp_single_fnmul, 0},
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[FOP_TO_IDX(FOP_FADD)] = {vfp_single_fadd, 0},
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[FOP_TO_IDX(FOP_FSUB)] = {vfp_single_fsub, 0},
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[FOP_TO_IDX(FOP_FDIV)] = {vfp_single_fdiv, 0},
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};
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#define FREG_BANK(x) ((x) & 0x18)
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@ -1174,19 +1174,18 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr)
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unsigned int sn = vfp_get_sn(inst);
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unsigned int sm = vfp_get_sm(inst);
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unsigned int vecitr, veclen, vecstride;
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u32 (*fop)(int, int, s32, u32);
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struct op *fop;
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veclen = fpscr & FPSCR_LENGTH_MASK;
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vecstride = 1 + ((fpscr & FPSCR_STRIDE_MASK) == FPSCR_STRIDE_MASK);
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fop = (op == FOP_EXT) ? &fops_ext[FEXT_TO_IDX(inst)] : &fops[FOP_TO_IDX(op)];
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/*
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* fcvtsd takes a dN register number as destination, not sN.
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* Technically, if bit 0 of dd is set, this is an invalid
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* instruction. However, we ignore this for efficiency.
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* It also only operates on scalars.
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*/
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if ((inst & FEXT_MASK) == FEXT_FCVT) {
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veclen = 0;
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if (fop->flags & OP_SD) {
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dest = vfp_get_dd(inst);
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} else
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dest = vfp_get_sd(inst);
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@ -1195,21 +1194,22 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr)
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* If destination bank is zero, vector length is always '1'.
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* ARM DDI0100F C5.1.3, C5.3.2.
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*/
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if (FREG_BANK(dest) == 0)
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if ((fop->flags & OP_SCALAR) || (FREG_BANK(dest) == 0))
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veclen = 0;
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else
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veclen = fpscr & FPSCR_LENGTH_MASK;
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pr_debug("VFP: vecstride=%u veclen=%u\n", vecstride,
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(veclen >> FPSCR_LENGTH_BIT) + 1);
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fop = (op == FOP_EXT) ? fop_extfns[FEXT_TO_IDX(inst)] : fop_fns[FOP_TO_IDX(op)];
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if (!fop)
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if (!fop->fn)
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goto invalid;
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for (vecitr = 0; vecitr <= veclen; vecitr += 1 << FPSCR_LENGTH_BIT) {
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s32 m = vfp_get_float(sm);
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u32 except;
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if (op == FOP_EXT && (inst & FEXT_MASK) == FEXT_FCVT)
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if (op == FOP_EXT && (fop->flags & OP_SD))
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pr_debug("VFP: itr%d (d%u) = op[%u] (s%u=%08x)\n",
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vecitr >> FPSCR_LENGTH_BIT, dest, sn, sm, m);
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else if (op == FOP_EXT)
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@ -1220,7 +1220,7 @@ u32 vfp_single_cpdo(u32 inst, u32 fpscr)
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vecitr >> FPSCR_LENGTH_BIT, dest, sn,
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FOP_TO_IDX(op), sm, m);
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except = fop(dest, sn, m, fpscr);
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except = fop->fn(dest, sn, m, fpscr);
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pr_debug("VFP: itr%d: exceptions=%08x\n",
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vecitr >> FPSCR_LENGTH_BIT, except);
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