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drm/amdgpu: enable UVD context buffer for older HW
Supported starting on certain FW versions. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1681,6 +1681,7 @@ struct amdgpu_uvd {
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struct amdgpu_ring ring;
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struct amdgpu_irq_src irq;
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bool address_64_bit;
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bool use_ctx_buf;
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struct amd_sched_entity entity;
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};
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@ -41,8 +41,15 @@
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/* 1 second timeout */
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#define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000)
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/* Firmware versions for VI */
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#define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8))
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#define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8))
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#define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8))
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#define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8))
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/* Polaris10/11 firmware version */
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#define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
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#define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8))
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/* Firmware Names */
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#ifdef CONFIG_DRM_AMDGPU_CIK
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@ -245,6 +252,23 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
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if (!amdgpu_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0))
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adev->uvd.address_64_bit = true;
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switch (adev->asic_type) {
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case CHIP_TONGA:
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adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10;
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break;
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case CHIP_CARRIZO:
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adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11;
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break;
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case CHIP_FIJI:
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adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12;
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break;
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case CHIP_STONEY:
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adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15;
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break;
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default:
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adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10;
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}
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return 0;
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}
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@ -554,7 +578,7 @@ static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg,
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/* reference picture buffer */
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min_dpb_size = image_size * num_dpb_buffer;
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if (adev->asic_type < CHIP_POLARIS10){
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if (!adev->uvd.use_ctx_buf){
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/* macroblock context buffer */
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min_dpb_size +=
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width_in_mb * height_in_mb * num_dpb_buffer * 192;
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