net: dsa: mv88e6xxx: use BMCR definitions for serdes control register

The SGMII/1000base-X serdes register set is a clause 22 register set
offset at 0x2000 in the PHYXS device. Rather than inventing our own
defintions, use those that already exist, and name the register
MV88E6390_SGMII_BMCR.  Also remove the unused MV88E6390_SGMII_STATUS
definitions.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Russell King 2020-03-14 10:15:33 +00:00 committed by David S. Miller
parent 87615c96e7
commit 4c8b7350a6
2 changed files with 5 additions and 14 deletions

View File

@ -410,20 +410,18 @@ static int mv88e6390_serdes_power_sgmii(struct mv88e6xxx_chip *chip, u8 lane,
int err;
err = mv88e6390_serdes_read(chip, lane, MDIO_MMD_PHYXS,
MV88E6390_SGMII_CONTROL, &val);
MV88E6390_SGMII_BMCR, &val);
if (err)
return err;
if (up)
new_val = val & ~(MV88E6390_SGMII_CONTROL_RESET |
MV88E6390_SGMII_CONTROL_LOOPBACK |
MV88E6390_SGMII_CONTROL_PDOWN);
new_val = val & ~(BMCR_RESET | BMCR_LOOPBACK | BMCR_PDOWN);
else
new_val = val | MV88E6390_SGMII_CONTROL_PDOWN;
new_val = val | BMCR_PDOWN;
if (val != new_val)
err = mv88e6390_serdes_write(chip, lane, MDIO_MMD_PHYXS,
MV88E6390_SGMII_CONTROL, new_val);
MV88E6390_SGMII_BMCR, new_val);
return err;
}

View File

@ -47,14 +47,7 @@
#define MV88E6390_PCS_CONTROL_1_PDOWN BIT(11)
/* 1000BASE-X and SGMII */
#define MV88E6390_SGMII_CONTROL 0x2000
#define MV88E6390_SGMII_CONTROL_RESET BIT(15)
#define MV88E6390_SGMII_CONTROL_LOOPBACK BIT(14)
#define MV88E6390_SGMII_CONTROL_PDOWN BIT(11)
#define MV88E6390_SGMII_STATUS 0x2001
#define MV88E6390_SGMII_STATUS_AN_DONE BIT(5)
#define MV88E6390_SGMII_STATUS_REMOTE_FAULT BIT(4)
#define MV88E6390_SGMII_STATUS_LINK BIT(2)
#define MV88E6390_SGMII_BMCR (0x2000 + MII_BMCR)
#define MV88E6390_SGMII_INT_ENABLE 0xa001
#define MV88E6390_SGMII_INT_SPEED_CHANGE BIT(14)
#define MV88E6390_SGMII_INT_DUPLEX_CHANGE BIT(13)