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arm64: dts: add dts nodes for MT6779
this adds initial MT6779 dts settings for board support, including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc. Signed-off-by: Hanks Chen <hanks.chen@mediatek.com> Link: https://lore.kernel.org/r/1596115816-11758-3-git-send-email-hanks.chen@mediatek.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Hanks Chen
Matthias Brugger
parent
f74cdb1c4e
commit
4c7a626077
@ -1,6 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt2712-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt6755-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt6779-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt6795-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb
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dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb
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31
arch/arm64/boot/dts/mediatek/mt6779-evb.dts
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31
arch/arm64/boot/dts/mediatek/mt6779-evb.dts
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@ -0,0 +1,31 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Mars.C <mars.cheng@mediatek.com>
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*
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*/
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/dts-v1/;
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#include "mt6779.dtsi"
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/ {
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model = "MediaTek MT6779 EVB";
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compatible = "mediatek,mt6779-evb", "mediatek,mt6779";
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aliases {
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serial0 = &uart0;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0 0x40000000 0 0x1e800000>;
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};
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chosen {
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stdout-path = "serial0:921600n8";
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};
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};
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&uart0 {
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status = "okay";
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};
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271
arch/arm64/boot/dts/mediatek/mt6779.dtsi
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271
arch/arm64/boot/dts/mediatek/mt6779.dtsi
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@ -0,0 +1,271 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Mars.C <mars.cheng@mediatek.com>
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*
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*/
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#include <dt-bindings/clock/mt6779-clk.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/mt6779-pinfunc.h>
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/ {
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compatible = "mediatek,mt6779";
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interrupt-parent = <&sysirq>;
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#address-cells = <2>;
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#size-cells = <2>;
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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enable-method = "psci";
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reg = <0x000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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enable-method = "psci";
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reg = <0x100>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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enable-method = "psci";
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reg = <0x200>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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enable-method = "psci";
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reg = <0x300>;
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};
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cpu4: cpu@4 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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enable-method = "psci";
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reg = <0x400>;
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};
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cpu5: cpu@5 {
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device_type = "cpu";
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compatible = "arm,cortex-a55";
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enable-method = "psci";
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reg = <0x500>;
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};
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cpu6: cpu@6 {
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device_type = "cpu";
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compatible = "arm,cortex-a75";
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enable-method = "psci";
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reg = <0x600>;
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};
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cpu7: cpu@7 {
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device_type = "cpu";
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compatible = "arm,cortex-a75";
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enable-method = "psci";
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reg = <0x700>;
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>;
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};
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clk26m: oscillator@0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "clk26m";
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};
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clk32k: oscillator@1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "clk32k";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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gic: interrupt-controller@0c000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <4>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0 0x0c000000 0 0x40000>, /* GICD */
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<0 0x0c040000 0 0x200000>; /* GICR */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
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ppi-partitions {
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ppi_cluster0: interrupt-partition-0 {
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affinity = <&cpu0 &cpu1 \
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&cpu2 &cpu3 &cpu4 &cpu5>;
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};
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ppi_cluster1: interrupt-partition-1 {
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affinity = <&cpu6 &cpu7>;
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};
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};
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};
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sysirq: intpol-controller@0c53a650 {
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compatible = "mediatek,mt6779-sysirq",
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"mediatek,mt6577-sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0 0x0c53a650 0 0x50>;
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};
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topckgen: clock-controller@10000000 {
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compatible = "mediatek,mt6779-topckgen", "syscon";
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reg = <0 0x10000000 0 0x1000>;
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#clock-cells = <1>;
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};
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infracfg_ao: clock-controller@10001000 {
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compatible = "mediatek,mt6779-infracfg_ao", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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};
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt6779-pinctrl", "syscon";
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reg = <0 0x10005000 0 0x1000>,
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<0 0x11c20000 0 0x1000>,
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<0 0x11d10000 0 0x1000>,
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<0 0x11e20000 0 0x1000>,
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<0 0x11e70000 0 0x1000>,
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<0 0x11ea0000 0 0x1000>,
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<0 0x11f20000 0 0x1000>,
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<0 0x11f30000 0 0x1000>,
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<0 0x1000b000 0 0x1000>;
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reg-names = "gpio", "iocfg_rm",
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"iocfg_br", "iocfg_lm",
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"iocfg_lb", "iocfg_rt",
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"iocfg_lt", "iocfg_tl",
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"eint";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pio 0 0 210>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
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};
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apmixed: clock-controller@1000c000 {
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compatible = "mediatek,mt6779-apmixed", "syscon";
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reg = <0 0x1000c000 0 0xe00>;
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#clock-cells = <1>;
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt6779-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x400>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART0>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,mt6779-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x400>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt6779-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11004000 0 0x400>;
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interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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audio: clock-controller@11210000 {
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compatible = "mediatek,mt6779-audio", "syscon";
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reg = <0 0x11210000 0 0x1000>;
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#clock-cells = <1>;
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};
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mfgcfg: clock-controller@13fbf000 {
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compatible = "mediatek,mt6779-mfgcfg", "syscon";
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reg = <0 0x13fbf000 0 0x1000>;
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#clock-cells = <1>;
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};
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mmsys: syscon@14000000 {
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compatible = "mediatek,mt6779-mmsys", "syscon";
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reg = <0 0x14000000 0 0x1000>;
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#clock-cells = <1>;
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};
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imgsys: clock-controller@15020000 {
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compatible = "mediatek,mt6779-imgsys", "syscon";
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reg = <0 0x15020000 0 0x1000>;
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#clock-cells = <1>;
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};
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vdecsys: clock-controller@16000000 {
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compatible = "mediatek,mt6779-vdecsys", "syscon";
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reg = <0 0x16000000 0 0x1000>;
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#clock-cells = <1>;
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};
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vencsys: clock-controller@17000000 {
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compatible = "mediatek,mt6779-vencsys", "syscon";
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reg = <0 0x17000000 0 0x1000>;
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#clock-cells = <1>;
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};
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camsys: clock-controller@1a000000 {
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compatible = "mediatek,mt6779-camsys", "syscon";
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reg = <0 0x1a000000 0 0x10000>;
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#clock-cells = <1>;
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};
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ipesys: clock-controller@1b000000 {
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compatible = "mediatek,mt6779-ipesys", "syscon";
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reg = <0 0x1b000000 0 0x1000>;
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#clock-cells = <1>;
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};
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};
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};
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