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mfd: rtsx: Support RTS5249
RTS5249 supports SD UHS-II interface. In order to support SD UHS-II，the definitions of some internal registers of RTS5249 have to be modified and are different from its predecessors. So we need this patch to ensure RTS5249 can work, even SD/MMC stack doesn't support UHS-II interface. Signed-off-by: Wei WANG <wei_wang@realsil.com.cn> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This commit is contained in:
Wei WANG
Samuel Ortiz
parent
95e50f6a2f
commit
4c4b8c105a
@ -12,7 +12,7 @@ obj-$(CONFIG_MFD_CROS_EC) += cros_ec.o
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obj-$(CONFIG_MFD_CROS_EC_I2C) += cros_ec_i2c.o
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obj-$(CONFIG_MFD_CROS_EC_SPI) += cros_ec_spi.o
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rtsx_pci-objs := rtsx_pcr.o rts5209.o rts5229.o rtl8411.o rts5227.o
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rtsx_pci-objs := rtsx_pcr.o rts5209.o rts5229.o rtl8411.o rts5227.o rts5249.o
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obj-$(CONFIG_MFD_RTSX_PCI) += rtsx_pci.o
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obj-$(CONFIG_HTC_EGPIO) += htc-egpio.o
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241
drivers/mfd/rts5249.c
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241
drivers/mfd/rts5249.c
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@ -0,0 +1,241 @@
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/* Driver for Realtek PCI-Express card reader
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*
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* Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2, or (at your option) any
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* later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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* Author:
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* Wei WANG <wei_wang@realsil.com.cn>
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* No. 128, West Shenhu Road, Suzhou Industry Park, Suzhou, China
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/mfd/rtsx_pci.h>
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#include "rtsx_pcr.h"
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static u8 rts5249_get_ic_version(struct rtsx_pcr *pcr)
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{
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u8 val;
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rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
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return val & 0x0F;
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}
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static int rts5249_extra_init_hw(struct rtsx_pcr *pcr)
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{
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rtsx_pci_init_cmd(pcr);
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/* Configure GPIO as output */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
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/* Switch LDO3318 source from DV33 to card_3v3 */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
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/* LED shine disabled, set initial shine cycle period */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
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/* Correct driving */
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
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SD30_CLK_DRIVE_SEL, 0xFF, 0x99);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
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SD30_CMD_DRIVE_SEL, 0xFF, 0x99);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD,
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SD30_DAT_DRIVE_SEL, 0xFF, 0x92);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static int rts5249_optimize_phy(struct rtsx_pcr *pcr)
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{
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int err;
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err = rtsx_pci_write_phy_register(pcr, PHY_REG_REV, 0xFE46);
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if (err < 0)
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return err;
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msleep(1);
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return rtsx_pci_write_phy_register(pcr, PHY_BPCR, 0x05C0);
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}
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static int rts5249_turn_on_led(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
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}
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static int rts5249_turn_off_led(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
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}
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static int rts5249_enable_auto_blink(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
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}
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static int rts5249_disable_auto_blink(struct rtsx_pcr *pcr)
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{
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return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
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}
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static int rts5249_card_power_on(struct rtsx_pcr *pcr, int card)
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{
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int err;
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rtsx_pci_init_cmd(pcr);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
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SD_POWER_MASK, SD_VCC_PARTIAL_POWER_ON);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
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LDO3318_PWR_MASK, 0x02);
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err = rtsx_pci_send_cmd(pcr, 100);
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if (err < 0)
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return err;
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msleep(5);
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rtsx_pci_init_cmd(pcr);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
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SD_POWER_MASK, SD_VCC_POWER_ON);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
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LDO3318_PWR_MASK, 0x06);
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err = rtsx_pci_send_cmd(pcr, 100);
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if (err < 0)
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return err;
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return 0;
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}
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static int rts5249_card_power_off(struct rtsx_pcr *pcr, int card)
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{
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rtsx_pci_init_cmd(pcr);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
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SD_POWER_MASK, SD_POWER_OFF);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
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LDO3318_PWR_MASK, 0x00);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static int rts5249_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
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{
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int err;
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u8 clk_drive, cmd_drive, dat_drive;
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if (voltage == OUTPUT_3V3) {
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err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4FC0 | 0x24);
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if (err < 0)
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return err;
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clk_drive = 0x99;
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cmd_drive = 0x99;
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dat_drive = 0x92;
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} else if (voltage == OUTPUT_1V8) {
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err = rtsx_pci_write_phy_register(pcr, PHY_BACR, 0x3C02);
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if (err < 0)
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return err;
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err = rtsx_pci_write_phy_register(pcr, PHY_TUNE, 0x4C40 | 0x24);
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if (err < 0)
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return err;
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clk_drive = 0xb3;
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cmd_drive = 0xb3;
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dat_drive = 0xb3;
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} else {
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return -EINVAL;
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}
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/* set pad drive */
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rtsx_pci_init_cmd(pcr);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
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0xFF, clk_drive);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
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0xFF, cmd_drive);
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rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
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0xFF, dat_drive);
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return rtsx_pci_send_cmd(pcr, 100);
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}
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static const struct pcr_ops rts5249_pcr_ops = {
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.extra_init_hw = rts5249_extra_init_hw,
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.optimize_phy = rts5249_optimize_phy,
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.turn_on_led = rts5249_turn_on_led,
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.turn_off_led = rts5249_turn_off_led,
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.enable_auto_blink = rts5249_enable_auto_blink,
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.disable_auto_blink = rts5249_disable_auto_blink,
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.card_power_on = rts5249_card_power_on,
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.card_power_off = rts5249_card_power_off,
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.switch_output_voltage = rts5249_switch_output_voltage,
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};
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/* SD Pull Control Enable:
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* SD_DAT[3:0] ==> pull up
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* SD_CD ==> pull up
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* SD_WP ==> pull up
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* SD_CMD ==> pull up
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* SD_CLK ==> pull down
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*/
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static const u32 rts5249_sd_pull_ctl_enable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
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RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
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RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
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RTSX_REG_PAIR(CARD_PULL_CTL4, 0xAA),
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0,
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};
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/* SD Pull Control Disable:
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* SD_DAT[3:0] ==> pull down
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* SD_CD ==> pull up
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* SD_WP ==> pull down
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* SD_CMD ==> pull down
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* SD_CLK ==> pull down
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*/
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static const u32 rts5249_sd_pull_ctl_disable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL1, 0x66),
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RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
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RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
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0,
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};
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/* MS Pull Control Enable:
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* MS CD ==> pull up
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* others ==> pull down
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*/
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static const u32 rts5249_ms_pull_ctl_enable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
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0,
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};
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/* MS Pull Control Disable:
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* MS CD ==> pull up
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* others ==> pull down
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*/
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static const u32 rts5249_ms_pull_ctl_disable_tbl[] = {
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RTSX_REG_PAIR(CARD_PULL_CTL4, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
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RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
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0,
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};
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void rts5249_init_params(struct rtsx_pcr *pcr)
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{
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pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
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pcr->num_slots = 2;
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pcr->ops = &rts5249_pcr_ops;
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pcr->ic_version = rts5249_get_ic_version(pcr);
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pcr->sd_pull_ctl_enable_tbl = rts5249_sd_pull_ctl_enable_tbl;
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pcr->sd_pull_ctl_disable_tbl = rts5249_sd_pull_ctl_disable_tbl;
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pcr->ms_pull_ctl_enable_tbl = rts5249_ms_pull_ctl_enable_tbl;
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pcr->ms_pull_ctl_disable_tbl = rts5249_ms_pull_ctl_disable_tbl;
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}
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@ -56,6 +56,7 @@ static DEFINE_PCI_DEVICE_TABLE(rtsx_pci_ids) = {
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{ PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS << 16, 0xFF0000 },
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{ PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS << 16, 0xFF0000 },
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{ PCI_DEVICE(0x10EC, 0x5227), PCI_CLASS_OTHERS << 16, 0xFF0000 },
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{ PCI_DEVICE(0x10EC, 0x5249), PCI_CLASS_OTHERS << 16, 0xFF0000 },
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{ 0, }
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};
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@ -1033,6 +1034,10 @@ static int rtsx_pci_init_chip(struct rtsx_pcr *pcr)
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case 0x5227:
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rts5227_init_params(pcr);
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break;
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case 0x5249:
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rts5249_init_params(pcr);
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break;
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}
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dev_dbg(&(pcr->pci->dev), "PID: 0x%04x, IC version: 0x%02x\n",
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@ -32,5 +32,6 @@ void rts5209_init_params(struct rtsx_pcr *pcr);
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void rts5229_init_params(struct rtsx_pcr *pcr);
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void rtl8411_init_params(struct rtsx_pcr *pcr);
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void rts5227_init_params(struct rtsx_pcr *pcr);
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void rts5249_init_params(struct rtsx_pcr *pcr);
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#endif
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@ -500,6 +500,8 @@
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#define BPP_POWER_15_PERCENT_ON 0x08
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#define BPP_POWER_ON 0x00
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#define BPP_POWER_MASK 0x0F
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#define SD_VCC_PARTIAL_POWER_ON 0x02
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#define SD_VCC_POWER_ON 0x00
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/* PWR_GATE_CTRL */
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#define PWR_GATE_EN 0x01
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@ -689,6 +691,40 @@
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#define IMAGE_FLAG_ADDR0 0xCE80
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#define IMAGE_FLAG_ADDR1 0xCE81
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/* Phy register */
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#define PHY_PCR 0x00
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#define PHY_RCR0 0x01
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#define PHY_RCR1 0x02
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#define PHY_RCR2 0x03
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#define PHY_RTCR 0x04
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#define PHY_RDR 0x05
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#define PHY_TCR0 0x06
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#define PHY_TCR1 0x07
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#define PHY_TUNE 0x08
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#define PHY_IMR 0x09
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#define PHY_BPCR 0x0A
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#define PHY_BIST 0x0B
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#define PHY_RAW_L 0x0C
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#define PHY_RAW_H 0x0D
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#define PHY_RAW_DATA 0x0E
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#define PHY_HOST_CLK_CTRL 0x0F
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#define PHY_DMR 0x10
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#define PHY_BACR 0x11
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#define PHY_IER 0x12
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#define PHY_BCSR 0x13
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#define PHY_BPR 0x14
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#define PHY_BPNR2 0x15
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#define PHY_BPNR 0x16
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#define PHY_BRNR2 0x17
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#define PHY_BENR 0x18
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#define PHY_REG_REV 0x19
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#define PHY_FLD0 0x1A
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#define PHY_FLD1 0x1B
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#define PHY_FLD2 0x1C
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#define PHY_FLD3 0x1D
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#define PHY_FLD4 0x1E
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#define PHY_DUM_REG 0x1F
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#define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0)
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struct rtsx_pcr;
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