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ide: add struct ide_io_ports (take 3)
* Add struct ide_io_ports and use it instead of `unsigned long io_ports[]` in ide_hwif_t. * Rename io_ports[] in hw_regs_t to io_ports_array[]. * Use un-named union for 'unsigned long io_ports_array[]' and 'struct ide_io_ports io_ports' in hw_regs_t. * Remove IDE_*_OFFSET defines. v2: * scc_pata.c build fix from Stephen Rothwell. v3: * Fix ctl_adrr typo in Sparc-specific part of ns87415.c. (Noticed by Andrew Morton) Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
This commit is contained in:
parent
387750c3bf
commit
4c3032d8a4
@ -35,12 +35,12 @@ static int __init bastide_register(unsigned int base, unsigned int aux, int irq)
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base += BAST_IDE_CS;
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base += BAST_IDE_CS;
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aux += BAST_IDE_CS;
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aux += BAST_IDE_CS;
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for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
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for (i = 0; i <= 7; i++) {
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hw.io_ports[i] = (unsigned long)base;
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hw.io_ports_array[i] = (unsigned long)base;
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base += 0x20;
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base += 0x20;
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}
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}
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hw.io_ports[IDE_CONTROL_OFFSET] = aux + (6 * 0x20);
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hw.io_ports.ctl_addr = aux + (6 * 0x20);
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hw.irq = irq;
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hw.irq = irq;
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hwif = ide_find_port();
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hwif = ide_find_port();
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@ -426,11 +426,12 @@ icside_setup(void __iomem *base, struct cardinfo *info, struct expansion_card *e
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*/
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*/
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default_hwif_mmiops(hwif);
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default_hwif_mmiops(hwif);
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for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
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for (i = 0; i <= 7; i++) {
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hwif->io_ports[i] = port;
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hwif->io_ports_array[i] = port;
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port += 1 << info->stepping;
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port += 1 << info->stepping;
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}
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}
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hwif->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
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hwif->io_ports.ctl_addr =
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(unsigned long)base + info->ctrloffset;
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hwif->irq = ec->irq;
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hwif->irq = ec->irq;
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hwif->chipset = ide_acorn;
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hwif->chipset = ide_acorn;
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hwif->gendev.parent = &ec->dev;
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hwif->gendev.parent = &ec->dev;
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@ -321,7 +321,7 @@ static int __devinit palm_bk3710_init_dma(ide_hwif_t *hwif,
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const struct ide_port_info *d)
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const struct ide_port_info *d)
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{
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{
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unsigned long base =
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unsigned long base =
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hwif->io_ports[IDE_DATA_OFFSET] - IDE_PALM_ATA_PRI_REG_OFFSET;
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hwif->io_ports.data_addr - IDE_PALM_ATA_PRI_REG_OFFSET;
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printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name);
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printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name);
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@ -386,8 +386,8 @@ static int __devinit palm_bk3710_probe(struct platform_device *pdev)
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pribase = mem->start + IDE_PALM_ATA_PRI_REG_OFFSET;
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pribase = mem->start + IDE_PALM_ATA_PRI_REG_OFFSET;
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for (i = 0; i < IDE_NR_PORTS - 2; i++)
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for (i = 0; i < IDE_NR_PORTS - 2; i++)
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hw.io_ports[i] = pribase + i;
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hw.io_ports_array[i] = pribase + i;
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hw.io_ports[IDE_CONTROL_OFFSET] = mem->start +
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hw.io_ports.ctl_addr = mem->start +
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IDE_PALM_ATA_PRI_CTL_OFFSET;
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IDE_PALM_ATA_PRI_CTL_OFFSET;
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hw.irq = irq->start;
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hw.irq = irq->start;
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hw.chipset = ide_palm3710;
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hw.chipset = ide_palm3710;
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@ -17,11 +17,11 @@ static void rapide_setup_ports(hw_regs_t *hw, void __iomem *base,
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unsigned long port = (unsigned long)base;
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unsigned long port = (unsigned long)base;
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int i;
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int i;
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for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
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for (i = 0; i <= 7; i++) {
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hw->io_ports[i] = port;
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hw->io_ports_array[i] = port;
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port += sz;
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port += sz;
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}
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}
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hw->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)ctrl;
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hw->io_ports.ctl_addr = (unsigned long)ctrl;
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hw->irq = irq;
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hw->irq = irq;
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}
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}
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@ -88,8 +88,8 @@ enum /* Transfer types */
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int
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int
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cris_ide_ack_intr(ide_hwif_t* hwif)
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cris_ide_ack_intr(ide_hwif_t* hwif)
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{
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{
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reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2,
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reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int,
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int, hwif->io_ports[0]);
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hwif->io_ports.data_addr);
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REG_WR_INT(ata, regi_ata, rw_ack_intr, 1 << ctrl2.sel);
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REG_WR_INT(ata, regi_ata, rw_ack_intr, 1 << ctrl2.sel);
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return 1;
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return 1;
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}
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}
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@ -231,7 +231,7 @@ cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int dir,int type,
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ide_hwif_t *hwif = drive->hwif;
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ide_hwif_t *hwif = drive->hwif;
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reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int,
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reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int,
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hwif->io_ports[IDE_DATA_OFFSET]);
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hwif->io_ports.data_addr);
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reg_ata_rw_trf_cnt trf_cnt = {0};
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reg_ata_rw_trf_cnt trf_cnt = {0};
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mycontext.saved_data = (dma_descr_data*)virt_to_phys(d);
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mycontext.saved_data = (dma_descr_data*)virt_to_phys(d);
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@ -271,7 +271,7 @@ static int cris_dma_test_irq(ide_drive_t *drive)
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int intr = REG_RD_INT(ata, regi_ata, r_intr);
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int intr = REG_RD_INT(ata, regi_ata, r_intr);
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reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int,
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reg_ata_rw_ctrl2 ctrl2 = REG_TYPE_CONV(reg_ata_rw_ctrl2, int,
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hwif->io_ports[IDE_DATA_OFFSET]);
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hwif->io_ports.data_addr);
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return intr & (1 << ctrl2.sel) ? 1 : 0;
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return intr & (1 << ctrl2.sel) ? 1 : 0;
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}
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}
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@ -531,7 +531,7 @@ static void cris_ide_start_dma(ide_drive_t *drive, cris_dma_descr_type *d, int d
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*R_ATA_CTRL_DATA =
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*R_ATA_CTRL_DATA =
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cmd |
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cmd |
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IO_FIELD(R_ATA_CTRL_DATA, data,
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IO_FIELD(R_ATA_CTRL_DATA, data,
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drive->hwif->io_ports[IDE_DATA_OFFSET]) |
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drive->hwif->io_ports.data_addr) |
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IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
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IO_STATE(R_ATA_CTRL_DATA, src_dst, dma) |
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IO_STATE(R_ATA_CTRL_DATA, multi, on) |
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IO_STATE(R_ATA_CTRL_DATA, multi, on) |
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IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
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IO_STATE(R_ATA_CTRL_DATA, dma_size, word);
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@ -550,7 +550,7 @@ static int cris_dma_test_irq(ide_drive_t *drive)
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{
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{
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int intr = *R_IRQ_MASK0_RD;
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int intr = *R_IRQ_MASK0_RD;
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int bus = IO_EXTRACT(R_ATA_CTRL_DATA, sel,
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int bus = IO_EXTRACT(R_ATA_CTRL_DATA, sel,
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drive->hwif->io_ports[IDE_DATA_OFFSET]);
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drive->hwif->io_ports.data_addr);
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return intr & (1 << (bus + IO_BITNR(R_IRQ_MASK0_RD, ata_irq0))) ? 1 : 0;
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return intr & (1 << (bus + IO_BITNR(R_IRQ_MASK0_RD, ata_irq0))) ? 1 : 0;
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}
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}
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@ -644,7 +644,7 @@ cris_ide_inw(unsigned long reg) {
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* call will also timeout on busy, but as long as the
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* call will also timeout on busy, but as long as the
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* write is still performed, everything will be fine.
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* write is still performed, everything will be fine.
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*/
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*/
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if (cris_ide_get_reg(reg) == IDE_STATUS_OFFSET)
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if (cris_ide_get_reg(reg) == 7)
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return BUSY_STAT;
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return BUSY_STAT;
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else
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else
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/* For other rare cases we assume 0 is good enough. */
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/* For other rare cases we assume 0 is good enough. */
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@ -765,13 +765,13 @@ static void __init cris_setup_ports(hw_regs_t *hw, unsigned long base)
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memset(hw, 0, sizeof(*hw));
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memset(hw, 0, sizeof(*hw));
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for (i = 0; i <= 7; i++)
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for (i = 0; i <= 7; i++)
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hw->io_ports[i] = base + cris_ide_reg_addr(i, 0, 1);
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hw->io_ports_array[i] = base + cris_ide_reg_addr(i, 0, 1);
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/*
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/*
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* the IDE control register is at ATA address 6,
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* the IDE control register is at ATA address 6,
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* with CS1 active instead of CS0
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* with CS1 active instead of CS0
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*/
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*/
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hw->io_ports[IDE_CONTROL_OFFSET] = base + cris_ide_reg_addr(6, 1, 0);
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hw->io_ports.ctl_addr = base + cris_ide_reg_addr(6, 1, 0);
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hw->irq = ide_default_irq(0);
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hw->irq = ide_default_irq(0);
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hw->ack_intr = cris_ide_ack_intr;
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hw->ack_intr = cris_ide_ack_intr;
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@ -63,9 +63,9 @@ static inline void hw_setup(hw_regs_t *hw)
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int i;
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int i;
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memset(hw, 0, sizeof(hw_regs_t));
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memset(hw, 0, sizeof(hw_regs_t));
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for (i = 0; i <= IDE_STATUS_OFFSET; i++)
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for (i = 0; i <= 7; i++)
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hw->io_ports[i] = CONFIG_H8300_IDE_BASE + H8300_IDE_GAP*i;
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hw->io_ports_array[i] = CONFIG_H8300_IDE_BASE + H8300_IDE_GAP*i;
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hw->io_ports[IDE_CONTROL_OFFSET] = CONFIG_H8300_IDE_ALT;
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hw->io_ports.ctl_addr = CONFIG_H8300_IDE_ALT;
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hw->irq = EXT_IRQ0 + CONFIG_H8300_IDE_IRQ;
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hw->irq = EXT_IRQ0 + CONFIG_H8300_IDE_IRQ;
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hw->chipset = ide_generic;
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hw->chipset = ide_generic;
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}
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}
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@ -560,7 +560,7 @@ static ide_startstop_t cdrom_start_packet_command(ide_drive_t *drive,
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/* packet command */
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/* packet command */
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spin_lock_irqsave(&ide_lock, flags);
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spin_lock_irqsave(&ide_lock, flags);
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hwif->OUTBSYNC(drive, WIN_PACKETCMD,
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hwif->OUTBSYNC(drive, WIN_PACKETCMD,
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hwif->io_ports[IDE_COMMAND_OFFSET]);
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hwif->io_ports.command_addr);
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ndelay(400);
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ndelay(400);
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spin_unlock_irqrestore(&ide_lock, flags);
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spin_unlock_irqrestore(&ide_lock, flags);
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@ -952,9 +952,9 @@ static ide_startstop_t cdrom_newpc_intr(ide_drive_t *drive)
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}
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}
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/* ok we fall to pio :/ */
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/* ok we fall to pio :/ */
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ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]) & 0x3;
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ireason = hwif->INB(hwif->io_ports.nsect_addr) & 0x3;
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lowcyl = hwif->INB(hwif->io_ports[IDE_BCOUNTL_OFFSET]);
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lowcyl = hwif->INB(hwif->io_ports.lbam_addr);
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highcyl = hwif->INB(hwif->io_ports[IDE_BCOUNTH_OFFSET]);
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highcyl = hwif->INB(hwif->io_ports.lbah_addr);
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len = lowcyl + (256 * highcyl);
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len = lowcyl + (256 * highcyl);
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@ -465,10 +465,10 @@ static ide_startstop_t idefloppy_pc_intr(ide_drive_t *drive)
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}
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}
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/* Get the number of bytes to transfer */
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/* Get the number of bytes to transfer */
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bcount = (hwif->INB(hwif->io_ports[IDE_BCOUNTH_OFFSET]) << 8) |
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bcount = (hwif->INB(hwif->io_ports.lbah_addr) << 8) |
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hwif->INB(hwif->io_ports[IDE_BCOUNTL_OFFSET]);
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hwif->INB(hwif->io_ports.lbam_addr);
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/* on this interrupt */
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/* on this interrupt */
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ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]);
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ireason = hwif->INB(hwif->io_ports.nsect_addr);
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if (ireason & CD) {
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if (ireason & CD) {
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printk(KERN_ERR "ide-floppy: CoD != 0 in %s\n", __func__);
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printk(KERN_ERR "ide-floppy: CoD != 0 in %s\n", __func__);
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@ -539,7 +539,7 @@ static ide_startstop_t idefloppy_transfer_pc(ide_drive_t *drive)
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"initiated yet DRQ isn't asserted\n");
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"initiated yet DRQ isn't asserted\n");
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return startstop;
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return startstop;
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}
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}
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ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]);
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ireason = hwif->INB(hwif->io_ports.nsect_addr);
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if ((ireason & CD) == 0 || (ireason & IO)) {
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if ((ireason & CD) == 0 || (ireason & IO)) {
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printk(KERN_ERR "ide-floppy: (IO,CoD) != (0,1) while "
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printk(KERN_ERR "ide-floppy: (IO,CoD) != (0,1) while "
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"issuing a packet command\n");
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"issuing a packet command\n");
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@ -586,7 +586,7 @@ static ide_startstop_t idefloppy_transfer_pc1(ide_drive_t *drive)
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"initiated yet DRQ isn't asserted\n");
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"initiated yet DRQ isn't asserted\n");
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return startstop;
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return startstop;
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}
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}
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ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]);
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ireason = hwif->INB(hwif->io_ports.nsect_addr);
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if ((ireason & CD) == 0 || (ireason & IO)) {
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if ((ireason & CD) == 0 || (ireason & IO)) {
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printk(KERN_ERR "ide-floppy: (IO,CoD) != (0,1) "
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printk(KERN_ERR "ide-floppy: (IO,CoD) != (0,1) "
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"while issuing a packet command\n");
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"while issuing a packet command\n");
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@ -692,7 +692,7 @@ static ide_startstop_t idefloppy_issue_pc(ide_drive_t *drive,
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return ide_started;
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return ide_started;
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} else {
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} else {
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/* Issue the packet command */
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/* Issue the packet command */
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hwif->OUTB(WIN_PACKETCMD, hwif->io_ports[IDE_COMMAND_OFFSET]);
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hwif->OUTB(WIN_PACKETCMD, hwif->io_ports.command_addr);
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return (*pkt_xfer_routine) (drive);
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return (*pkt_xfer_routine) (drive);
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}
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}
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}
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}
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@ -298,48 +298,43 @@ static void ide_complete_pm_request (ide_drive_t *drive, struct request *rq)
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void ide_tf_read(ide_drive_t *drive, ide_task_t *task)
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void ide_tf_read(ide_drive_t *drive, ide_task_t *task)
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{
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{
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ide_hwif_t *hwif = drive->hwif;
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ide_hwif_t *hwif = drive->hwif;
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struct ide_io_ports *io_ports = &hwif->io_ports;
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struct ide_taskfile *tf = &task->tf;
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struct ide_taskfile *tf = &task->tf;
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if (task->tf_flags & IDE_TFLAG_IN_DATA) {
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if (task->tf_flags & IDE_TFLAG_IN_DATA) {
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u16 data = hwif->INW(hwif->io_ports[IDE_DATA_OFFSET]);
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u16 data = hwif->INW(io_ports->data_addr);
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tf->data = data & 0xff;
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tf->data = data & 0xff;
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tf->hob_data = (data >> 8) & 0xff;
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tf->hob_data = (data >> 8) & 0xff;
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}
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}
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/* be sure we're looking at the low order bits */
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/* be sure we're looking at the low order bits */
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hwif->OUTB(drive->ctl & ~0x80, hwif->io_ports[IDE_CONTROL_OFFSET]);
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hwif->OUTB(drive->ctl & ~0x80, io_ports->ctl_addr);
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if (task->tf_flags & IDE_TFLAG_IN_NSECT)
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if (task->tf_flags & IDE_TFLAG_IN_NSECT)
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tf->nsect = hwif->INB(hwif->io_ports[IDE_NSECTOR_OFFSET]);
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tf->nsect = hwif->INB(io_ports->nsect_addr);
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if (task->tf_flags & IDE_TFLAG_IN_LBAL)
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if (task->tf_flags & IDE_TFLAG_IN_LBAL)
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tf->lbal = hwif->INB(hwif->io_ports[IDE_SECTOR_OFFSET]);
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tf->lbal = hwif->INB(io_ports->lbal_addr);
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if (task->tf_flags & IDE_TFLAG_IN_LBAM)
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if (task->tf_flags & IDE_TFLAG_IN_LBAM)
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tf->lbam = hwif->INB(hwif->io_ports[IDE_LCYL_OFFSET]);
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tf->lbam = hwif->INB(io_ports->lbam_addr);
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if (task->tf_flags & IDE_TFLAG_IN_LBAH)
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if (task->tf_flags & IDE_TFLAG_IN_LBAH)
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tf->lbah = hwif->INB(hwif->io_ports[IDE_HCYL_OFFSET]);
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tf->lbah = hwif->INB(io_ports->lbah_addr);
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if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
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if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
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tf->device = hwif->INB(hwif->io_ports[IDE_SELECT_OFFSET]);
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tf->device = hwif->INB(io_ports->device_addr);
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if (task->tf_flags & IDE_TFLAG_LBA48) {
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if (task->tf_flags & IDE_TFLAG_LBA48) {
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hwif->OUTB(drive->ctl | 0x80,
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hwif->OUTB(drive->ctl | 0x80, io_ports->ctl_addr);
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hwif->io_ports[IDE_CONTROL_OFFSET]);
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if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
|
if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
|
||||||
tf->hob_feature =
|
tf->hob_feature = hwif->INB(io_ports->feature_addr);
|
||||||
hwif->INB(hwif->io_ports[IDE_FEATURE_OFFSET]);
|
|
||||||
if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
|
if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
|
||||||
tf->hob_nsect =
|
tf->hob_nsect = hwif->INB(io_ports->nsect_addr);
|
||||||
hwif->INB(hwif->io_ports[IDE_NSECTOR_OFFSET]);
|
|
||||||
if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
|
if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
|
||||||
tf->hob_lbal =
|
tf->hob_lbal = hwif->INB(io_ports->lbal_addr);
|
||||||
hwif->INB(hwif->io_ports[IDE_SECTOR_OFFSET]);
|
|
||||||
if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
|
if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
|
||||||
tf->hob_lbam =
|
tf->hob_lbam = hwif->INB(io_ports->lbam_addr);
|
||||||
hwif->INB(hwif->io_ports[IDE_LCYL_OFFSET]);
|
|
||||||
if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
|
if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
|
||||||
tf->hob_lbah =
|
tf->hob_lbah = hwif->INB(io_ports->lbah_addr);
|
||||||
hwif->INB(hwif->io_ports[IDE_HCYL_OFFSET]);
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -454,7 +449,7 @@ static ide_startstop_t ide_ata_error(ide_drive_t *drive, struct request *rq, u8
|
|||||||
if (err == ABRT_ERR) {
|
if (err == ABRT_ERR) {
|
||||||
if (drive->select.b.lba &&
|
if (drive->select.b.lba &&
|
||||||
/* some newer drives don't support WIN_SPECIFY */
|
/* some newer drives don't support WIN_SPECIFY */
|
||||||
hwif->INB(hwif->io_ports[IDE_COMMAND_OFFSET]) ==
|
hwif->INB(hwif->io_ports.command_addr) ==
|
||||||
WIN_SPECIFY)
|
WIN_SPECIFY)
|
||||||
return ide_stopped;
|
return ide_stopped;
|
||||||
} else if ((err & BAD_CRC) == BAD_CRC) {
|
} else if ((err & BAD_CRC) == BAD_CRC) {
|
||||||
@ -507,8 +502,7 @@ static ide_startstop_t ide_atapi_error(ide_drive_t *drive, struct request *rq, u
|
|||||||
|
|
||||||
if (ide_read_status(drive) & (BUSY_STAT | DRQ_STAT))
|
if (ide_read_status(drive) & (BUSY_STAT | DRQ_STAT))
|
||||||
/* force an abort */
|
/* force an abort */
|
||||||
hwif->OUTB(WIN_IDLEIMMEDIATE,
|
hwif->OUTB(WIN_IDLEIMMEDIATE, hwif->io_ports.command_addr);
|
||||||
hwif->io_ports[IDE_COMMAND_OFFSET]);
|
|
||||||
|
|
||||||
if (rq->errors >= ERROR_MAX) {
|
if (rq->errors >= ERROR_MAX) {
|
||||||
ide_kill_rq(drive, rq);
|
ide_kill_rq(drive, rq);
|
||||||
@ -1421,7 +1415,7 @@ static void unexpected_intr (int irq, ide_hwgroup_t *hwgroup)
|
|||||||
*/
|
*/
|
||||||
do {
|
do {
|
||||||
if (hwif->irq == irq) {
|
if (hwif->irq == irq) {
|
||||||
stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]);
|
stat = hwif->INB(hwif->io_ports.status_addr);
|
||||||
if (!OK_STAT(stat, READY_STAT, BAD_STAT)) {
|
if (!OK_STAT(stat, READY_STAT, BAD_STAT)) {
|
||||||
/* Try to not flood the console with msgs */
|
/* Try to not flood the console with msgs */
|
||||||
static unsigned long last_msgtime, count;
|
static unsigned long last_msgtime, count;
|
||||||
@ -1511,7 +1505,7 @@ irqreturn_t ide_intr (int irq, void *dev_id)
|
|||||||
* Whack the status register, just in case
|
* Whack the status register, just in case
|
||||||
* we have a leftover pending IRQ.
|
* we have a leftover pending IRQ.
|
||||||
*/
|
*/
|
||||||
(void) hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]);
|
(void) hwif->INB(hwif->io_ports.status_addr);
|
||||||
#endif /* CONFIG_BLK_DEV_IDEPCI */
|
#endif /* CONFIG_BLK_DEV_IDEPCI */
|
||||||
}
|
}
|
||||||
spin_unlock_irqrestore(&ide_lock, flags);
|
spin_unlock_irqrestore(&ide_lock, flags);
|
||||||
|
@ -164,7 +164,7 @@ void SELECT_DRIVE (ide_drive_t *drive)
|
|||||||
if (port_ops && port_ops->selectproc)
|
if (port_ops && port_ops->selectproc)
|
||||||
port_ops->selectproc(drive);
|
port_ops->selectproc(drive);
|
||||||
|
|
||||||
hwif->OUTB(drive->select.all, hwif->io_ports[IDE_SELECT_OFFSET]);
|
hwif->OUTB(drive->select.all, hwif->io_ports.device_addr);
|
||||||
}
|
}
|
||||||
|
|
||||||
void SELECT_MASK (ide_drive_t *drive, int mask)
|
void SELECT_MASK (ide_drive_t *drive, int mask)
|
||||||
@ -194,24 +194,22 @@ static void ata_vlb_sync(ide_drive_t *drive, unsigned long port)
|
|||||||
*/
|
*/
|
||||||
static void ata_input_data(ide_drive_t *drive, void *buffer, u32 wcount)
|
static void ata_input_data(ide_drive_t *drive, void *buffer, u32 wcount)
|
||||||
{
|
{
|
||||||
ide_hwif_t *hwif = HWIF(drive);
|
ide_hwif_t *hwif = drive->hwif;
|
||||||
u8 io_32bit = drive->io_32bit;
|
struct ide_io_ports *io_ports = &hwif->io_ports;
|
||||||
|
u8 io_32bit = drive->io_32bit;
|
||||||
|
|
||||||
if (io_32bit) {
|
if (io_32bit) {
|
||||||
if (io_32bit & 2) {
|
if (io_32bit & 2) {
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
|
|
||||||
local_irq_save(flags);
|
local_irq_save(flags);
|
||||||
ata_vlb_sync(drive, hwif->io_ports[IDE_NSECTOR_OFFSET]);
|
ata_vlb_sync(drive, io_ports->nsect_addr);
|
||||||
hwif->INSL(hwif->io_ports[IDE_DATA_OFFSET], buffer,
|
hwif->INSL(io_ports->data_addr, buffer, wcount);
|
||||||
wcount);
|
|
||||||
local_irq_restore(flags);
|
local_irq_restore(flags);
|
||||||
} else
|
} else
|
||||||
hwif->INSL(hwif->io_ports[IDE_DATA_OFFSET], buffer,
|
hwif->INSL(io_ports->data_addr, buffer, wcount);
|
||||||
wcount);
|
|
||||||
} else
|
} else
|
||||||
hwif->INSW(hwif->io_ports[IDE_DATA_OFFSET], buffer,
|
hwif->INSW(io_ports->data_addr, buffer, wcount << 1);
|
||||||
wcount << 1);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -219,24 +217,22 @@ static void ata_input_data(ide_drive_t *drive, void *buffer, u32 wcount)
|
|||||||
*/
|
*/
|
||||||
static void ata_output_data(ide_drive_t *drive, void *buffer, u32 wcount)
|
static void ata_output_data(ide_drive_t *drive, void *buffer, u32 wcount)
|
||||||
{
|
{
|
||||||
ide_hwif_t *hwif = HWIF(drive);
|
ide_hwif_t *hwif = drive->hwif;
|
||||||
u8 io_32bit = drive->io_32bit;
|
struct ide_io_ports *io_ports = &hwif->io_ports;
|
||||||
|
u8 io_32bit = drive->io_32bit;
|
||||||
|
|
||||||
if (io_32bit) {
|
if (io_32bit) {
|
||||||
if (io_32bit & 2) {
|
if (io_32bit & 2) {
|
||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
|
|
||||||
local_irq_save(flags);
|
local_irq_save(flags);
|
||||||
ata_vlb_sync(drive, hwif->io_ports[IDE_NSECTOR_OFFSET]);
|
ata_vlb_sync(drive, io_ports->nsect_addr);
|
||||||
hwif->OUTSL(hwif->io_ports[IDE_DATA_OFFSET], buffer,
|
hwif->OUTSL(io_ports->data_addr, buffer, wcount);
|
||||||
wcount);
|
|
||||||
local_irq_restore(flags);
|
local_irq_restore(flags);
|
||||||
} else
|
} else
|
||||||
hwif->OUTSL(hwif->io_ports[IDE_DATA_OFFSET], buffer,
|
hwif->OUTSL(io_ports->data_addr, buffer, wcount);
|
||||||
wcount);
|
|
||||||
} else
|
} else
|
||||||
hwif->OUTSW(hwif->io_ports[IDE_DATA_OFFSET], buffer,
|
hwif->OUTSW(io_ports->data_addr, buffer, wcount << 1);
|
||||||
wcount << 1);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -255,14 +251,13 @@ static void atapi_input_bytes(ide_drive_t *drive, void *buffer, u32 bytecount)
|
|||||||
#if defined(CONFIG_ATARI) || defined(CONFIG_Q40)
|
#if defined(CONFIG_ATARI) || defined(CONFIG_Q40)
|
||||||
if (MACH_IS_ATARI || MACH_IS_Q40) {
|
if (MACH_IS_ATARI || MACH_IS_Q40) {
|
||||||
/* Atari has a byte-swapped IDE interface */
|
/* Atari has a byte-swapped IDE interface */
|
||||||
insw_swapw(hwif->io_ports[IDE_DATA_OFFSET], buffer,
|
insw_swapw(hwif->io_ports.data_addr, buffer, bytecount / 2);
|
||||||
bytecount / 2);
|
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_ATARI || CONFIG_Q40 */
|
#endif /* CONFIG_ATARI || CONFIG_Q40 */
|
||||||
hwif->ata_input_data(drive, buffer, bytecount / 4);
|
hwif->ata_input_data(drive, buffer, bytecount / 4);
|
||||||
if ((bytecount & 0x03) >= 2)
|
if ((bytecount & 0x03) >= 2)
|
||||||
hwif->INSW(hwif->io_ports[IDE_DATA_OFFSET],
|
hwif->INSW(hwif->io_ports.data_addr,
|
||||||
(u8 *)buffer + (bytecount & ~0x03), 1);
|
(u8 *)buffer + (bytecount & ~0x03), 1);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -274,14 +269,13 @@ static void atapi_output_bytes(ide_drive_t *drive, void *buffer, u32 bytecount)
|
|||||||
#if defined(CONFIG_ATARI) || defined(CONFIG_Q40)
|
#if defined(CONFIG_ATARI) || defined(CONFIG_Q40)
|
||||||
if (MACH_IS_ATARI || MACH_IS_Q40) {
|
if (MACH_IS_ATARI || MACH_IS_Q40) {
|
||||||
/* Atari has a byte-swapped IDE interface */
|
/* Atari has a byte-swapped IDE interface */
|
||||||
outsw_swapw(hwif->io_ports[IDE_DATA_OFFSET], buffer,
|
outsw_swapw(hwif->io_ports.data_addr, buffer, bytecount / 2);
|
||||||
bytecount / 2);
|
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_ATARI || CONFIG_Q40 */
|
#endif /* CONFIG_ATARI || CONFIG_Q40 */
|
||||||
hwif->ata_output_data(drive, buffer, bytecount / 4);
|
hwif->ata_output_data(drive, buffer, bytecount / 4);
|
||||||
if ((bytecount & 0x03) >= 2)
|
if ((bytecount & 0x03) >= 2)
|
||||||
hwif->OUTSW(hwif->io_ports[IDE_DATA_OFFSET],
|
hwif->OUTSW(hwif->io_ports.data_addr,
|
||||||
(u8 *)buffer + (bytecount & ~0x03), 1);
|
(u8 *)buffer + (bytecount & ~0x03), 1);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -445,7 +439,7 @@ int drive_is_ready (ide_drive_t *drive)
|
|||||||
* an interrupt with another pci card/device. We make no assumptions
|
* an interrupt with another pci card/device. We make no assumptions
|
||||||
* about possible isa-pnp and pci-pnp issues yet.
|
* about possible isa-pnp and pci-pnp issues yet.
|
||||||
*/
|
*/
|
||||||
if (hwif->io_ports[IDE_CONTROL_OFFSET])
|
if (hwif->io_ports.ctl_addr)
|
||||||
stat = ide_read_altstatus(drive);
|
stat = ide_read_altstatus(drive);
|
||||||
else
|
else
|
||||||
/* Note: this may clear a pending IRQ!! */
|
/* Note: this may clear a pending IRQ!! */
|
||||||
@ -647,7 +641,7 @@ int ide_driveid_update(ide_drive_t *drive)
|
|||||||
SELECT_MASK(drive, 1);
|
SELECT_MASK(drive, 1);
|
||||||
ide_set_irq(drive, 1);
|
ide_set_irq(drive, 1);
|
||||||
msleep(50);
|
msleep(50);
|
||||||
hwif->OUTB(WIN_IDENTIFY, hwif->io_ports[IDE_COMMAND_OFFSET]);
|
hwif->OUTB(WIN_IDENTIFY, hwif->io_ports.command_addr);
|
||||||
timeout = jiffies + WAIT_WORSTCASE;
|
timeout = jiffies + WAIT_WORSTCASE;
|
||||||
do {
|
do {
|
||||||
if (time_after(jiffies, timeout)) {
|
if (time_after(jiffies, timeout)) {
|
||||||
@ -696,6 +690,7 @@ int ide_driveid_update(ide_drive_t *drive)
|
|||||||
int ide_config_drive_speed(ide_drive_t *drive, u8 speed)
|
int ide_config_drive_speed(ide_drive_t *drive, u8 speed)
|
||||||
{
|
{
|
||||||
ide_hwif_t *hwif = drive->hwif;
|
ide_hwif_t *hwif = drive->hwif;
|
||||||
|
struct ide_io_ports *io_ports = &hwif->io_ports;
|
||||||
int error = 0;
|
int error = 0;
|
||||||
u8 stat;
|
u8 stat;
|
||||||
|
|
||||||
@ -734,10 +729,9 @@ int ide_config_drive_speed(ide_drive_t *drive, u8 speed)
|
|||||||
SELECT_MASK(drive, 0);
|
SELECT_MASK(drive, 0);
|
||||||
udelay(1);
|
udelay(1);
|
||||||
ide_set_irq(drive, 0);
|
ide_set_irq(drive, 0);
|
||||||
hwif->OUTB(speed, hwif->io_ports[IDE_NSECTOR_OFFSET]);
|
hwif->OUTB(speed, io_ports->nsect_addr);
|
||||||
hwif->OUTB(SETFEATURES_XFER, hwif->io_ports[IDE_FEATURE_OFFSET]);
|
hwif->OUTB(SETFEATURES_XFER, io_ports->feature_addr);
|
||||||
hwif->OUTBSYNC(drive, WIN_SETFEATURES,
|
hwif->OUTBSYNC(drive, WIN_SETFEATURES, io_ports->command_addr);
|
||||||
hwif->io_ports[IDE_COMMAND_OFFSET]);
|
|
||||||
if (drive->quirk_list == 2)
|
if (drive->quirk_list == 2)
|
||||||
ide_set_irq(drive, 1);
|
ide_set_irq(drive, 1);
|
||||||
|
|
||||||
@ -845,7 +839,7 @@ void ide_execute_command(ide_drive_t *drive, u8 cmd, ide_handler_t *handler,
|
|||||||
|
|
||||||
spin_lock_irqsave(&ide_lock, flags);
|
spin_lock_irqsave(&ide_lock, flags);
|
||||||
__ide_set_handler(drive, handler, timeout, expiry);
|
__ide_set_handler(drive, handler, timeout, expiry);
|
||||||
hwif->OUTBSYNC(drive, cmd, hwif->io_ports[IDE_COMMAND_OFFSET]);
|
hwif->OUTBSYNC(drive, cmd, hwif->io_ports.command_addr);
|
||||||
/*
|
/*
|
||||||
* Drive takes 400nS to respond, we must avoid the IRQ being
|
* Drive takes 400nS to respond, we must avoid the IRQ being
|
||||||
* serviced before that.
|
* serviced before that.
|
||||||
@ -1029,6 +1023,7 @@ static ide_startstop_t do_reset1 (ide_drive_t *drive, int do_not_try_atapi)
|
|||||||
unsigned long flags;
|
unsigned long flags;
|
||||||
ide_hwif_t *hwif;
|
ide_hwif_t *hwif;
|
||||||
ide_hwgroup_t *hwgroup;
|
ide_hwgroup_t *hwgroup;
|
||||||
|
struct ide_io_ports *io_ports;
|
||||||
const struct ide_port_ops *port_ops;
|
const struct ide_port_ops *port_ops;
|
||||||
u8 ctl;
|
u8 ctl;
|
||||||
|
|
||||||
@ -1036,6 +1031,8 @@ static ide_startstop_t do_reset1 (ide_drive_t *drive, int do_not_try_atapi)
|
|||||||
hwif = HWIF(drive);
|
hwif = HWIF(drive);
|
||||||
hwgroup = HWGROUP(drive);
|
hwgroup = HWGROUP(drive);
|
||||||
|
|
||||||
|
io_ports = &hwif->io_ports;
|
||||||
|
|
||||||
/* We must not reset with running handlers */
|
/* We must not reset with running handlers */
|
||||||
BUG_ON(hwgroup->handler != NULL);
|
BUG_ON(hwgroup->handler != NULL);
|
||||||
|
|
||||||
@ -1045,8 +1042,7 @@ static ide_startstop_t do_reset1 (ide_drive_t *drive, int do_not_try_atapi)
|
|||||||
pre_reset(drive);
|
pre_reset(drive);
|
||||||
SELECT_DRIVE(drive);
|
SELECT_DRIVE(drive);
|
||||||
udelay (20);
|
udelay (20);
|
||||||
hwif->OUTBSYNC(drive, WIN_SRST,
|
hwif->OUTBSYNC(drive, WIN_SRST, io_ports->command_addr);
|
||||||
hwif->io_ports[IDE_COMMAND_OFFSET]);
|
|
||||||
ndelay(400);
|
ndelay(400);
|
||||||
hwgroup->poll_timeout = jiffies + WAIT_WORSTCASE;
|
hwgroup->poll_timeout = jiffies + WAIT_WORSTCASE;
|
||||||
hwgroup->polling = 1;
|
hwgroup->polling = 1;
|
||||||
@ -1062,7 +1058,7 @@ static ide_startstop_t do_reset1 (ide_drive_t *drive, int do_not_try_atapi)
|
|||||||
for (unit = 0; unit < MAX_DRIVES; ++unit)
|
for (unit = 0; unit < MAX_DRIVES; ++unit)
|
||||||
pre_reset(&hwif->drives[unit]);
|
pre_reset(&hwif->drives[unit]);
|
||||||
|
|
||||||
if (hwif->io_ports[IDE_CONTROL_OFFSET] == 0) {
|
if (io_ports->ctl_addr == 0) {
|
||||||
spin_unlock_irqrestore(&ide_lock, flags);
|
spin_unlock_irqrestore(&ide_lock, flags);
|
||||||
return ide_stopped;
|
return ide_stopped;
|
||||||
}
|
}
|
||||||
@ -1077,14 +1073,14 @@ static ide_startstop_t do_reset1 (ide_drive_t *drive, int do_not_try_atapi)
|
|||||||
* recover from reset very quickly, saving us the first 50ms wait time.
|
* recover from reset very quickly, saving us the first 50ms wait time.
|
||||||
*/
|
*/
|
||||||
/* set SRST and nIEN */
|
/* set SRST and nIEN */
|
||||||
hwif->OUTBSYNC(drive, drive->ctl|6, hwif->io_ports[IDE_CONTROL_OFFSET]);
|
hwif->OUTBSYNC(drive, drive->ctl|6, io_ports->ctl_addr);
|
||||||
/* more than enough time */
|
/* more than enough time */
|
||||||
udelay(10);
|
udelay(10);
|
||||||
if (drive->quirk_list == 2)
|
if (drive->quirk_list == 2)
|
||||||
ctl = drive->ctl; /* clear SRST and nIEN */
|
ctl = drive->ctl; /* clear SRST and nIEN */
|
||||||
else
|
else
|
||||||
ctl = drive->ctl | 2; /* clear SRST, leave nIEN */
|
ctl = drive->ctl | 2; /* clear SRST, leave nIEN */
|
||||||
hwif->OUTBSYNC(drive, ctl, hwif->io_ports[IDE_CONTROL_OFFSET]);
|
hwif->OUTBSYNC(drive, ctl, io_ports->ctl_addr);
|
||||||
/* more than enough time */
|
/* more than enough time */
|
||||||
udelay(10);
|
udelay(10);
|
||||||
hwgroup->poll_timeout = jiffies + WAIT_WORSTCASE;
|
hwgroup->poll_timeout = jiffies + WAIT_WORSTCASE;
|
||||||
@ -1129,7 +1125,7 @@ int ide_wait_not_busy(ide_hwif_t *hwif, unsigned long timeout)
|
|||||||
* about locking issues (2.5 work ?).
|
* about locking issues (2.5 work ?).
|
||||||
*/
|
*/
|
||||||
mdelay(1);
|
mdelay(1);
|
||||||
stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]);
|
stat = hwif->INB(hwif->io_ports.status_addr);
|
||||||
if ((stat & BUSY_STAT) == 0)
|
if ((stat & BUSY_STAT) == 0)
|
||||||
return 0;
|
return 0;
|
||||||
/*
|
/*
|
||||||
|
@ -264,6 +264,7 @@ err_misc:
|
|||||||
static int actual_try_to_identify (ide_drive_t *drive, u8 cmd)
|
static int actual_try_to_identify (ide_drive_t *drive, u8 cmd)
|
||||||
{
|
{
|
||||||
ide_hwif_t *hwif = HWIF(drive);
|
ide_hwif_t *hwif = HWIF(drive);
|
||||||
|
struct ide_io_ports *io_ports = &hwif->io_ports;
|
||||||
int use_altstatus = 0, rc;
|
int use_altstatus = 0, rc;
|
||||||
unsigned long timeout;
|
unsigned long timeout;
|
||||||
u8 s = 0, a = 0;
|
u8 s = 0, a = 0;
|
||||||
@ -271,7 +272,7 @@ static int actual_try_to_identify (ide_drive_t *drive, u8 cmd)
|
|||||||
/* take a deep breath */
|
/* take a deep breath */
|
||||||
msleep(50);
|
msleep(50);
|
||||||
|
|
||||||
if (hwif->io_ports[IDE_CONTROL_OFFSET]) {
|
if (io_ports->ctl_addr) {
|
||||||
a = ide_read_altstatus(drive);
|
a = ide_read_altstatus(drive);
|
||||||
s = ide_read_status(drive);
|
s = ide_read_status(drive);
|
||||||
if ((a ^ s) & ~INDEX_STAT)
|
if ((a ^ s) & ~INDEX_STAT)
|
||||||
@ -289,10 +290,10 @@ static int actual_try_to_identify (ide_drive_t *drive, u8 cmd)
|
|||||||
*/
|
*/
|
||||||
if ((cmd == WIN_PIDENTIFY))
|
if ((cmd == WIN_PIDENTIFY))
|
||||||
/* disable dma & overlap */
|
/* disable dma & overlap */
|
||||||
hwif->OUTB(0, hwif->io_ports[IDE_FEATURE_OFFSET]);
|
hwif->OUTB(0, io_ports->feature_addr);
|
||||||
|
|
||||||
/* ask drive for ID */
|
/* ask drive for ID */
|
||||||
hwif->OUTB(cmd, hwif->io_ports[IDE_COMMAND_OFFSET]);
|
hwif->OUTB(cmd, io_ports->command_addr);
|
||||||
|
|
||||||
timeout = ((cmd == WIN_IDENTIFY) ? WAIT_WORSTCASE : WAIT_PIDENTIFY) / 2;
|
timeout = ((cmd == WIN_IDENTIFY) ? WAIT_WORSTCASE : WAIT_PIDENTIFY) / 2;
|
||||||
timeout += jiffies;
|
timeout += jiffies;
|
||||||
@ -353,7 +354,7 @@ static int try_to_identify (ide_drive_t *drive, u8 cmd)
|
|||||||
* interrupts during the identify-phase that
|
* interrupts during the identify-phase that
|
||||||
* the irq handler isn't expecting.
|
* the irq handler isn't expecting.
|
||||||
*/
|
*/
|
||||||
if (hwif->io_ports[IDE_CONTROL_OFFSET]) {
|
if (hwif->io_ports.ctl_addr) {
|
||||||
if (!hwif->irq) {
|
if (!hwif->irq) {
|
||||||
autoprobe = 1;
|
autoprobe = 1;
|
||||||
cookie = probe_irq_on();
|
cookie = probe_irq_on();
|
||||||
@ -393,7 +394,7 @@ static int ide_busy_sleep(ide_hwif_t *hwif)
|
|||||||
|
|
||||||
do {
|
do {
|
||||||
msleep(50);
|
msleep(50);
|
||||||
stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]);
|
stat = hwif->INB(hwif->io_ports.status_addr);
|
||||||
if ((stat & BUSY_STAT) == 0)
|
if ((stat & BUSY_STAT) == 0)
|
||||||
return 0;
|
return 0;
|
||||||
} while (time_before(jiffies, timeout));
|
} while (time_before(jiffies, timeout));
|
||||||
@ -425,6 +426,7 @@ static int ide_busy_sleep(ide_hwif_t *hwif)
|
|||||||
static int do_probe (ide_drive_t *drive, u8 cmd)
|
static int do_probe (ide_drive_t *drive, u8 cmd)
|
||||||
{
|
{
|
||||||
ide_hwif_t *hwif = HWIF(drive);
|
ide_hwif_t *hwif = HWIF(drive);
|
||||||
|
struct ide_io_ports *io_ports = &hwif->io_ports;
|
||||||
int rc;
|
int rc;
|
||||||
u8 stat;
|
u8 stat;
|
||||||
|
|
||||||
@ -445,7 +447,7 @@ static int do_probe (ide_drive_t *drive, u8 cmd)
|
|||||||
msleep(50);
|
msleep(50);
|
||||||
SELECT_DRIVE(drive);
|
SELECT_DRIVE(drive);
|
||||||
msleep(50);
|
msleep(50);
|
||||||
if (hwif->INB(hwif->io_ports[IDE_SELECT_OFFSET]) != drive->select.all &&
|
if (hwif->INB(io_ports->device_addr) != drive->select.all &&
|
||||||
!drive->present) {
|
!drive->present) {
|
||||||
if (drive->select.b.unit != 0) {
|
if (drive->select.b.unit != 0) {
|
||||||
/* exit with drive0 selected */
|
/* exit with drive0 selected */
|
||||||
@ -476,11 +478,9 @@ static int do_probe (ide_drive_t *drive, u8 cmd)
|
|||||||
printk(KERN_ERR "%s: no response (status = 0x%02x), "
|
printk(KERN_ERR "%s: no response (status = 0x%02x), "
|
||||||
"resetting drive\n", drive->name, stat);
|
"resetting drive\n", drive->name, stat);
|
||||||
msleep(50);
|
msleep(50);
|
||||||
hwif->OUTB(drive->select.all,
|
hwif->OUTB(drive->select.all, io_ports->device_addr);
|
||||||
hwif->io_ports[IDE_SELECT_OFFSET]);
|
|
||||||
msleep(50);
|
msleep(50);
|
||||||
hwif->OUTB(WIN_SRST,
|
hwif->OUTB(WIN_SRST, io_ports->command_addr);
|
||||||
hwif->io_ports[IDE_COMMAND_OFFSET]);
|
|
||||||
(void)ide_busy_sleep(hwif);
|
(void)ide_busy_sleep(hwif);
|
||||||
rc = try_to_identify(drive, cmd);
|
rc = try_to_identify(drive, cmd);
|
||||||
}
|
}
|
||||||
@ -516,7 +516,7 @@ static void enable_nest (ide_drive_t *drive)
|
|||||||
printk("%s: enabling %s -- ", hwif->name, drive->id->model);
|
printk("%s: enabling %s -- ", hwif->name, drive->id->model);
|
||||||
SELECT_DRIVE(drive);
|
SELECT_DRIVE(drive);
|
||||||
msleep(50);
|
msleep(50);
|
||||||
hwif->OUTB(EXABYTE_ENABLE_NEST, hwif->io_ports[IDE_COMMAND_OFFSET]);
|
hwif->OUTB(EXABYTE_ENABLE_NEST, hwif->io_ports.command_addr);
|
||||||
|
|
||||||
if (ide_busy_sleep(hwif)) {
|
if (ide_busy_sleep(hwif)) {
|
||||||
printk(KERN_CONT "failed (timeout)\n");
|
printk(KERN_CONT "failed (timeout)\n");
|
||||||
@ -982,6 +982,7 @@ static void ide_port_setup_devices(ide_hwif_t *hwif)
|
|||||||
*/
|
*/
|
||||||
static int init_irq (ide_hwif_t *hwif)
|
static int init_irq (ide_hwif_t *hwif)
|
||||||
{
|
{
|
||||||
|
struct ide_io_ports *io_ports = &hwif->io_ports;
|
||||||
unsigned int index;
|
unsigned int index;
|
||||||
ide_hwgroup_t *hwgroup;
|
ide_hwgroup_t *hwgroup;
|
||||||
ide_hwif_t *match = NULL;
|
ide_hwif_t *match = NULL;
|
||||||
@ -1065,9 +1066,9 @@ static int init_irq (ide_hwif_t *hwif)
|
|||||||
if (IDE_CHIPSET_IS_PCI(hwif->chipset))
|
if (IDE_CHIPSET_IS_PCI(hwif->chipset))
|
||||||
sa = IRQF_SHARED;
|
sa = IRQF_SHARED;
|
||||||
|
|
||||||
if (hwif->io_ports[IDE_CONTROL_OFFSET])
|
if (io_ports->ctl_addr)
|
||||||
/* clear nIEN */
|
/* clear nIEN */
|
||||||
hwif->OUTB(0x08, hwif->io_ports[IDE_CONTROL_OFFSET]);
|
hwif->OUTB(0x08, io_ports->ctl_addr);
|
||||||
|
|
||||||
if (request_irq(hwif->irq,&ide_intr,sa,hwif->name,hwgroup))
|
if (request_irq(hwif->irq,&ide_intr,sa,hwif->name,hwgroup))
|
||||||
goto out_unlink;
|
goto out_unlink;
|
||||||
@ -1083,12 +1084,11 @@ static int init_irq (ide_hwif_t *hwif)
|
|||||||
|
|
||||||
#if !defined(__mc68000__)
|
#if !defined(__mc68000__)
|
||||||
printk("%s at 0x%03lx-0x%03lx,0x%03lx on irq %d", hwif->name,
|
printk("%s at 0x%03lx-0x%03lx,0x%03lx on irq %d", hwif->name,
|
||||||
hwif->io_ports[IDE_DATA_OFFSET],
|
io_ports->data_addr, io_ports->status_addr,
|
||||||
hwif->io_ports[IDE_DATA_OFFSET]+7,
|
io_ports->ctl_addr, hwif->irq);
|
||||||
hwif->io_ports[IDE_CONTROL_OFFSET], hwif->irq);
|
|
||||||
#else
|
#else
|
||||||
printk("%s at 0x%08lx on irq %d", hwif->name,
|
printk("%s at 0x%08lx on irq %d", hwif->name,
|
||||||
hwif->io_ports[IDE_DATA_OFFSET], hwif->irq);
|
io_ports->data_addr, hwif->irq);
|
||||||
#endif /* __mc68000__ */
|
#endif /* __mc68000__ */
|
||||||
if (match)
|
if (match)
|
||||||
printk(" (%sed with %s)",
|
printk(" (%sed with %s)",
|
||||||
@ -1230,8 +1230,8 @@ static int hwif_init(ide_hwif_t *hwif)
|
|||||||
int old_irq;
|
int old_irq;
|
||||||
|
|
||||||
if (!hwif->irq) {
|
if (!hwif->irq) {
|
||||||
if (!(hwif->irq = ide_default_irq(hwif->io_ports[IDE_DATA_OFFSET])))
|
hwif->irq = ide_default_irq(hwif->io_ports.data_addr);
|
||||||
{
|
if (!hwif->irq) {
|
||||||
printk("%s: DISABLED, NO IRQ\n", hwif->name);
|
printk("%s: DISABLED, NO IRQ\n", hwif->name);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
@ -1260,7 +1260,8 @@ static int hwif_init(ide_hwif_t *hwif)
|
|||||||
* It failed to initialise. Find the default IRQ for
|
* It failed to initialise. Find the default IRQ for
|
||||||
* this port and try that.
|
* this port and try that.
|
||||||
*/
|
*/
|
||||||
if (!(hwif->irq = ide_default_irq(hwif->io_ports[IDE_DATA_OFFSET]))) {
|
hwif->irq = ide_default_irq(hwif->io_ports.data_addr);
|
||||||
|
if (!hwif->irq) {
|
||||||
printk("%s: Disabled unable to get IRQ %d.\n",
|
printk("%s: Disabled unable to get IRQ %d.\n",
|
||||||
hwif->name, old_irq);
|
hwif->name, old_irq);
|
||||||
goto out;
|
goto out;
|
||||||
|
@ -849,10 +849,10 @@ static ide_startstop_t idetape_pc_intr(ide_drive_t *drive)
|
|||||||
return ide_do_reset(drive);
|
return ide_do_reset(drive);
|
||||||
}
|
}
|
||||||
/* Get the number of bytes to transfer on this interrupt. */
|
/* Get the number of bytes to transfer on this interrupt. */
|
||||||
bcount = (hwif->INB(hwif->io_ports[IDE_BCOUNTH_OFFSET]) << 8) |
|
bcount = (hwif->INB(hwif->io_ports.lbah_addr) << 8) |
|
||||||
hwif->INB(hwif->io_ports[IDE_BCOUNTL_OFFSET]);
|
hwif->INB(hwif->io_ports.lbam_addr);
|
||||||
|
|
||||||
ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]);
|
ireason = hwif->INB(hwif->io_ports.nsect_addr);
|
||||||
|
|
||||||
if (ireason & CD) {
|
if (ireason & CD) {
|
||||||
printk(KERN_ERR "ide-tape: CoD != 0 in %s\n", __func__);
|
printk(KERN_ERR "ide-tape: CoD != 0 in %s\n", __func__);
|
||||||
@ -956,12 +956,12 @@ static ide_startstop_t idetape_transfer_pc(ide_drive_t *drive)
|
|||||||
"yet DRQ isn't asserted\n");
|
"yet DRQ isn't asserted\n");
|
||||||
return startstop;
|
return startstop;
|
||||||
}
|
}
|
||||||
ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]);
|
ireason = hwif->INB(hwif->io_ports.nsect_addr);
|
||||||
while (retries-- && ((ireason & CD) == 0 || (ireason & IO))) {
|
while (retries-- && ((ireason & CD) == 0 || (ireason & IO))) {
|
||||||
printk(KERN_ERR "ide-tape: (IO,CoD != (0,1) while issuing "
|
printk(KERN_ERR "ide-tape: (IO,CoD != (0,1) while issuing "
|
||||||
"a packet command, retrying\n");
|
"a packet command, retrying\n");
|
||||||
udelay(100);
|
udelay(100);
|
||||||
ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]);
|
ireason = hwif->INB(hwif->io_ports.nsect_addr);
|
||||||
if (retries == 0) {
|
if (retries == 0) {
|
||||||
printk(KERN_ERR "ide-tape: (IO,CoD != (0,1) while "
|
printk(KERN_ERR "ide-tape: (IO,CoD != (0,1) while "
|
||||||
"issuing a packet command, ignoring\n");
|
"issuing a packet command, ignoring\n");
|
||||||
@ -1058,7 +1058,7 @@ static ide_startstop_t idetape_issue_pc(ide_drive_t *drive,
|
|||||||
IDETAPE_WAIT_CMD, NULL);
|
IDETAPE_WAIT_CMD, NULL);
|
||||||
return ide_started;
|
return ide_started;
|
||||||
} else {
|
} else {
|
||||||
hwif->OUTB(WIN_PACKETCMD, hwif->io_ports[IDE_COMMAND_OFFSET]);
|
hwif->OUTB(WIN_PACKETCMD, hwif->io_ports.command_addr);
|
||||||
return idetape_transfer_pc(drive);
|
return idetape_transfer_pc(drive);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -36,6 +36,7 @@
|
|||||||
void ide_tf_load(ide_drive_t *drive, ide_task_t *task)
|
void ide_tf_load(ide_drive_t *drive, ide_task_t *task)
|
||||||
{
|
{
|
||||||
ide_hwif_t *hwif = drive->hwif;
|
ide_hwif_t *hwif = drive->hwif;
|
||||||
|
struct ide_io_ports *io_ports = &hwif->io_ports;
|
||||||
struct ide_taskfile *tf = &task->tf;
|
struct ide_taskfile *tf = &task->tf;
|
||||||
u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
|
u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
|
||||||
|
|
||||||
@ -59,34 +60,33 @@ void ide_tf_load(ide_drive_t *drive, ide_task_t *task)
|
|||||||
SELECT_MASK(drive, 0);
|
SELECT_MASK(drive, 0);
|
||||||
|
|
||||||
if (task->tf_flags & IDE_TFLAG_OUT_DATA)
|
if (task->tf_flags & IDE_TFLAG_OUT_DATA)
|
||||||
hwif->OUTW((tf->hob_data << 8) | tf->data,
|
hwif->OUTW((tf->hob_data << 8) | tf->data, io_ports->data_addr);
|
||||||
hwif->io_ports[IDE_DATA_OFFSET]);
|
|
||||||
|
|
||||||
if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
|
if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
|
||||||
hwif->OUTB(tf->hob_feature, hwif->io_ports[IDE_FEATURE_OFFSET]);
|
hwif->OUTB(tf->hob_feature, io_ports->feature_addr);
|
||||||
if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
|
if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
|
||||||
hwif->OUTB(tf->hob_nsect, hwif->io_ports[IDE_NSECTOR_OFFSET]);
|
hwif->OUTB(tf->hob_nsect, io_ports->nsect_addr);
|
||||||
if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
|
if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
|
||||||
hwif->OUTB(tf->hob_lbal, hwif->io_ports[IDE_SECTOR_OFFSET]);
|
hwif->OUTB(tf->hob_lbal, io_ports->lbal_addr);
|
||||||
if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
|
if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
|
||||||
hwif->OUTB(tf->hob_lbam, hwif->io_ports[IDE_LCYL_OFFSET]);
|
hwif->OUTB(tf->hob_lbam, io_ports->lbam_addr);
|
||||||
if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
|
if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
|
||||||
hwif->OUTB(tf->hob_lbah, hwif->io_ports[IDE_HCYL_OFFSET]);
|
hwif->OUTB(tf->hob_lbah, io_ports->lbah_addr);
|
||||||
|
|
||||||
if (task->tf_flags & IDE_TFLAG_OUT_FEATURE)
|
if (task->tf_flags & IDE_TFLAG_OUT_FEATURE)
|
||||||
hwif->OUTB(tf->feature, hwif->io_ports[IDE_FEATURE_OFFSET]);
|
hwif->OUTB(tf->feature, io_ports->feature_addr);
|
||||||
if (task->tf_flags & IDE_TFLAG_OUT_NSECT)
|
if (task->tf_flags & IDE_TFLAG_OUT_NSECT)
|
||||||
hwif->OUTB(tf->nsect, hwif->io_ports[IDE_NSECTOR_OFFSET]);
|
hwif->OUTB(tf->nsect, io_ports->nsect_addr);
|
||||||
if (task->tf_flags & IDE_TFLAG_OUT_LBAL)
|
if (task->tf_flags & IDE_TFLAG_OUT_LBAL)
|
||||||
hwif->OUTB(tf->lbal, hwif->io_ports[IDE_SECTOR_OFFSET]);
|
hwif->OUTB(tf->lbal, io_ports->lbal_addr);
|
||||||
if (task->tf_flags & IDE_TFLAG_OUT_LBAM)
|
if (task->tf_flags & IDE_TFLAG_OUT_LBAM)
|
||||||
hwif->OUTB(tf->lbam, hwif->io_ports[IDE_LCYL_OFFSET]);
|
hwif->OUTB(tf->lbam, io_ports->lbam_addr);
|
||||||
if (task->tf_flags & IDE_TFLAG_OUT_LBAH)
|
if (task->tf_flags & IDE_TFLAG_OUT_LBAH)
|
||||||
hwif->OUTB(tf->lbah, hwif->io_ports[IDE_HCYL_OFFSET]);
|
hwif->OUTB(tf->lbah, io_ports->lbah_addr);
|
||||||
|
|
||||||
if (task->tf_flags & IDE_TFLAG_OUT_DEVICE)
|
if (task->tf_flags & IDE_TFLAG_OUT_DEVICE)
|
||||||
hwif->OUTB((tf->device & HIHI) | drive->select.all,
|
hwif->OUTB((tf->device & HIHI) | drive->select.all,
|
||||||
hwif->io_ports[IDE_SELECT_OFFSET]);
|
io_ports->device_addr);
|
||||||
}
|
}
|
||||||
|
|
||||||
int taskfile_lib_get_identify (ide_drive_t *drive, u8 *buf)
|
int taskfile_lib_get_identify (ide_drive_t *drive, u8 *buf)
|
||||||
@ -155,8 +155,7 @@ ide_startstop_t do_rw_taskfile (ide_drive_t *drive, ide_task_t *task)
|
|||||||
switch (task->data_phase) {
|
switch (task->data_phase) {
|
||||||
case TASKFILE_MULTI_OUT:
|
case TASKFILE_MULTI_OUT:
|
||||||
case TASKFILE_OUT:
|
case TASKFILE_OUT:
|
||||||
hwif->OUTBSYNC(drive, tf->command,
|
hwif->OUTBSYNC(drive, tf->command, hwif->io_ports.command_addr);
|
||||||
hwif->io_ports[IDE_COMMAND_OFFSET]);
|
|
||||||
ndelay(400); /* FIXME */
|
ndelay(400); /* FIXME */
|
||||||
return pre_task_out_intr(drive, task->rq);
|
return pre_task_out_intr(drive, task->rq);
|
||||||
case TASKFILE_MULTI_IN:
|
case TASKFILE_MULTI_IN:
|
||||||
|
@ -368,7 +368,7 @@ EXPORT_SYMBOL(ide_unregister);
|
|||||||
|
|
||||||
void ide_init_port_hw(ide_hwif_t *hwif, hw_regs_t *hw)
|
void ide_init_port_hw(ide_hwif_t *hwif, hw_regs_t *hw)
|
||||||
{
|
{
|
||||||
memcpy(hwif->io_ports, hw->io_ports, sizeof(hwif->io_ports));
|
memcpy(&hwif->io_ports, &hw->io_ports, sizeof(hwif->io_ports));
|
||||||
hwif->irq = hw->irq;
|
hwif->irq = hw->irq;
|
||||||
hwif->chipset = hw->chipset;
|
hwif->chipset = hw->chipset;
|
||||||
hwif->gendev.parent = hw->dev;
|
hwif->gendev.parent = hw->dev;
|
||||||
|
@ -102,7 +102,7 @@ static int buddha_ack_intr(ide_hwif_t *hwif)
|
|||||||
{
|
{
|
||||||
unsigned char ch;
|
unsigned char ch;
|
||||||
|
|
||||||
ch = z_readb(hwif->io_ports[IDE_IRQ_OFFSET]);
|
ch = z_readb(hwif->io_ports.irq_addr);
|
||||||
if (!(ch & 0x80))
|
if (!(ch & 0x80))
|
||||||
return 0;
|
return 0;
|
||||||
return 1;
|
return 1;
|
||||||
@ -112,9 +112,9 @@ static int xsurf_ack_intr(ide_hwif_t *hwif)
|
|||||||
{
|
{
|
||||||
unsigned char ch;
|
unsigned char ch;
|
||||||
|
|
||||||
ch = z_readb(hwif->io_ports[IDE_IRQ_OFFSET]);
|
ch = z_readb(hwif->io_ports.irq_addr);
|
||||||
/* X-Surf needs a 0 written to IRQ register to ensure ISA bit A11 stays at 0 */
|
/* X-Surf needs a 0 written to IRQ register to ensure ISA bit A11 stays at 0 */
|
||||||
z_writeb(0, hwif->io_ports[IDE_IRQ_OFFSET]);
|
z_writeb(0, hwif->io_ports.irq_addr);
|
||||||
if (!(ch & 0x80))
|
if (!(ch & 0x80))
|
||||||
return 0;
|
return 0;
|
||||||
return 1;
|
return 1;
|
||||||
@ -128,13 +128,13 @@ static void __init buddha_setup_ports(hw_regs_t *hw, unsigned long base,
|
|||||||
|
|
||||||
memset(hw, 0, sizeof(*hw));
|
memset(hw, 0, sizeof(*hw));
|
||||||
|
|
||||||
hw->io_ports[IDE_DATA_OFFSET] = base;
|
hw->io_ports.data_addr = base;
|
||||||
|
|
||||||
for (i = 1; i < 8; i++)
|
for (i = 1; i < 8; i++)
|
||||||
hw->io_ports[i] = base + 2 + i * 4;
|
hw->io_ports_array[i] = base + 2 + i * 4;
|
||||||
|
|
||||||
hw->io_ports[IDE_CONTROL_OFFSET] = ctl;
|
hw->io_ports.ctl_addr = ctl;
|
||||||
hw->io_ports[IDE_IRQ_OFFSET] = irq_port;
|
hw->io_ports.irq_addr = irq_port;
|
||||||
|
|
||||||
hw->irq = IRQ_AMIGA_PORTS;
|
hw->irq = IRQ_AMIGA_PORTS;
|
||||||
hw->ack_intr = ack_intr;
|
hw->ack_intr = ack_intr;
|
||||||
|
@ -50,12 +50,12 @@ static void __init falconide_setup_ports(hw_regs_t *hw)
|
|||||||
|
|
||||||
memset(hw, 0, sizeof(*hw));
|
memset(hw, 0, sizeof(*hw));
|
||||||
|
|
||||||
hw->io_ports[IDE_DATA_OFFSET] = ATA_HD_BASE;
|
hw->io_ports.data_addr = ATA_HD_BASE;
|
||||||
|
|
||||||
for (i = 1; i < 8; i++)
|
for (i = 1; i < 8; i++)
|
||||||
hw->io_ports[i] = ATA_HD_BASE + 1 + i * 4;
|
hw->io_ports_array[i] = ATA_HD_BASE + 1 + i * 4;
|
||||||
|
|
||||||
hw->io_ports[IDE_CONTROL_OFFSET] = ATA_HD_BASE + ATA_HD_CONTROL;
|
hw->io_ports.ctl_addr = ATA_HD_BASE + ATA_HD_CONTROL;
|
||||||
|
|
||||||
hw->irq = IRQ_MFP_IDE;
|
hw->irq = IRQ_MFP_IDE;
|
||||||
hw->ack_intr = NULL;
|
hw->ack_intr = NULL;
|
||||||
|
@ -76,7 +76,7 @@ static int gayle_ack_intr_a4000(ide_hwif_t *hwif)
|
|||||||
{
|
{
|
||||||
unsigned char ch;
|
unsigned char ch;
|
||||||
|
|
||||||
ch = z_readb(hwif->io_ports[IDE_IRQ_OFFSET]);
|
ch = z_readb(hwif->io_ports.irq_addr);
|
||||||
if (!(ch & GAYLE_IRQ_IDE))
|
if (!(ch & GAYLE_IRQ_IDE))
|
||||||
return 0;
|
return 0;
|
||||||
return 1;
|
return 1;
|
||||||
@ -86,11 +86,11 @@ static int gayle_ack_intr_a1200(ide_hwif_t *hwif)
|
|||||||
{
|
{
|
||||||
unsigned char ch;
|
unsigned char ch;
|
||||||
|
|
||||||
ch = z_readb(hwif->io_ports[IDE_IRQ_OFFSET]);
|
ch = z_readb(hwif->io_ports.irq_addr);
|
||||||
if (!(ch & GAYLE_IRQ_IDE))
|
if (!(ch & GAYLE_IRQ_IDE))
|
||||||
return 0;
|
return 0;
|
||||||
(void)z_readb(hwif->io_ports[IDE_STATUS_OFFSET]);
|
(void)z_readb(hwif->io_ports.status_addr);
|
||||||
z_writeb(0x7c, hwif->io_ports[IDE_IRQ_OFFSET]);
|
z_writeb(0x7c, hwif->io_ports.irq_addr);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -102,13 +102,13 @@ static void __init gayle_setup_ports(hw_regs_t *hw, unsigned long base,
|
|||||||
|
|
||||||
memset(hw, 0, sizeof(*hw));
|
memset(hw, 0, sizeof(*hw));
|
||||||
|
|
||||||
hw->io_ports[IDE_DATA_OFFSET] = base;
|
hw->io_ports.data_addr = base;
|
||||||
|
|
||||||
for (i = 1; i < 8; i++)
|
for (i = 1; i < 8; i++)
|
||||||
hw->io_ports[i] = base + 2 + i * 4;
|
hw->io_ports_array[i] = base + 2 + i * 4;
|
||||||
|
|
||||||
hw->io_ports[IDE_CONTROL_OFFSET] = ctl;
|
hw->io_ports.ctl_addr = ctl;
|
||||||
hw->io_ports[IDE_IRQ_OFFSET] = irq_port;
|
hw->io_ports.irq_addr = irq_port;
|
||||||
|
|
||||||
hw->irq = IRQ_AMIGA_PORTS;
|
hw->irq = IRQ_AMIGA_PORTS;
|
||||||
hw->ack_intr = ack_intr;
|
hw->ack_intr = ack_intr;
|
||||||
|
@ -157,8 +157,8 @@ static void ht6560b_selectproc (ide_drive_t *drive)
|
|||||||
/*
|
/*
|
||||||
* Set timing for this drive:
|
* Set timing for this drive:
|
||||||
*/
|
*/
|
||||||
outb(timing, hwif->io_ports[IDE_SELECT_OFFSET]);
|
outb(timing, hwif->io_ports.device_addr);
|
||||||
(void)inb(hwif->io_ports[IDE_STATUS_OFFSET]);
|
(void)inb(hwif->io_ports.status_addr);
|
||||||
#ifdef DEBUG
|
#ifdef DEBUG
|
||||||
printk("ht6560b: %s: select=%#x timing=%#x\n",
|
printk("ht6560b: %s: select=%#x timing=%#x\n",
|
||||||
drive->name, select, timing);
|
drive->name, select, timing);
|
||||||
|
@ -140,8 +140,8 @@ static void ide_detach(struct pcmcia_device *link)
|
|||||||
|
|
||||||
ide_release(link);
|
ide_release(link);
|
||||||
|
|
||||||
release_region(hwif->io_ports[IDE_CONTROL_OFFSET], 1);
|
release_region(hwif->io_ports.ctl_addr, 1);
|
||||||
release_region(hwif->io_ports[IDE_DATA_OFFSET], 8);
|
release_region(hwif->io_ports.data_addr, 8);
|
||||||
|
|
||||||
kfree(info);
|
kfree(info);
|
||||||
} /* ide_detach */
|
} /* ide_detach */
|
||||||
|
@ -30,14 +30,14 @@ static void __devinit plat_ide_setup_ports(hw_regs_t *hw,
|
|||||||
unsigned long port = (unsigned long)base;
|
unsigned long port = (unsigned long)base;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
hw->io_ports[IDE_DATA_OFFSET] = port;
|
hw->io_ports.data_addr = port;
|
||||||
|
|
||||||
port += (1 << pdata->ioport_shift);
|
port += (1 << pdata->ioport_shift);
|
||||||
for (i = IDE_ERROR_OFFSET; i <= IDE_STATUS_OFFSET;
|
for (i = 1; i <= 7;
|
||||||
i++, port += (1 << pdata->ioport_shift))
|
i++, port += (1 << pdata->ioport_shift))
|
||||||
hw->io_ports[i] = port;
|
hw->io_ports_array[i] = port;
|
||||||
|
|
||||||
hw->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)ctrl;
|
hw->io_ports.ctl_addr = (unsigned long)ctrl;
|
||||||
|
|
||||||
hw->irq = irq;
|
hw->irq = irq;
|
||||||
|
|
||||||
|
@ -72,9 +72,9 @@ static void __init macide_setup_ports(hw_regs_t *hw, unsigned long base,
|
|||||||
memset(hw, 0, sizeof(*hw));
|
memset(hw, 0, sizeof(*hw));
|
||||||
|
|
||||||
for (i = 0; i < 8; i++)
|
for (i = 0; i < 8; i++)
|
||||||
hw->io_ports[i] = base + i * 4;
|
hw->io_ports_array[i] = base + i * 4;
|
||||||
|
|
||||||
hw->io_ports[IDE_CONTROL_OFFSET] = base + IDE_CONTROL;
|
hw->io_ports.ctl_addr = base + IDE_CONTROL;
|
||||||
|
|
||||||
hw->irq = irq;
|
hw->irq = irq;
|
||||||
hw->ack_intr = ack_intr;
|
hw->ack_intr = ack_intr;
|
||||||
|
@ -80,10 +80,10 @@ void q40_ide_setup_ports ( hw_regs_t *hw,
|
|||||||
for (i = 0; i < IDE_NR_PORTS; i++) {
|
for (i = 0; i < IDE_NR_PORTS; i++) {
|
||||||
/* BIG FAT WARNING:
|
/* BIG FAT WARNING:
|
||||||
assumption: only DATA port is ever used in 16 bit mode */
|
assumption: only DATA port is ever used in 16 bit mode */
|
||||||
if ( i==0 )
|
if (i == 0)
|
||||||
hw->io_ports[i] = Q40_ISA_IO_W(base + offsets[i]);
|
hw->io_ports_array[i] = Q40_ISA_IO_W(base + offsets[i]);
|
||||||
else
|
else
|
||||||
hw->io_ports[i] = Q40_ISA_IO_B(base + offsets[i]);
|
hw->io_ports_array[i] = Q40_ISA_IO_B(base + offsets[i]);
|
||||||
}
|
}
|
||||||
|
|
||||||
hw->irq = irq;
|
hw->irq = irq;
|
||||||
|
@ -502,12 +502,11 @@ static int auide_ddma_init(ide_hwif_t *hwif, const struct ide_port_info *d)
|
|||||||
static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
|
static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
unsigned long *ata_regs = hw->io_ports;
|
unsigned long *ata_regs = hw->io_ports_array;
|
||||||
|
|
||||||
/* FIXME? */
|
/* FIXME? */
|
||||||
for (i = 0; i < IDE_CONTROL_OFFSET; i++) {
|
for (i = 0; i < 8; i++)
|
||||||
*ata_regs++ = ahwif->regbase + (i << AU1XXX_ATA_REG_OFFSET);
|
*ata_regs++ = ahwif->regbase + (i << AU1XXX_ATA_REG_OFFSET);
|
||||||
}
|
|
||||||
|
|
||||||
/* set the Alternative Status register */
|
/* set the Alternative Status register */
|
||||||
*ata_regs = ahwif->regbase + (14 << AU1XXX_ATA_REG_OFFSET);
|
*ata_regs = ahwif->regbase + (14 << AU1XXX_ATA_REG_OFFSET);
|
||||||
|
@ -113,10 +113,10 @@ static int __devinit swarm_ide_probe(struct device *dev)
|
|||||||
|
|
||||||
hwif->chipset = ide_generic;
|
hwif->chipset = ide_generic;
|
||||||
|
|
||||||
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
|
for (i = 0; i <= 7; i++)
|
||||||
hwif->io_ports[i] =
|
hwif->io_ports_array[i] =
|
||||||
(unsigned long)(base + ((0x1f0 + i) << 5));
|
(unsigned long)(base + ((0x1f0 + i) << 5));
|
||||||
hwif->io_ports[IDE_CONTROL_OFFSET] =
|
hwif->io_ports.ctl_addr =
|
||||||
(unsigned long)(base + (0x3f6 << 5));
|
(unsigned long)(base + (0x3f6 << 5));
|
||||||
hwif->irq = K_INT_GB_IDE;
|
hwif->irq = K_INT_GB_IDE;
|
||||||
|
|
||||||
|
@ -347,12 +347,12 @@ static int __init secondary_port_responding(void)
|
|||||||
|
|
||||||
spin_lock_irqsave(&cmd640_lock, flags);
|
spin_lock_irqsave(&cmd640_lock, flags);
|
||||||
|
|
||||||
outb_p(0x0a, 0x170 + IDE_SELECT_OFFSET); /* select drive0 */
|
outb_p(0x0a, 0x176); /* select drive0 */
|
||||||
udelay(100);
|
udelay(100);
|
||||||
if ((inb_p(0x170 + IDE_SELECT_OFFSET) & 0x1f) != 0x0a) {
|
if ((inb_p(0x176) & 0x1f) != 0x0a) {
|
||||||
outb_p(0x1a, 0x170 + IDE_SELECT_OFFSET); /* select drive1 */
|
outb_p(0x1a, 0x176); /* select drive1 */
|
||||||
udelay(100);
|
udelay(100);
|
||||||
if ((inb_p(0x170 + IDE_SELECT_OFFSET) & 0x1f) != 0x1a) {
|
if ((inb_p(0x176) & 0x1f) != 0x1a) {
|
||||||
spin_unlock_irqrestore(&cmd640_lock, flags);
|
spin_unlock_irqrestore(&cmd640_lock, flags);
|
||||||
return 0; /* nothing responded */
|
return 0; /* nothing responded */
|
||||||
}
|
}
|
||||||
|
@ -760,7 +760,7 @@ static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
|
|||||||
}
|
}
|
||||||
} else
|
} else
|
||||||
outb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
|
outb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
|
||||||
hwif->io_ports[IDE_CONTROL_OFFSET]);
|
hwif->io_ports.ctl_addr);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -72,8 +72,8 @@ static void __devinit superio_ide_init_iops (struct hwif_s *hwif)
|
|||||||
base = pci_resource_start(pdev, port * 2) & ~3;
|
base = pci_resource_start(pdev, port * 2) & ~3;
|
||||||
dmabase = pci_resource_start(pdev, 4) & ~3;
|
dmabase = pci_resource_start(pdev, 4) & ~3;
|
||||||
|
|
||||||
superio_ide_status[port] = base + IDE_STATUS_OFFSET;
|
superio_ide_status[port] = base + 7;
|
||||||
superio_ide_select[port] = base + IDE_SELECT_OFFSET;
|
superio_ide_select[port] = base + 6;
|
||||||
superio_ide_dma_status[port] = dmabase + (!port ? 2 : 0xa);
|
superio_ide_dma_status[port] = dmabase + (!port ? 2 : 0xa);
|
||||||
|
|
||||||
/* Clear error/interrupt, enable dma */
|
/* Clear error/interrupt, enable dma */
|
||||||
@ -231,12 +231,12 @@ static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
|
|||||||
* SELECT_DRIVE() properly during first ide_probe_port().
|
* SELECT_DRIVE() properly during first ide_probe_port().
|
||||||
*/
|
*/
|
||||||
timeout = 10000;
|
timeout = 10000;
|
||||||
outb(12, hwif->io_ports[IDE_CONTROL_OFFSET]);
|
outb(12, hwif->io_ports.ctl_addr);
|
||||||
udelay(10);
|
udelay(10);
|
||||||
outb(8, hwif->io_ports[IDE_CONTROL_OFFSET]);
|
outb(8, hwif->io_ports.ctl_addr);
|
||||||
do {
|
do {
|
||||||
udelay(50);
|
udelay(50);
|
||||||
stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]);
|
stat = hwif->INB(hwif->io_ports.status_addr);
|
||||||
if (stat == 0xff)
|
if (stat == 0xff)
|
||||||
break;
|
break;
|
||||||
} while ((stat & BUSY_STAT) && --timeout);
|
} while ((stat & BUSY_STAT) && --timeout);
|
||||||
@ -244,7 +244,7 @@ static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (!using_inta)
|
if (!using_inta)
|
||||||
hwif->irq = ide_default_irq(hwif->io_ports[IDE_DATA_OFFSET]);
|
hwif->irq = ide_default_irq(hwif->io_ports.data_addr);
|
||||||
else if (!hwif->irq && hwif->mate && hwif->mate->irq)
|
else if (!hwif->irq && hwif->mate && hwif->mate->irq)
|
||||||
hwif->irq = hwif->mate->irq; /* share IRQ with mate */
|
hwif->irq = hwif->mate->irq; /* share IRQ with mate */
|
||||||
|
|
||||||
|
@ -279,7 +279,7 @@ static void opti621_set_pio_mode(ide_drive_t *drive, const u8 pio)
|
|||||||
|
|
||||||
spin_lock_irqsave(&opti621_lock, flags);
|
spin_lock_irqsave(&opti621_lock, flags);
|
||||||
|
|
||||||
reg_base = hwif->io_ports[IDE_DATA_OFFSET];
|
reg_base = hwif->io_ports.data_addr;
|
||||||
|
|
||||||
/* allow Register-B */
|
/* allow Register-B */
|
||||||
outb(0xc0, reg_base + CNTRL_REG);
|
outb(0xc0, reg_base + CNTRL_REG);
|
||||||
|
@ -334,7 +334,7 @@ static int scc_dma_end(ide_drive_t *drive)
|
|||||||
|
|
||||||
/* errata A308 workaround: Step5 (check data loss) */
|
/* errata A308 workaround: Step5 (check data loss) */
|
||||||
/* We don't check non ide_disk because it is limited to UDMA4 */
|
/* We don't check non ide_disk because it is limited to UDMA4 */
|
||||||
if (!(in_be32((void __iomem *)hwif->io_ports[IDE_ALTSTATUS_OFFSET])
|
if (!(in_be32((void __iomem *)hwif->io_ports.ctl_addr)
|
||||||
& ERR_STAT) &&
|
& ERR_STAT) &&
|
||||||
drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
|
drive->media == ide_disk && drive->current_speed > XFER_UDMA_4) {
|
||||||
reg = in_be32((void __iomem *)intsts_port);
|
reg = in_be32((void __iomem *)intsts_port);
|
||||||
@ -438,7 +438,7 @@ static int scc_dma_test_irq(ide_drive_t *drive)
|
|||||||
u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
|
u32 int_stat = in_be32((void __iomem *)hwif->dma_base + 0x014);
|
||||||
|
|
||||||
/* SCC errata A252,A308 workaround: Step4 */
|
/* SCC errata A252,A308 workaround: Step4 */
|
||||||
if ((in_be32((void __iomem *)hwif->io_ports[IDE_ALTSTATUS_OFFSET])
|
if ((in_be32((void __iomem *)hwif->io_ports.ctl_addr)
|
||||||
& ERR_STAT) &&
|
& ERR_STAT) &&
|
||||||
(int_stat & INTSTS_INTRQ))
|
(int_stat & INTSTS_INTRQ))
|
||||||
return 1;
|
return 1;
|
||||||
@ -534,8 +534,8 @@ static int scc_ide_setup_pci_device(struct pci_dev *dev,
|
|||||||
}
|
}
|
||||||
|
|
||||||
memset(&hw, 0, sizeof(hw));
|
memset(&hw, 0, sizeof(hw));
|
||||||
for (i = IDE_DATA_OFFSET; i <= IDE_CONTROL_OFFSET; i++)
|
for (i = 0; i <= 8; i++)
|
||||||
hw.io_ports[i] = ports->dma + 0x20 + i * 4;
|
hw.io_ports_array[i] = ports->dma + 0x20 + i * 4;
|
||||||
hw.irq = dev->irq;
|
hw.irq = dev->irq;
|
||||||
hw.dev = &dev->dev;
|
hw.dev = &dev->dev;
|
||||||
hw.chipset = ide_pci;
|
hw.chipset = ide_pci;
|
||||||
|
@ -98,28 +98,28 @@ sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
|
|||||||
int i;
|
int i;
|
||||||
|
|
||||||
/* Registers are word (32 bit) aligned */
|
/* Registers are word (32 bit) aligned */
|
||||||
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
|
for (i = 0; i <= 7; i++)
|
||||||
hw->io_ports[i] = reg + i * 4;
|
hw->io_ports_array[i] = reg + i * 4;
|
||||||
|
|
||||||
if (ctrl_port)
|
if (ctrl_port)
|
||||||
hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
|
hw->io_ports.ctl_addr = ctrl_port;
|
||||||
|
|
||||||
if (irq_port)
|
if (irq_port)
|
||||||
hw->io_ports[IDE_IRQ_OFFSET] = irq_port;
|
hw->io_ports.irq_addr = irq_port;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void
|
static void
|
||||||
sgiioc4_maskproc(ide_drive_t * drive, int mask)
|
sgiioc4_maskproc(ide_drive_t * drive, int mask)
|
||||||
{
|
{
|
||||||
writeb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
|
writeb(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
|
||||||
(void __iomem *)drive->hwif->io_ports[IDE_CONTROL_OFFSET]);
|
(void __iomem *)drive->hwif->io_ports.ctl_addr);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int
|
static int
|
||||||
sgiioc4_checkirq(ide_hwif_t * hwif)
|
sgiioc4_checkirq(ide_hwif_t * hwif)
|
||||||
{
|
{
|
||||||
unsigned long intr_addr =
|
unsigned long intr_addr =
|
||||||
hwif->io_ports[IDE_IRQ_OFFSET] + IOC4_INTR_REG * 4;
|
hwif->io_ports.irq_addr + IOC4_INTR_REG * 4;
|
||||||
|
|
||||||
if ((u8)readl((void __iomem *)intr_addr) & 0x03)
|
if ((u8)readl((void __iomem *)intr_addr) & 0x03)
|
||||||
return 1;
|
return 1;
|
||||||
@ -134,8 +134,8 @@ sgiioc4_clearirq(ide_drive_t * drive)
|
|||||||
{
|
{
|
||||||
u32 intr_reg;
|
u32 intr_reg;
|
||||||
ide_hwif_t *hwif = HWIF(drive);
|
ide_hwif_t *hwif = HWIF(drive);
|
||||||
unsigned long other_ir =
|
struct ide_io_ports *io_ports = &hwif->io_ports;
|
||||||
hwif->io_ports[IDE_IRQ_OFFSET] + (IOC4_INTR_REG << 2);
|
unsigned long other_ir = io_ports->irq_addr + (IOC4_INTR_REG << 2);
|
||||||
|
|
||||||
/* Code to check for PCI error conditions */
|
/* Code to check for PCI error conditions */
|
||||||
intr_reg = readl((void __iomem *)other_ir);
|
intr_reg = readl((void __iomem *)other_ir);
|
||||||
@ -147,12 +147,12 @@ sgiioc4_clearirq(ide_drive_t * drive)
|
|||||||
* a "clear" status if it got cleared. If not, then spin
|
* a "clear" status if it got cleared. If not, then spin
|
||||||
* for a bit trying to clear it.
|
* for a bit trying to clear it.
|
||||||
*/
|
*/
|
||||||
u8 stat = sgiioc4_INB(hwif->io_ports[IDE_STATUS_OFFSET]);
|
u8 stat = sgiioc4_INB(io_ports->status_addr);
|
||||||
int count = 0;
|
int count = 0;
|
||||||
stat = sgiioc4_INB(hwif->io_ports[IDE_STATUS_OFFSET]);
|
stat = sgiioc4_INB(io_ports->status_addr);
|
||||||
while ((stat & 0x80) && (count++ < 100)) {
|
while ((stat & 0x80) && (count++ < 100)) {
|
||||||
udelay(1);
|
udelay(1);
|
||||||
stat = sgiioc4_INB(hwif->io_ports[IDE_STATUS_OFFSET]);
|
stat = sgiioc4_INB(io_ports->status_addr);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (intr_reg & 0x02) {
|
if (intr_reg & 0x02) {
|
||||||
@ -162,9 +162,9 @@ sgiioc4_clearirq(ide_drive_t * drive)
|
|||||||
pci_stat_cmd_reg;
|
pci_stat_cmd_reg;
|
||||||
|
|
||||||
pci_err_addr_low =
|
pci_err_addr_low =
|
||||||
readl((void __iomem *)hwif->io_ports[IDE_IRQ_OFFSET]);
|
readl((void __iomem *)io_ports->irq_addr);
|
||||||
pci_err_addr_high =
|
pci_err_addr_high =
|
||||||
readl((void __iomem *)(hwif->io_ports[IDE_IRQ_OFFSET] + 4));
|
readl((void __iomem *)(io_ports->irq_addr + 4));
|
||||||
pci_read_config_dword(dev, PCI_COMMAND,
|
pci_read_config_dword(dev, PCI_COMMAND,
|
||||||
&pci_stat_cmd_reg);
|
&pci_stat_cmd_reg);
|
||||||
printk(KERN_ERR
|
printk(KERN_ERR
|
||||||
|
@ -622,9 +622,10 @@ static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
|
|||||||
struct pci_dev *dev = to_pci_dev(hwif->dev);
|
struct pci_dev *dev = to_pci_dev(hwif->dev);
|
||||||
void *addr = pci_get_drvdata(dev);
|
void *addr = pci_get_drvdata(dev);
|
||||||
u8 ch = hwif->channel;
|
u8 ch = hwif->channel;
|
||||||
hw_regs_t hw;
|
|
||||||
unsigned long base;
|
unsigned long base;
|
||||||
|
|
||||||
|
struct ide_io_ports *io_ports = &hwif->io_ports;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Fill in the basic HWIF bits
|
* Fill in the basic HWIF bits
|
||||||
*/
|
*/
|
||||||
@ -638,7 +639,7 @@ static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
|
|||||||
* based I/O
|
* based I/O
|
||||||
*/
|
*/
|
||||||
|
|
||||||
memset(&hw, 0, sizeof(hw_regs_t));
|
memset(io_ports, 0, sizeof(*io_ports));
|
||||||
|
|
||||||
base = (unsigned long)addr;
|
base = (unsigned long)addr;
|
||||||
if (ch)
|
if (ch)
|
||||||
@ -651,17 +652,15 @@ static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
|
|||||||
* so we can't currently use it sanely since we want to
|
* so we can't currently use it sanely since we want to
|
||||||
* use LBA48 mode.
|
* use LBA48 mode.
|
||||||
*/
|
*/
|
||||||
hw.io_ports[IDE_DATA_OFFSET] = base;
|
io_ports->data_addr = base;
|
||||||
hw.io_ports[IDE_ERROR_OFFSET] = base + 1;
|
io_ports->error_addr = base + 1;
|
||||||
hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
|
io_ports->nsect_addr = base + 2;
|
||||||
hw.io_ports[IDE_SECTOR_OFFSET] = base + 3;
|
io_ports->lbal_addr = base + 3;
|
||||||
hw.io_ports[IDE_LCYL_OFFSET] = base + 4;
|
io_ports->lbam_addr = base + 4;
|
||||||
hw.io_ports[IDE_HCYL_OFFSET] = base + 5;
|
io_ports->lbah_addr = base + 5;
|
||||||
hw.io_ports[IDE_SELECT_OFFSET] = base + 6;
|
io_ports->device_addr = base + 6;
|
||||||
hw.io_ports[IDE_STATUS_OFFSET] = base + 7;
|
io_ports->status_addr = base + 7;
|
||||||
hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
|
io_ports->ctl_addr = base + 10;
|
||||||
|
|
||||||
hw.io_ports[IDE_IRQ_OFFSET] = 0;
|
|
||||||
|
|
||||||
if (pdev_is_sata(dev)) {
|
if (pdev_is_sata(dev)) {
|
||||||
base = (unsigned long)addr;
|
base = (unsigned long)addr;
|
||||||
@ -672,8 +671,6 @@ static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
|
|||||||
hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
|
hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
|
||||||
}
|
}
|
||||||
|
|
||||||
memcpy(hwif->io_ports, hw.io_ports, sizeof(hwif->io_ports));
|
|
||||||
|
|
||||||
hwif->irq = dev->irq;
|
hwif->irq = dev->irq;
|
||||||
|
|
||||||
hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00);
|
hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00);
|
||||||
|
@ -298,7 +298,7 @@ static void __devinit init_hwif_trm290(ide_hwif_t *hwif)
|
|||||||
if (old != compat && old_mask == 0xff) {
|
if (old != compat && old_mask == 0xff) {
|
||||||
/* leave lower 10 bits untouched */
|
/* leave lower 10 bits untouched */
|
||||||
compat += (next_offset += 0x400);
|
compat += (next_offset += 0x400);
|
||||||
hwif->io_ports[IDE_CONTROL_OFFSET] = compat + 2;
|
hwif->io_ports.ctl_addr = compat + 2;
|
||||||
outw(compat | 1, hwif->config_data);
|
outw(compat | 1, hwif->config_data);
|
||||||
new = inw(hwif->config_data);
|
new = inw(hwif->config_data);
|
||||||
printk(KERN_INFO "%s: control basereg workaround: "
|
printk(KERN_INFO "%s: control basereg workaround: "
|
||||||
|
@ -131,7 +131,7 @@ static int pcmcia_schlvl = PCMCIA_SCHLVL;
|
|||||||
#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT)
|
#if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT)
|
||||||
static int __init m8xx_ide_init_ports(hw_regs_t *hw, unsigned long data_port)
|
static int __init m8xx_ide_init_ports(hw_regs_t *hw, unsigned long data_port)
|
||||||
{
|
{
|
||||||
unsigned long *p = hw->io_ports;
|
unsigned long *p = hw->io_ports_array;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
typedef struct {
|
typedef struct {
|
||||||
@ -314,7 +314,7 @@ static int __init m8xx_ide_init_ports(hw_regs_t *hw, unsigned long data_port)
|
|||||||
#if defined(CONFIG_IDE_EXT_DIRECT)
|
#if defined(CONFIG_IDE_EXT_DIRECT)
|
||||||
static int __init m8xx_ide_init_ports(hw_regs_t *hw, unsigned long data_port)
|
static int __init m8xx_ide_init_ports(hw_regs_t *hw, unsigned long data_port)
|
||||||
{
|
{
|
||||||
unsigned long *p = hw->io_ports;
|
unsigned long *p = hw->io_ports_array;
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
u32 ide_phy_base;
|
u32 ide_phy_base;
|
||||||
|
@ -417,7 +417,7 @@ static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
|
|||||||
#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
|
#endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
|
||||||
|
|
||||||
#define PMAC_IDE_REG(x) \
|
#define PMAC_IDE_REG(x) \
|
||||||
((void __iomem *)((drive)->hwif->io_ports[IDE_DATA_OFFSET] + (x)))
|
((void __iomem *)((drive)->hwif->io_ports.data_addr + (x)))
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Apply the timings of the proper unit (master/slave) to the shared
|
* Apply the timings of the proper unit (master/slave) to the shared
|
||||||
@ -1086,8 +1086,9 @@ static void __devinit pmac_ide_init_ports(hw_regs_t *hw, unsigned long base)
|
|||||||
int i;
|
int i;
|
||||||
|
|
||||||
for (i = 0; i < 8; ++i)
|
for (i = 0; i < 8; ++i)
|
||||||
hw->io_ports[i] = base + i * 0x10;
|
hw->io_ports_array[i] = base + i * 0x10;
|
||||||
hw->io_ports[8] = base + 0x160;
|
|
||||||
|
hw->io_ports.ctl_addr = base + 0x160;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -258,8 +258,7 @@ idescsi_atapi_error(ide_drive_t *drive, struct request *rq, u8 stat, u8 err)
|
|||||||
|
|
||||||
if (ide_read_status(drive) & (BUSY_STAT | DRQ_STAT))
|
if (ide_read_status(drive) & (BUSY_STAT | DRQ_STAT))
|
||||||
/* force an abort */
|
/* force an abort */
|
||||||
hwif->OUTB(WIN_IDLEIMMEDIATE,
|
hwif->OUTB(WIN_IDLEIMMEDIATE, hwif->io_ports.command_addr);
|
||||||
hwif->io_ports[IDE_COMMAND_OFFSET]);
|
|
||||||
|
|
||||||
rq->errors++;
|
rq->errors++;
|
||||||
|
|
||||||
@ -410,9 +409,9 @@ static ide_startstop_t idescsi_pc_intr (ide_drive_t *drive)
|
|||||||
idescsi_end_request (drive, 1, 0);
|
idescsi_end_request (drive, 1, 0);
|
||||||
return ide_stopped;
|
return ide_stopped;
|
||||||
}
|
}
|
||||||
bcount = (hwif->INB(hwif->io_ports[IDE_BCOUNTH_OFFSET]) << 8) |
|
bcount = (hwif->INB(hwif->io_ports.lbah_addr) << 8) |
|
||||||
hwif->INB(hwif->io_ports[IDE_BCOUNTL_OFFSET]);
|
hwif->INB(hwif->io_ports.lbam_addr);
|
||||||
ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]);
|
ireason = hwif->INB(hwif->io_ports.nsect_addr);
|
||||||
|
|
||||||
if (ireason & CD) {
|
if (ireason & CD) {
|
||||||
printk(KERN_ERR "ide-scsi: CoD != 0 in idescsi_pc_intr\n");
|
printk(KERN_ERR "ide-scsi: CoD != 0 in idescsi_pc_intr\n");
|
||||||
@ -485,7 +484,7 @@ static ide_startstop_t idescsi_transfer_pc(ide_drive_t *drive)
|
|||||||
"initiated yet DRQ isn't asserted\n");
|
"initiated yet DRQ isn't asserted\n");
|
||||||
return startstop;
|
return startstop;
|
||||||
}
|
}
|
||||||
ireason = hwif->INB(hwif->io_ports[IDE_IREASON_OFFSET]);
|
ireason = hwif->INB(hwif->io_ports.nsect_addr);
|
||||||
if ((ireason & CD) == 0 || (ireason & IO)) {
|
if ((ireason & CD) == 0 || (ireason & IO)) {
|
||||||
printk(KERN_ERR "ide-scsi: (IO,CoD) != (0,1) while "
|
printk(KERN_ERR "ide-scsi: (IO,CoD) != (0,1) while "
|
||||||
"issuing a packet command\n");
|
"issuing a packet command\n");
|
||||||
@ -575,7 +574,7 @@ static ide_startstop_t idescsi_issue_pc(ide_drive_t *drive,
|
|||||||
return ide_started;
|
return ide_started;
|
||||||
} else {
|
} else {
|
||||||
/* Issue the packet command */
|
/* Issue the packet command */
|
||||||
hwif->OUTB(WIN_PACKETCMD, hwif->io_ports[IDE_COMMAND_OFFSET]);
|
hwif->OUTB(WIN_PACKETCMD, hwif->io_ports.command_addr);
|
||||||
return idescsi_transfer_pc(drive);
|
return idescsi_transfer_pc(drive);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -37,12 +37,12 @@ static inline void ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port,
|
|||||||
|
|
||||||
memset(hw, 0, sizeof(*hw));
|
memset(hw, 0, sizeof(*hw));
|
||||||
|
|
||||||
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
|
for (i = 0; i <= 7; i++) {
|
||||||
hw->io_ports[i] = reg;
|
hw->io_ports_array[i] = reg;
|
||||||
reg += regincr;
|
reg += regincr;
|
||||||
}
|
}
|
||||||
|
|
||||||
hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
|
hw->io_ports.ctl_addr = ctrl_port;
|
||||||
|
|
||||||
if (irq)
|
if (irq)
|
||||||
*irq = 0;
|
*irq = 0;
|
||||||
|
@ -59,22 +59,19 @@ static inline void ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port, u
|
|||||||
int i;
|
int i;
|
||||||
|
|
||||||
/* fill in ports for ATA addresses 0 to 7 */
|
/* fill in ports for ATA addresses 0 to 7 */
|
||||||
|
for (i = 0; i <= 7; i++) {
|
||||||
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
|
hw->io_ports_array[i] = data_port |
|
||||||
hw->io_ports[i] = data_port |
|
|
||||||
IO_FIELD(R_ATA_CTRL_DATA, addr, i) |
|
IO_FIELD(R_ATA_CTRL_DATA, addr, i) |
|
||||||
IO_STATE(R_ATA_CTRL_DATA, cs0, active);
|
IO_STATE(R_ATA_CTRL_DATA, cs0, active);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* the IDE control register is at ATA address 6, with CS1 active instead of CS0 */
|
/* the IDE control register is at ATA address 6, with CS1 active instead of CS0 */
|
||||||
|
hw->io_ports.ctl_addr = data_port |
|
||||||
hw->io_ports[IDE_CONTROL_OFFSET] = data_port |
|
|
||||||
IO_FIELD(R_ATA_CTRL_DATA, addr, 6) |
|
IO_FIELD(R_ATA_CTRL_DATA, addr, 6) |
|
||||||
IO_STATE(R_ATA_CTRL_DATA, cs1, active);
|
IO_STATE(R_ATA_CTRL_DATA, cs1, active);
|
||||||
|
|
||||||
/* whats this for ? */
|
/* whats this for ? */
|
||||||
|
hw->io_ports.irq_addr = 0;
|
||||||
hw->io_ports[IDE_IRQ_OFFSET] = 0;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void ide_init_default_hwifs(void)
|
static inline void ide_init_default_hwifs(void)
|
||||||
|
@ -61,23 +61,30 @@ typedef unsigned char byte; /* used everywhere */
|
|||||||
*/
|
*/
|
||||||
#define IDE_NR_PORTS (10)
|
#define IDE_NR_PORTS (10)
|
||||||
|
|
||||||
#define IDE_DATA_OFFSET (0)
|
struct ide_io_ports {
|
||||||
#define IDE_ERROR_OFFSET (1)
|
unsigned long data_addr;
|
||||||
#define IDE_NSECTOR_OFFSET (2)
|
|
||||||
#define IDE_SECTOR_OFFSET (3)
|
|
||||||
#define IDE_LCYL_OFFSET (4)
|
|
||||||
#define IDE_HCYL_OFFSET (5)
|
|
||||||
#define IDE_SELECT_OFFSET (6)
|
|
||||||
#define IDE_STATUS_OFFSET (7)
|
|
||||||
#define IDE_CONTROL_OFFSET (8)
|
|
||||||
#define IDE_IRQ_OFFSET (9)
|
|
||||||
|
|
||||||
#define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET
|
union {
|
||||||
#define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET
|
unsigned long error_addr; /* read: error */
|
||||||
#define IDE_ALTSTATUS_OFFSET IDE_CONTROL_OFFSET
|
unsigned long feature_addr; /* write: feature */
|
||||||
#define IDE_IREASON_OFFSET IDE_NSECTOR_OFFSET
|
};
|
||||||
#define IDE_BCOUNTL_OFFSET IDE_LCYL_OFFSET
|
|
||||||
#define IDE_BCOUNTH_OFFSET IDE_HCYL_OFFSET
|
unsigned long nsect_addr;
|
||||||
|
unsigned long lbal_addr;
|
||||||
|
unsigned long lbam_addr;
|
||||||
|
unsigned long lbah_addr;
|
||||||
|
|
||||||
|
unsigned long device_addr;
|
||||||
|
|
||||||
|
union {
|
||||||
|
unsigned long status_addr; /* read: status */
|
||||||
|
unsigned long command_addr; /* write: command */
|
||||||
|
};
|
||||||
|
|
||||||
|
unsigned long ctl_addr;
|
||||||
|
|
||||||
|
unsigned long irq_addr;
|
||||||
|
};
|
||||||
|
|
||||||
#define OK_STAT(stat,good,bad) (((stat)&((good)|(bad)))==(good))
|
#define OK_STAT(stat,good,bad) (((stat)&((good)|(bad)))==(good))
|
||||||
#define BAD_R_STAT (BUSY_STAT | ERR_STAT)
|
#define BAD_R_STAT (BUSY_STAT | ERR_STAT)
|
||||||
@ -156,7 +163,11 @@ typedef u8 hwif_chipset_t;
|
|||||||
* Structure to hold all information about the location of this port
|
* Structure to hold all information about the location of this port
|
||||||
*/
|
*/
|
||||||
typedef struct hw_regs_s {
|
typedef struct hw_regs_s {
|
||||||
unsigned long io_ports[IDE_NR_PORTS]; /* task file registers */
|
union {
|
||||||
|
struct ide_io_ports io_ports;
|
||||||
|
unsigned long io_ports_array[IDE_NR_PORTS];
|
||||||
|
};
|
||||||
|
|
||||||
int irq; /* our irq number */
|
int irq; /* our irq number */
|
||||||
ide_ack_intr_t *ack_intr; /* acknowledge interrupt */
|
ide_ack_intr_t *ack_intr; /* acknowledge interrupt */
|
||||||
hwif_chipset_t chipset;
|
hwif_chipset_t chipset;
|
||||||
@ -172,10 +183,10 @@ static inline void ide_std_init_ports(hw_regs_t *hw,
|
|||||||
{
|
{
|
||||||
unsigned int i;
|
unsigned int i;
|
||||||
|
|
||||||
for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++)
|
for (i = 0; i <= 7; i++)
|
||||||
hw->io_ports[i] = io_addr++;
|
hw->io_ports_array[i] = io_addr++;
|
||||||
|
|
||||||
hw->io_ports[IDE_CONTROL_OFFSET] = ctl_addr;
|
hw->io_ports.ctl_addr = ctl_addr;
|
||||||
}
|
}
|
||||||
|
|
||||||
#include <asm/ide.h>
|
#include <asm/ide.h>
|
||||||
@ -424,8 +435,8 @@ typedef struct hwif_s {
|
|||||||
|
|
||||||
char name[6]; /* name of interface, eg. "ide0" */
|
char name[6]; /* name of interface, eg. "ide0" */
|
||||||
|
|
||||||
/* task file registers for pata and sata */
|
struct ide_io_ports io_ports;
|
||||||
unsigned long io_ports[IDE_NR_PORTS];
|
|
||||||
unsigned long sata_scr[SATA_NR_PORTS];
|
unsigned long sata_scr[SATA_NR_PORTS];
|
||||||
|
|
||||||
ide_drive_t drives[MAX_DRIVES]; /* drive info */
|
ide_drive_t drives[MAX_DRIVES]; /* drive info */
|
||||||
@ -1330,29 +1341,28 @@ static inline void ide_set_irq(ide_drive_t *drive, int on)
|
|||||||
{
|
{
|
||||||
ide_hwif_t *hwif = drive->hwif;
|
ide_hwif_t *hwif = drive->hwif;
|
||||||
|
|
||||||
hwif->OUTB(drive->ctl | (on ? 0 : 2),
|
hwif->OUTB(drive->ctl | (on ? 0 : 2), hwif->io_ports.ctl_addr);
|
||||||
hwif->io_ports[IDE_CONTROL_OFFSET]);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline u8 ide_read_status(ide_drive_t *drive)
|
static inline u8 ide_read_status(ide_drive_t *drive)
|
||||||
{
|
{
|
||||||
ide_hwif_t *hwif = drive->hwif;
|
ide_hwif_t *hwif = drive->hwif;
|
||||||
|
|
||||||
return hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]);
|
return hwif->INB(hwif->io_ports.status_addr);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline u8 ide_read_altstatus(ide_drive_t *drive)
|
static inline u8 ide_read_altstatus(ide_drive_t *drive)
|
||||||
{
|
{
|
||||||
ide_hwif_t *hwif = drive->hwif;
|
ide_hwif_t *hwif = drive->hwif;
|
||||||
|
|
||||||
return hwif->INB(hwif->io_ports[IDE_CONTROL_OFFSET]);
|
return hwif->INB(hwif->io_ports.ctl_addr);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline u8 ide_read_error(ide_drive_t *drive)
|
static inline u8 ide_read_error(ide_drive_t *drive)
|
||||||
{
|
{
|
||||||
ide_hwif_t *hwif = drive->hwif;
|
ide_hwif_t *hwif = drive->hwif;
|
||||||
|
|
||||||
return hwif->INB(hwif->io_ports[IDE_ERROR_OFFSET]);
|
return hwif->INB(hwif->io_ports.error_addr);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -1365,7 +1375,7 @@ static inline void ide_atapi_discard_data(ide_drive_t *drive, unsigned bcount)
|
|||||||
|
|
||||||
/* FIXME: use ->atapi_input_bytes */
|
/* FIXME: use ->atapi_input_bytes */
|
||||||
while (bcount--)
|
while (bcount--)
|
||||||
(void)hwif->INB(hwif->io_ports[IDE_DATA_OFFSET]);
|
(void)hwif->INB(hwif->io_ports.data_addr);
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void ide_atapi_write_zeros(ide_drive_t *drive, unsigned bcount)
|
static inline void ide_atapi_write_zeros(ide_drive_t *drive, unsigned bcount)
|
||||||
@ -1374,7 +1384,7 @@ static inline void ide_atapi_write_zeros(ide_drive_t *drive, unsigned bcount)
|
|||||||
|
|
||||||
/* FIXME: use ->atapi_output_bytes */
|
/* FIXME: use ->atapi_output_bytes */
|
||||||
while (bcount--)
|
while (bcount--)
|
||||||
hwif->OUTB(0, hwif->io_ports[IDE_DATA_OFFSET]);
|
hwif->OUTB(0, hwif->io_ports.data_addr);
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* _IDE_H */
|
#endif /* _IDE_H */
|
||||||
|
Loading…
Reference in New Issue
Block a user