korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-11-30 23:54:04 +08:00
Code Issues Packages Projects Releases Wiki Activity

perf vendor events s390: Add metric for TLB and cache

Browse Source 
Add metrics for tlb and cache statistics:

- finite_cpi: Cycles per Instructions from Finite cache/memory
- est_cpi: Estimated Instruction Complexity CPI infinite Level 1
- scpl1m: Estimated Sourcing Cycles per Level 1 Miss
- tlb_percent: Estimated TLB CPU percentage of Total CPU
- tlb_miss: Estimated Cycles per TLB Miss

For details about the formulas see this documentation:

  https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf

Output after:

  # ./perf stat -M tlb_miss -- dd if=/dev/zero of=/dev/null bs=1M count=10K
  ... dd output removed

  Performance counter stats for 'dd if=/dev/zero of=/dev/null bs=1M count=10K':

           667,726      DTLB2_MISSES             #   440.96 tlb_miss
               198      ITLB2_WRITES
       795,170,260      L1C_TLB2_MISSES
             9,478      ITLB2_MISSES
               820      DTLB2_WRITES
     1,197,126,869      L1D_PENALTY_CYCLES
         2,457,447      L1I_PENALTY_CYCLES

       1.249342187 seconds time elapsed

       0.001030000 seconds user
       1.248105000 seconds sys

  #

Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
Acked-by: Ian Rogers <irogers@google.com>
Acked-By: Sumanth Korikkar <sumanthk@linux.ibm.com>
Cc: Heiko Carstens <hca@linux.ibm.com>
Cc: Sven Schnelle <svens@linux.ibm.com>
Cc: Vasily Gorbik <gor@linux.ibm.com>
Link: https://lore.kernel.org/r/20230313080201.2440201-3-tmricht@linux.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Thomas Richter 2023-03-13 09:02:01 +01:00 committed by Arnaldo Carvalho de Melo
parent 850eea236f
commit 4c290d4fa3
4 changed files with 105 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

30
tools/perf/pmu-events/arch/s390/cf_z13/transaction.json
View File

@ -43,5 +43,35 @@
"BriefDescription": "Percentage sourced from memory",
"MetricName": "memp",
"MetricExpr": "((L1D_ONNODE_MEM_SOURCED_WRITES + L1D_ONDRAWER_MEM_SOURCED_WRITES + L1D_OFFDRAWER_MEM_SOURCED_WRITES + L1D_ONCHIP_MEM_SOURCED_WRITES + L1I_ONNODE_MEM_SOURCED_WRITES + L1I_ONDRAWER_MEM_SOURCED_WRITES + L1I_OFFDRAWER_MEM_SOURCED_WRITES + L1I_ONCHIP_MEM_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
},
{
"BriefDescription": "Cycles per Instructions from Finite cache/memory",
"MetricName": "finite_cpi",
"MetricExpr": "L1C_TLB1_MISSES / INSTRUCTIONS"
},
{
"BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1",
"MetricName": "est_cpi",
"MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB1_MISSES / INSTRUCTIONS)"
},
{
"BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss",
"MetricName": "scpl1m",
"MetricExpr": "L1C_TLB1_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)"
},
{
"BriefDescription": "Estimated TLB CPU percentage of Total CPU",
"MetricName": "tlb_percent",
"MetricExpr": "((DTLB1_MISSES + ITLB1_MISSES) / CPU_CYCLES) * (L1C_TLB1_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100"
},
{
"BriefDescription": "Estimated Cycles per TLB Miss",
"MetricName": "tlb_miss",
"MetricExpr": "((DTLB1_MISSES + ITLB1_MISSES) / (DTLB1_WRITES + ITLB1_WRITES)) * (L1C_TLB1_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))"
},
{
"BriefDescription": "Page Table Entry misses",
"MetricName": "pte_miss",
"MetricExpr": "(TLB2_PTE_WRITES / (DTLB1_WRITES + ITLB1_WRITES)) * 100"
}
]

25
tools/perf/pmu-events/arch/s390/cf_z14/transaction.json
View File

@ -43,5 +43,30 @@
"BriefDescription": "Percentage sourced from memory",
"MetricName": "memp",
"MetricExpr": "((L1D_ONCHIP_MEMORY_SOURCED_WRITES + L1D_ONCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFDRAWER_MEMORY_SOURCED_WRITES + L1I_ONCHIP_MEMORY_SOURCED_WRITES + L1I_ONCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFDRAWER_MEMORY_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
},
{
"BriefDescription": "Cycles per Instructions from Finite cache/memory",
"MetricName": "finite_cpi",
"MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS"
},
{
"BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1",
"MetricName": "est_cpi",
"MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)"
},
{
"BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss",
"MetricName": "scpl1m",
"MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)"
},
{
"BriefDescription": "Estimated TLB CPU percentage of Total CPU",
"MetricName": "tlb_percent",
"MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100"
},
{
"BriefDescription": "Estimated Cycles per TLB Miss",
"MetricName": "tlb_miss",
"MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))"
}
]

25
tools/perf/pmu-events/arch/s390/cf_z15/transaction.json
View File

@ -43,5 +43,30 @@
"BriefDescription": "Percentage sourced from memory",
"MetricName": "memp",
"MetricExpr": "((L1D_ONCHIP_MEMORY_SOURCED_WRITES + L1D_ONCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFDRAWER_MEMORY_SOURCED_WRITES + L1I_ONCHIP_MEMORY_SOURCED_WRITES + L1I_ONCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFDRAWER_MEMORY_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
},
{
"BriefDescription": "Cycles per Instructions from Finite cache/memory",
"MetricName": "finite_cpi",
"MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS"
},
{
"BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1",
"MetricName": "est_cpi",
"MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)"
},
{
"BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss",
"MetricName": "scpl1m",
"MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)"
},
{
"BriefDescription": "Estimated TLB CPU percentage of Total CPU",
"MetricName": "tlb_percent",
"MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100"
},
{
"BriefDescription": "Estimated Cycles per TLB Miss",
"MetricName": "tlb_miss",
"MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))"
}
]

25
tools/perf/pmu-events/arch/s390/cf_z16/transaction.json
View File

@ -43,5 +43,30 @@
"BriefDescription": "Percentage sourced from memory",
"MetricName": "memp",
"MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
},
{
"BriefDescription": "Cycles per Instructions from Finite cache/memory",
"MetricName": "finite_cpi",
"MetricExpr": "L1C_TLB2_MISSES / INSTRUCTIONS"
},
{
"BriefDescription": "Estimated Instruction Complexity CPI infinite Level 1",
"MetricName": "est_cpi",
"MetricExpr": "(CPU_CYCLES / INSTRUCTIONS) - (L1C_TLB2_MISSES / INSTRUCTIONS)"
},
{
"BriefDescription": "Estimated Sourcing Cycles per Level 1 Miss",
"MetricName": "scpl1m",
"MetricExpr": "L1C_TLB2_MISSES / (L1I_DIR_WRITES + L1D_DIR_WRITES)"
},
{
"BriefDescription": "Estimated TLB CPU percentage of Total CPU",
"MetricName": "tlb_percent",
"MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / CPU_CYCLES) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES)) * 100"
},
{
"BriefDescription": "Estimated Cycles per TLB Miss",
"MetricName": "tlb_miss",
"MetricExpr": "((DTLB2_MISSES + ITLB2_MISSES) / (DTLB2_WRITES + ITLB2_WRITES)) * (L1C_TLB2_MISSES / (L1I_PENALTY_CYCLES + L1D_PENALTY_CYCLES))"
}
]