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ARM: mv78xx0: add code to enable XOR and CRYPTO engines on mv78xx0

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Adding missing code/values required to enable the XOR and CESA engines for this SoC

Signed-off-by: Jeremy J. Peper <jeremy@jeremypeper.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Jeremy J. Peper 2023-03-17 10:43:46 -05:00 committed by Arnd Bergmann
parent 189e3ddb64
commit 4b01f735a6
4 changed files with 37 additions and 0 deletions
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2
arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
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@ -119,6 +119,8 @@ static void __init wxl_init(void)
mv78xx0_uart1_init();
mv78xx0_uart2_init();
mv78xx0_uart3_init();
mv78xx0_xor_init();
mv78xx0_crypto_init();
mv78xx0_i2c_init();
i2c_register_board_info(0, &db78x00_i2c_rtc, 1);
}

23
arch/arm/mach-mv78xx0/common.c
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@ -342,6 +342,29 @@ void __ref mv78xx0_timer_init(void)
IRQ_MV78XX0_TIMER_1, get_tclk());
}
/****************************************************************************
* XOR engine
****************************************************************************/
void __init mv78xx0_xor_init(void)
{
orion_xor0_init(XOR_PHYS_BASE,
XOR_PHYS_BASE + 0x200,
IRQ_MV78XX0_XOR_0, IRQ_MV78XX0_XOR_1);
}
/****************************************************************************
* Cryptographic Engines and Security Accelerator (CESA)
****************************************************************************/
void __init mv78xx0_crypto_init(void)
{
mvebu_mbus_add_window_by_id(MV78XX0_MBUS_SRAM_TARGET,
MV78XX0_MBUS_SRAM_ATTR,
MV78XX0_SRAM_PHYS_BASE,
MV78XX0_SRAM_SIZE);
orion_crypto_init(CRYPTO_PHYS_BASE, MV78XX0_SRAM_PHYS_BASE,
SZ_8K, IRQ_MV78XX0_CRYPTO);
}
/*****************************************************************************
* General

2
arch/arm/mach-mv78xx0/common.h
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@ -43,6 +43,8 @@ void mv78xx0_uart0_init(void);
void mv78xx0_uart1_init(void);
void mv78xx0_uart2_init(void);
void mv78xx0_uart3_init(void);
void mv78xx0_xor_init(void);
void mv78xx0_crypto_init(void);
void mv78xx0_i2c_init(void);
void mv78xx0_restart(enum reboot_mode, const char *);

10
arch/arm/mach-mv78xx0/mv78xx0.h
View File

@ -49,9 +49,15 @@
#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
#define MV78XX0_REGS_SIZE SZ_1M
#define MV78XX0_SRAM_PHYS_BASE (0xf2200000)
#define MV78XX0_SRAM_SIZE SZ_8K
#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
#define MV78XX0_PCIE_MEM_SIZE 0x30000000
#define MV78XX0_MBUS_SRAM_TARGET 0x09
#define MV78XX0_MBUS_SRAM_ATTR 0x00
/*
* Core-specific peripheral registers.
*/
@ -98,6 +104,8 @@
#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000)
#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000)
#define XOR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x60900)
#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000)
#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000)
@ -106,6 +114,8 @@
#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000)
#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000)
#define CRYPTO_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x90000)
#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000)
/*