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drm/i915: Rename HSW/BDW PLL bits

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Give the PLL control register bits better names on HSW/BDW.

v2: Fix the copy paste fails in SPLL_REF defines (Maarten)

Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190610133609.27288-1-ville.syrjala@linux.intel.com
Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> #irc
This commit is contained in:
Ville Syrjälä 2019-06-10 16:36:09 +03:00
parent b16c7ed95c
commit 4a95e36f03
4 changed files with 34 additions and 26 deletions
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32
drivers/gpu/drm/i915/i915_reg.h
View File

@ -9466,24 +9466,28 @@ enum skl_power_gate {
/* SPLL */
#define SPLL_CTL _MMIO(0x46020)
#define SPLL_PLL_ENABLE (1 << 31)
#define SPLL_PLL_SSC (1 << 28)
#define SPLL_PLL_NON_SSC (2 << 28)
#define SPLL_PLL_LCPLL (3 << 28)
#define SPLL_PLL_REF_MASK (3 << 28)
#define SPLL_PLL_FREQ_810MHz (0 << 26)
#define SPLL_PLL_FREQ_1350MHz (1 << 26)
#define SPLL_PLL_FREQ_2700MHz (2 << 26)
#define SPLL_PLL_FREQ_MASK (3 << 26)
#define SPLL_REF_BCLK (0 << 28)
#define SPLL_REF_MUXED_SSC (1 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
#define SPLL_REF_NON_SSC_HSW (2 << 28)
#define SPLL_REF_PCH_SSC_BDW (2 << 28)
#define SPLL_REF_LCPLL (3 << 28)
#define SPLL_REF_MASK (3 << 28)
#define SPLL_FREQ_810MHz (0 << 26)
#define SPLL_FREQ_1350MHz (1 << 26)
#define SPLL_FREQ_2700MHz (2 << 26)
#define SPLL_FREQ_MASK (3 << 26)
/* WRPLL */
#define _WRPLL_CTL1 0x46040
#define _WRPLL_CTL2 0x46060
#define WRPLL_CTL(pll) _MMIO_PIPE(pll, _WRPLL_CTL1, _WRPLL_CTL2)
#define WRPLL_PLL_ENABLE (1 << 31)
#define WRPLL_PLL_SSC (1 << 28)
#define WRPLL_PLL_NON_SSC (2 << 28)
#define WRPLL_PLL_LCPLL (3 << 28)
#define WRPLL_PLL_REF_MASK (3 << 28)
#define WRPLL_REF_BCLK (0 << 28)
#define WRPLL_REF_PCH_SSC (1 << 28)
#define WRPLL_REF_MUXED_SSC_BDW (2 << 28) /* CPU SSC if fused enabled, PCH SSC otherwise */
#define WRPLL_REF_SPECIAL_HSW (2 << 28) /* muxed SSC (ULT), non-SSC (non-ULT) */
#define WRPLL_REF_LCPLL (3 << 28)
#define WRPLL_REF_MASK (3 << 28)
/* WRPLL divider programming */
#define WRPLL_DIVIDER_REFERENCE(x) ((x) << 0)
#define WRPLL_DIVIDER_REF_MASK (0xff)
@ -9549,6 +9553,10 @@ enum skl_power_gate {
#define LCPLL_CTL _MMIO(0x130040)
#define LCPLL_PLL_DISABLE (1 << 31)
#define LCPLL_PLL_LOCK (1 << 30)
#define LCPLL_REF_NON_SSC (0 << 28)
#define LCPLL_REF_BCLK (2 << 28)
#define LCPLL_REF_PCH_SSC (3 << 28)
#define LCPLL_REF_MASK (3 << 28)
#define LCPLL_CLK_FREQ_MASK (3 << 26)
#define LCPLL_CLK_FREQ_450 (0 << 26)
#define LCPLL_CLK_FREQ_54O_BDW (1 << 26)

16
drivers/gpu/drm/i915/intel_ddi.c
View File

@ -1231,9 +1231,9 @@ static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
u32 wrpll;
wrpll = I915_READ(reg);
switch (wrpll & WRPLL_PLL_REF_MASK) {
case WRPLL_PLL_SSC:
case WRPLL_PLL_NON_SSC:
switch (wrpll & WRPLL_REF_MASK) {
case WRPLL_REF_SPECIAL_HSW:
case WRPLL_REF_PCH_SSC:
/*
* We could calculate spread here, but our checking
* code only cares about 5% accuracy, and spread is a max of
@ -1241,7 +1241,7 @@ static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
*/
refclk = 135;
break;
case WRPLL_PLL_LCPLL:
case WRPLL_REF_LCPLL:
refclk = LC_FREQ;
break;
default:
@ -1613,12 +1613,12 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder,
link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
break;
case PORT_CLK_SEL_SPLL:
pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
if (pll == SPLL_PLL_FREQ_810MHz)
pll = I915_READ(SPLL_CTL) & SPLL_FREQ_MASK;
if (pll == SPLL_FREQ_810MHz)
link_clock = 81000;
else if (pll == SPLL_PLL_FREQ_1350MHz)
else if (pll == SPLL_FREQ_1350MHz)
link_clock = 135000;
else if (pll == SPLL_PLL_FREQ_2700MHz)
else if (pll == SPLL_FREQ_2700MHz)
link_clock = 270000;
else {
WARN(1, "bad spll freq\n");

8
drivers/gpu/drm/i915/intel_display.c
View File

@ -9134,12 +9134,12 @@ static bool spll_uses_pch_ssc(struct drm_i915_private *dev_priv)
if ((ctl & SPLL_PLL_ENABLE) == 0)
return false;
if ((ctl & SPLL_PLL_REF_MASK) == SPLL_PLL_SSC &&
if ((ctl & SPLL_REF_MASK) == SPLL_REF_MUXED_SSC &&
(fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
return true;
if (IS_BROADWELL(dev_priv) &&
(ctl & SPLL_PLL_REF_MASK) == SPLL_PLL_NON_SSC)
(ctl & SPLL_REF_MASK) == SPLL_REF_PCH_SSC_BDW)
return true;
return false;
@ -9154,11 +9154,11 @@ static bool wrpll_uses_pch_ssc(struct drm_i915_private *dev_priv,
if ((ctl & WRPLL_PLL_ENABLE) == 0)
return false;
if ((ctl & WRPLL_PLL_REF_MASK) == WRPLL_PLL_SSC)
if ((ctl & WRPLL_REF_MASK) == WRPLL_REF_PCH_SSC)
return true;
if ((IS_BROADWELL(dev_priv) || IS_HSW_ULT(dev_priv)) &&
(ctl & WRPLL_PLL_REF_MASK) == WRPLL_PLL_NON_SSC &&
(ctl & WRPLL_REF_MASK) == WRPLL_REF_MUXED_SSC_BDW &&
(fuse_strap & HSW_CPU_SSC_ENABLE) == 0)
return true;

4
drivers/gpu/drm/i915/intel_dpll_mgr.c
View File

@ -775,7 +775,7 @@ static struct intel_shared_dpll *hsw_ddi_hdmi_get_dpll(struct intel_crtc_state *
hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p);
val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
val = WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL |
WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
WRPLL_DIVIDER_POST(p);
@ -839,7 +839,7 @@ hsw_get_dpll(struct intel_crtc_state *crtc_state,
return NULL;
crtc_state->dpll_hw_state.spll =
SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC;
SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;
pll = intel_find_shared_dpll(crtc_state,
DPLL_ID_SPLL, DPLL_ID_SPLL);