korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-11-16 08:44:21 +08:00
Code Issues Packages Projects Releases Wiki Activity

ARM: dts: exynos: Add GPU/Mali 400 node to Exynos3250

Browse Source 
Add nodes for GPU (Mali 400) to Exynos3250.  This is still limited and
not tested:
1. No dynamic voltage and frequency scaling,
2. Not sure what to do with CLK_G3D clock responsible for gating entire
   IP block (it is now being disabled as unused).

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Krzysztof Kozlowski 2019-06-21 20:02:02 +02:00
parent 8b388cee66
commit 4a7bc07f5c
4 changed files with 48 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm/boot/dts/exynos3250-artik5.dtsi
View File

@ -59,6 +59,11 @@
cpu0-supply = <&buck2_reg>;
};
&gpu {
mali-supply = <&buck3_reg>;
status = "okay";
};
&i2c_0 {
#address-cells = <1>;
#size-cells = <0>;

5
arch/arm/boot/dts/exynos3250-monk.dts
View File

@ -172,6 +172,11 @@
status = "okay";
};
&gpu {
mali-supply = <&buck3_reg>;
status = "okay";
};
&hsotg {
vusb_d-supply = <&ldo15_reg>;
vusb_a-supply = <&ldo12_reg>;

5
arch/arm/boot/dts/exynos3250-rinato.dts
View File

@ -244,6 +244,11 @@
};
};
&gpu {
mali-supply = <&buck3_reg>;
status = "okay";
};
&i2c_0 {
#address-cells = <1>;
#size-cells = <0>;

33
arch/arm/boot/dts/exynos3250.dtsi
View File

@ -126,6 +126,39 @@
};
};
gpu: gpu@13000000 {
compatible = "samsung,exynos4210-mali", "arm,mali-400";
reg = <0x13000000 0x10000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp",
"gpmmu",
"pp0",
"ppmmu0",
"pp1",
"ppmmu1",
"pp2",
"ppmmu2",
"pp3",
"ppmmu3",
"pmu";
clocks = <&cmu CLK_G3D>,
<&cmu CLK_SCLK_G3D>;
clock-names = "bus", "core";
power-domains = <&pd_g3d>;
status = "disabled";
/* TODO: operating points for DVFS, assigned clock as 134 MHz */
};
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,