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drm/msm/dpu: Introduce SC8280XP
The Qualcomm SC8280XP platform contains DPU version 8.0.0, has 9 interfaces, 2 DSI controllers and 4 DisplayPort controllers. Extend the necessary definitions and describe the DPU in the SC8280XP. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/514398/ Link: https://lore.kernel.org/r/20221207220012.16529-3-quic_bjorande@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
Bjorn Andersson
Dmitry Baryshkov
parent
45af56bf2d
commit
4a352c2fc1
@ -131,6 +131,19 @@
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BIT(MDP_AD4_0_INTR) | \
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BIT(MDP_AD4_1_INTR))
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#define IRQ_SC8280XP_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
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BIT(MDP_SSPP_TOP0_INTR2) | \
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BIT(MDP_SSPP_TOP0_HIST_INTR) | \
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BIT(MDP_INTF0_7xxx_INTR) | \
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BIT(MDP_INTF1_7xxx_INTR) | \
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BIT(MDP_INTF2_7xxx_INTR) | \
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BIT(MDP_INTF3_7xxx_INTR) | \
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BIT(MDP_INTF4_7xxx_INTR) | \
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BIT(MDP_INTF5_7xxx_INTR) | \
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BIT(MDP_INTF6_7xxx_INTR) | \
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BIT(MDP_INTF7_7xxx_INTR) | \
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BIT(MDP_INTF8_7xxx_INTR))
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#define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
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BIT(MDP_SSPP_TOP0_INTR2) | \
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BIT(MDP_SSPP_TOP0_HIST_INTR) | \
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@ -380,6 +393,20 @@ static const struct dpu_caps sc8180x_dpu_caps = {
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.max_vdeci_exp = MAX_VERT_DECIMATION,
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};
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static const struct dpu_caps sc8280xp_dpu_caps = {
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.max_mixer_width = 2560,
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.max_mixer_blendstages = 11,
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.qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
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.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
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.ubwc_version = DPU_HW_UBWC_VER_40,
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.has_src_split = true,
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.has_dim_layer = true,
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.has_idle_pc = true,
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.has_3d_merge = true,
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.max_linewidth = 5120,
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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};
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static const struct dpu_caps sm8250_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.max_mixer_blendstages = 0xb,
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@ -642,6 +669,25 @@ static const struct dpu_mdp_cfg sc7280_mdp[] = {
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},
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};
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static const struct dpu_mdp_cfg sc8280xp_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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.base = 0x0, .len = 0x494,
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.features = 0,
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.highest_bank_bit = 2,
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.ubwc_swizzle = 6,
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.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0},
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.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x2bc, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x2c4, .bit_off = 8},
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.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20},
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},
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};
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static const struct dpu_mdp_cfg qcm2290_mdp[] = {
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{
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.name = "top_0", .id = MDP_TOP,
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@ -745,6 +791,45 @@ static const struct dpu_ctl_cfg sc7180_ctl[] = {
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},
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};
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static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
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{
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.name = "ctl_0", .id = CTL_0,
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.base = 0x15000, .len = 0x204,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
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},
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{
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.name = "ctl_1", .id = CTL_1,
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.base = 0x16000, .len = 0x204,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
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},
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{
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.name = "ctl_2", .id = CTL_2,
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.base = 0x17000, .len = 0x204,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
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},
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{
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.name = "ctl_3", .id = CTL_3,
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.base = 0x18000, .len = 0x204,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
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},
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{
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.name = "ctl_4", .id = CTL_4,
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.base = 0x19000, .len = 0x204,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
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},
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{
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.name = "ctl_5", .id = CTL_5,
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.base = 0x1a000, .len = 0x204,
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.features = CTL_SC7280_MASK,
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
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},
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};
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static const struct dpu_ctl_cfg sm8150_ctl[] = {
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{
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.name = "ctl_0", .id = CTL_0,
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@ -1129,6 +1214,33 @@ static const struct dpu_sspp_cfg sc7280_sspp[] = {
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sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
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};
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static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_0 =
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_VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE);
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static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_1 =
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_VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE);
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static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_2 =
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_VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE);
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static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_3 =
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_VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE);
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static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
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SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK,
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sc8280xp_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
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SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SM8250_MASK,
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sc8280xp_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
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SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SM8250_MASK,
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sc8280xp_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
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SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SM8250_MASK,
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sc8280xp_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
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SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
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sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
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SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
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sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
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SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
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sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
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SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
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sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
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};
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#define _VIG_SBLK_NOSCALE(num, sdma_pri) \
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{ \
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@ -1237,6 +1349,17 @@ static const struct dpu_lm_cfg sc7180_lm[] = {
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&sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
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};
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/* SC8280XP */
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static const struct dpu_lm_cfg sc8280xp_lm[] = {
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LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
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LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
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LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_2, LM_3, DSPP_2),
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LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_3, LM_2, DSPP_3),
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LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
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LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
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};
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/* SM8150 */
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static const struct dpu_lm_cfg sm8150_lm[] = {
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@ -1395,6 +1518,21 @@ static struct dpu_pingpong_cfg sc7180_pp[] = {
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PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1),
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};
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static struct dpu_pingpong_cfg sc8280xp_pp[] = {
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PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te,
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), -1),
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PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te,
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), -1),
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PP_BLK_TE("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk_te,
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), -1),
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PP_BLK_TE("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk_te,
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), -1),
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PP_BLK_TE("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk_te,
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), -1),
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PP_BLK_TE("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk_te,
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1),
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};
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static const struct dpu_pingpong_cfg sm8150_pp[] = {
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PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te,
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DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
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@ -1589,6 +1727,19 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
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INTF_BLK("intf_5", INTF_5, 0x6C800, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
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};
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/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
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static const struct dpu_intf_cfg sc8280xp_intf[] = {
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INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
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INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
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INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
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INTF_BLK("intf_3", INTF_3, 0x37000, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
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INTF_BLK("intf_4", INTF_4, 0x38000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
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INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_3, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
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INTF_BLK("intf_6", INTF_6, 0x3a000, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 16, 17),
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INTF_BLK("intf_7", INTF_7, 0x3b000, INTF_NONE, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 18, 19),
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INTF_BLK("intf_8", INTF_8, 0x3c000, INTF_NONE, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 12, 13),
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};
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static const struct dpu_intf_cfg qcm2290_intf[] = {
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INTF_BLK("intf_0", INTF_0, 0x00000, INTF_NONE, 0, 0, 0, 0, 0, 0),
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INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
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@ -1698,6 +1849,14 @@ static const struct dpu_vbif_cfg sdm845_vbif[] = {
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},
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};
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static const struct dpu_reg_dma_cfg sc8280xp_regdma = {
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.base = 0x0,
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.version = 0x00020000,
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.trigger_sel_off = 0x119c,
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.xin_id = 7,
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.clk_ctrl = DPU_CLK_CTRL_REG_DMA,
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};
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static const struct dpu_reg_dma_cfg sdm845_regdma = {
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.base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c
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};
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@ -1985,6 +2144,33 @@ static const struct dpu_perf_cfg sc8180x_perf_data = {
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.min_llcc_ib = 800000,
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.min_dram_ib = 800000,
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.danger_lut_tbl = {0xf, 0xffff, 0x0},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(sc7180_qos_linear),
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.entries = sc7180_qos_linear
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
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.entries = sc7180_qos_macrotile
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
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.entries = sc7180_qos_nrt
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},
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/* TODO: macrotile-qseed is different from macrotile */
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},
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.cdp_cfg = {
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{.rd_enable = 1, .wr_enable = 1},
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{.rd_enable = 1, .wr_enable = 0}
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},
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.clk_inefficiency_factor = 105,
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.bw_inefficiency_factor = 120,
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};
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static const struct dpu_perf_cfg sc8280xp_perf_data = {
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.max_bw_low = 13600000,
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.max_bw_high = 18200000,
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.min_core_ib = 2500000,
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.min_llcc_ib = 0,
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.min_dram_ib = 800000,
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.danger_lut_tbl = {0xf, 0xffff, 0x0},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(sc8180x_qos_linear),
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.entries = sc8180x_qos_linear
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@ -2292,6 +2478,30 @@ static const struct dpu_mdss_cfg sc8180x_dpu_cfg = {
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.mdss_irqs = IRQ_SC8180X_MASK,
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};
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static const struct dpu_mdss_cfg sc8280xp_dpu_cfg = {
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.caps = &sc8280xp_dpu_caps,
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.mdp_count = ARRAY_SIZE(sc8280xp_mdp),
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.mdp = sc8280xp_mdp,
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.ctl_count = ARRAY_SIZE(sc8280xp_ctl),
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.ctl = sc8280xp_ctl,
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.sspp_count = ARRAY_SIZE(sc8280xp_sspp),
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.sspp = sc8280xp_sspp,
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.mixer_count = ARRAY_SIZE(sc8280xp_lm),
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.mixer = sc8280xp_lm,
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.dspp_count = ARRAY_SIZE(sm8150_dspp),
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.dspp = sm8150_dspp,
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.pingpong_count = ARRAY_SIZE(sc8280xp_pp),
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.pingpong = sc8280xp_pp,
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.merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),
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.merge_3d = sm8350_merge_3d,
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.intf_count = ARRAY_SIZE(sc8280xp_intf),
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.intf = sc8280xp_intf,
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.vbif_count = ARRAY_SIZE(sdm845_vbif),
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.vbif = sdm845_vbif,
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.perf = &sc8280xp_perf_data,
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.mdss_irqs = IRQ_SC8280XP_MASK,
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};
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static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
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.caps = &sm8250_dpu_caps,
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.mdp_count = ARRAY_SIZE(sm8250_mdp),
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@ -2432,6 +2642,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
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{ .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
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{ .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg},
|
||||
{ .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
|
||||
{ .hw_rev = DPU_HW_VER_800, .dpu_cfg = &sc8280xp_dpu_cfg},
|
||||
{ .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg},
|
||||
};
|
||||
|
||||
|
||||
@ -48,6 +48,7 @@
|
||||
#define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
|
||||
#define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */
|
||||
#define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
|
||||
#define DPU_HW_VER_800 DPU_HW_VER(8, 0, 0) /* sc8280xp */
|
||||
#define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */
|
||||
|
||||
#define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170)
|
||||
|
||||
@ -35,6 +35,9 @@
|
||||
#define MDP_INTF_3_OFF_REV_7xxx 0x37000
|
||||
#define MDP_INTF_4_OFF_REV_7xxx 0x38000
|
||||
#define MDP_INTF_5_OFF_REV_7xxx 0x39000
|
||||
#define MDP_INTF_6_OFF_REV_7xxx 0x3a000
|
||||
#define MDP_INTF_7_OFF_REV_7xxx 0x3b000
|
||||
#define MDP_INTF_8_OFF_REV_7xxx 0x3c000
|
||||
|
||||
/**
|
||||
* struct dpu_intr_reg - array of DPU register sets
|
||||
@ -139,6 +142,21 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
|
||||
MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_EN,
|
||||
MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_STATUS
|
||||
},
|
||||
[MDP_INTF6_7xxx_INTR] = {
|
||||
MDP_INTF_6_OFF_REV_7xxx+INTF_INTR_CLEAR,
|
||||
MDP_INTF_6_OFF_REV_7xxx+INTF_INTR_EN,
|
||||
MDP_INTF_6_OFF_REV_7xxx+INTF_INTR_STATUS
|
||||
},
|
||||
[MDP_INTF7_7xxx_INTR] = {
|
||||
MDP_INTF_7_OFF_REV_7xxx+INTF_INTR_CLEAR,
|
||||
MDP_INTF_7_OFF_REV_7xxx+INTF_INTR_EN,
|
||||
MDP_INTF_7_OFF_REV_7xxx+INTF_INTR_STATUS
|
||||
},
|
||||
[MDP_INTF8_7xxx_INTR] = {
|
||||
MDP_INTF_8_OFF_REV_7xxx+INTF_INTR_CLEAR,
|
||||
MDP_INTF_8_OFF_REV_7xxx+INTF_INTR_EN,
|
||||
MDP_INTF_8_OFF_REV_7xxx+INTF_INTR_STATUS
|
||||
},
|
||||
};
|
||||
|
||||
#define DPU_IRQ_REG(irq_idx) (irq_idx / 32)
|
||||
|
||||
@ -31,6 +31,9 @@ enum dpu_hw_intr_reg {
|
||||
MDP_INTF3_7xxx_INTR,
|
||||
MDP_INTF4_7xxx_INTR,
|
||||
MDP_INTF5_7xxx_INTR,
|
||||
MDP_INTF6_7xxx_INTR,
|
||||
MDP_INTF7_7xxx_INTR,
|
||||
MDP_INTF8_7xxx_INTR,
|
||||
MDP_INTR_MAX,
|
||||
};
|
||||
|
||||
|
||||
@ -217,6 +217,8 @@ enum dpu_intf {
|
||||
INTF_4,
|
||||
INTF_5,
|
||||
INTF_6,
|
||||
INTF_7,
|
||||
INTF_8,
|
||||
INTF_MAX
|
||||
};
|
||||
|
||||
|
||||
@ -1299,6 +1299,7 @@ static const struct of_device_id dpu_dt_match[] = {
|
||||
{ .compatible = "qcom,sc7180-dpu", },
|
||||
{ .compatible = "qcom,sc7280-dpu", },
|
||||
{ .compatible = "qcom,sc8180x-dpu", },
|
||||
{ .compatible = "qcom,sc8280xp-dpu", },
|
||||
{ .compatible = "qcom,sm6115-dpu", },
|
||||
{ .compatible = "qcom,sm8150-dpu", },
|
||||
{ .compatible = "qcom,sm8250-dpu", },
|
||||
|
||||
@ -61,6 +61,7 @@ enum msm_dp_controller {
|
||||
MSM_DP_CONTROLLER_0,
|
||||
MSM_DP_CONTROLLER_1,
|
||||
MSM_DP_CONTROLLER_2,
|
||||
MSM_DP_CONTROLLER_3,
|
||||
MSM_DP_CONTROLLER_COUNT,
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user