mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
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Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (26 commits) sh: Convert sh to use read/update_persistent_clock sh: Move PMB debugfs entry initialization to later stage sh: Fix up flush_cache_vmap() on SMP. sh: fix up MMU reset with variable PMB mapping sizes. sh: establish PMB mappings for NUMA nodes. sh: check for existing mappings for bolted PMB entries. sh: fixed virt/phys mapping helpers for PMB. sh: make pmb iomapping configurable. sh: reworked dynamic PMB mapping. sh: Fix up cpumask_of_pcibus() for the NUMA build. serial: sh-sci: Tidy up build warnings. sh: Fix up ctrl_read/write stragglers in migor setup. serial: sh-sci: Add DMA support. dmaengine: shdma: extend .device_terminate_all() to record partial transfer sh: merge sh7722 and sh7724 DMA register definitions sh: activate runtime PM for dmaengine on sh7722 and sh7724 dmaengine: shdma: add runtime PM support. dmaengine: shdma: separate DMA headers. dmaengine: shdma: convert to platform device resources dmaengine: shdma: fix DMA error handling. ...
This commit is contained in:
commit
4a31c08d2f
@ -419,6 +419,9 @@ static struct i2c_board_info migor_i2c_devices[] = {
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I2C_BOARD_INFO("migor_ts", 0x51),
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.irq = 38, /* IRQ6 */
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},
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{
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I2C_BOARD_INFO("wm8978", 0x1a),
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},
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};
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static struct i2c_board_info migor_i2c_camera[] = {
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@ -619,6 +622,19 @@ static int __init migor_devices_setup(void)
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platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);
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/* SIU: Port B */
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gpio_request(GPIO_FN_SIUBOLR, NULL);
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gpio_request(GPIO_FN_SIUBOBT, NULL);
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gpio_request(GPIO_FN_SIUBISLD, NULL);
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gpio_request(GPIO_FN_SIUBOSLD, NULL);
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gpio_request(GPIO_FN_SIUMCKB, NULL);
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/*
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* The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
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* output. Need only SIUB, set to output for master mode (table 34.2)
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*/
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__raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA);
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i2c_register_board_info(0, migor_i2c_devices,
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ARRAY_SIZE(migor_i2c_devices));
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@ -5,7 +5,7 @@ int cache_control(unsigned int command)
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for (i = 0; i < (32 * 1024); i += 32) {
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(void)*p;
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p += (32 / sizeof (int));
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p += (32 / sizeof(int));
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}
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return 0;
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@ -86,8 +86,8 @@ extern void copy_from_user_page(struct vm_area_struct *vma,
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struct page *page, unsigned long vaddr, void *dst, const void *src,
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unsigned long len);
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#define flush_cache_vmap(start, end) flush_cache_all()
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#define flush_cache_vunmap(start, end) flush_cache_all()
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#define flush_cache_vmap(start, end) local_flush_cache_all(NULL)
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#define flush_cache_vunmap(start, end) local_flush_cache_all(NULL)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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|
51
arch/sh/include/asm/dma-register.h
Normal file
51
arch/sh/include/asm/dma-register.h
Normal file
@ -0,0 +1,51 @@
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/*
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* Common header for the legacy SH DMA driver and the new dmaengine driver
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*
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* extracted from arch/sh/include/asm/dma-sh.h:
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*
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* Copyright (C) 2000 Takashi YOSHII
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* Copyright (C) 2003 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef DMA_REGISTER_H
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#define DMA_REGISTER_H
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/* DMA register */
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#define SAR 0x00
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#define DAR 0x04
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#define TCR 0x08
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#define CHCR 0x0C
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#define DMAOR 0x40
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/* DMAOR definitions */
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#define DMAOR_AE 0x00000004
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#define DMAOR_NMIF 0x00000002
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#define DMAOR_DME 0x00000001
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/* Definitions for the SuperH DMAC */
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#define REQ_L 0x00000000
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#define REQ_E 0x00080000
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#define RACK_H 0x00000000
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#define RACK_L 0x00040000
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#define ACK_R 0x00000000
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#define ACK_W 0x00020000
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#define ACK_H 0x00000000
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#define ACK_L 0x00010000
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#define DM_INC 0x00004000
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#define DM_DEC 0x00008000
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#define DM_FIX 0x0000c000
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#define SM_INC 0x00001000
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#define SM_DEC 0x00002000
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#define SM_FIX 0x00003000
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#define RS_IN 0x00000200
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#define RS_OUT 0x00000300
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#define TS_BLK 0x00000040
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#define TM_BUR 0x00000020
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#define CHCR_DE 0x00000001
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#define CHCR_TE 0x00000002
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#define CHCR_IE 0x00000004
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#endif
|
@ -11,7 +11,8 @@
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#ifndef __DMA_SH_H
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#define __DMA_SH_H
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#include <asm/dma.h>
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#include <asm/dma-register.h>
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#include <cpu/dma-register.h>
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#include <cpu/dma.h>
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/* DMAOR contorl: The DMAOR access size is different by CPU.*/
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@ -53,34 +54,6 @@ static int dmte_irq_map[] __maybe_unused = {
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#endif
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};
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/* Definitions for the SuperH DMAC */
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#define REQ_L 0x00000000
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#define REQ_E 0x00080000
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#define RACK_H 0x00000000
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#define RACK_L 0x00040000
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#define ACK_R 0x00000000
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#define ACK_W 0x00020000
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#define ACK_H 0x00000000
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#define ACK_L 0x00010000
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#define DM_INC 0x00004000
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#define DM_DEC 0x00008000
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#define DM_FIX 0x0000c000
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#define SM_INC 0x00001000
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#define SM_DEC 0x00002000
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#define SM_FIX 0x00003000
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#define RS_IN 0x00000200
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#define RS_OUT 0x00000300
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#define TS_BLK 0x00000040
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#define TM_BUR 0x00000020
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#define CHCR_DE 0x00000001
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#define CHCR_TE 0x00000002
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#define CHCR_IE 0x00000004
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/* DMAOR definitions */
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#define DMAOR_AE 0x00000004
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#define DMAOR_NMIF 0x00000002
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#define DMAOR_DME 0x00000001
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/*
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* Define the default configuration for dual address memory-memory transfer.
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* The 0x400 value represents auto-request, external->external.
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@ -111,61 +84,4 @@ static u32 dma_base_addr[] __maybe_unused = {
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#endif
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};
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/* DMA register */
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#define SAR 0x00
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#define DAR 0x04
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#define TCR 0x08
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#define CHCR 0x0C
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#define DMAOR 0x40
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/*
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* for dma engine
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*
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* SuperH DMA mode
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*/
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#define SHDMA_MIX_IRQ (1 << 1)
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#define SHDMA_DMAOR1 (1 << 2)
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#define SHDMA_DMAE1 (1 << 3)
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enum sh_dmae_slave_chan_id {
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SHDMA_SLAVE_SCIF0_TX,
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SHDMA_SLAVE_SCIF0_RX,
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SHDMA_SLAVE_SCIF1_TX,
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SHDMA_SLAVE_SCIF1_RX,
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SHDMA_SLAVE_SCIF2_TX,
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SHDMA_SLAVE_SCIF2_RX,
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SHDMA_SLAVE_SCIF3_TX,
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SHDMA_SLAVE_SCIF3_RX,
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SHDMA_SLAVE_SCIF4_TX,
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SHDMA_SLAVE_SCIF4_RX,
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SHDMA_SLAVE_SCIF5_TX,
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SHDMA_SLAVE_SCIF5_RX,
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SHDMA_SLAVE_SIUA_TX,
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SHDMA_SLAVE_SIUA_RX,
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SHDMA_SLAVE_SIUB_TX,
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SHDMA_SLAVE_SIUB_RX,
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SHDMA_SLAVE_NUMBER, /* Must stay last */
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};
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struct sh_dmae_slave_config {
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enum sh_dmae_slave_chan_id slave_id;
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dma_addr_t addr;
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u32 chcr;
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char mid_rid;
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};
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struct sh_dmae_pdata {
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unsigned int mode;
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struct sh_dmae_slave_config *config;
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int config_num;
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};
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struct device;
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struct sh_dmae_slave {
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enum sh_dmae_slave_chan_id slave_id; /* Set by the platform */
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struct device *dma_dev; /* Set by the platform */
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struct sh_dmae_slave_config *config; /* Set by the driver */
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};
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#endif /* __DMA_SH_H */
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|
93
arch/sh/include/asm/dmaengine.h
Normal file
93
arch/sh/include/asm/dmaengine.h
Normal file
@ -0,0 +1,93 @@
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/*
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* Header for the new SH dmaengine driver
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*
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* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef ASM_DMAENGINE_H
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#define ASM_DMAENGINE_H
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#include <linux/dmaengine.h>
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#include <linux/list.h>
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#include <asm/dma-register.h>
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#define SH_DMAC_MAX_CHANNELS 6
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enum sh_dmae_slave_chan_id {
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SHDMA_SLAVE_SCIF0_TX,
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SHDMA_SLAVE_SCIF0_RX,
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SHDMA_SLAVE_SCIF1_TX,
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SHDMA_SLAVE_SCIF1_RX,
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SHDMA_SLAVE_SCIF2_TX,
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SHDMA_SLAVE_SCIF2_RX,
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SHDMA_SLAVE_SCIF3_TX,
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SHDMA_SLAVE_SCIF3_RX,
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SHDMA_SLAVE_SCIF4_TX,
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SHDMA_SLAVE_SCIF4_RX,
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SHDMA_SLAVE_SCIF5_TX,
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SHDMA_SLAVE_SCIF5_RX,
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SHDMA_SLAVE_SIUA_TX,
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SHDMA_SLAVE_SIUA_RX,
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SHDMA_SLAVE_SIUB_TX,
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SHDMA_SLAVE_SIUB_RX,
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SHDMA_SLAVE_NUMBER, /* Must stay last */
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};
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struct sh_dmae_slave_config {
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enum sh_dmae_slave_chan_id slave_id;
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dma_addr_t addr;
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u32 chcr;
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char mid_rid;
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};
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struct sh_dmae_channel {
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unsigned int offset;
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unsigned int dmars;
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unsigned int dmars_bit;
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};
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struct sh_dmae_pdata {
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struct sh_dmae_slave_config *slave;
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int slave_num;
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struct sh_dmae_channel *channel;
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int channel_num;
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unsigned int ts_low_shift;
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unsigned int ts_low_mask;
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unsigned int ts_high_shift;
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unsigned int ts_high_mask;
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unsigned int *ts_shift;
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int ts_shift_num;
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u16 dmaor_init;
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};
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struct device;
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/* Used by slave DMA clients to request DMA to/from a specific peripheral */
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struct sh_dmae_slave {
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enum sh_dmae_slave_chan_id slave_id; /* Set by the platform */
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struct device *dma_dev; /* Set by the platform */
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struct sh_dmae_slave_config *config; /* Set by the driver */
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};
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struct sh_dmae_regs {
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u32 sar; /* SAR / source address */
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u32 dar; /* DAR / destination address */
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u32 tcr; /* TCR / transfer count */
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||||
};
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struct sh_desc {
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struct sh_dmae_regs hw;
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struct list_head node;
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struct dma_async_tx_descriptor async_tx;
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enum dma_data_direction direction;
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dma_cookie_t cookie;
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size_t partial;
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int chunks;
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||||
int mark;
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||||
};
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||||
|
||||
#endif
|
@ -291,21 +291,21 @@ unsigned long long poke_real_address_q(unsigned long long addr,
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* doesn't exist, so everything must go through page tables.
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||||
*/
|
||||
#ifdef CONFIG_MMU
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void __iomem *__ioremap_caller(unsigned long offset, unsigned long size,
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||||
void __iomem *__ioremap_caller(phys_addr_t offset, unsigned long size,
|
||||
pgprot_t prot, void *caller);
|
||||
void __iounmap(void __iomem *addr);
|
||||
|
||||
static inline void __iomem *
|
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__ioremap(unsigned long offset, unsigned long size, pgprot_t prot)
|
||||
__ioremap(phys_addr_t offset, unsigned long size, pgprot_t prot)
|
||||
{
|
||||
return __ioremap_caller(offset, size, prot, __builtin_return_address(0));
|
||||
}
|
||||
|
||||
static inline void __iomem *
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||||
__ioremap_29bit(unsigned long offset, unsigned long size, pgprot_t prot)
|
||||
__ioremap_29bit(phys_addr_t offset, unsigned long size, pgprot_t prot)
|
||||
{
|
||||
#ifdef CONFIG_29BIT
|
||||
unsigned long last_addr = offset + size - 1;
|
||||
phys_addr_t last_addr = offset + size - 1;
|
||||
|
||||
/*
|
||||
* For P1 and P2 space this is trivial, as everything is already
|
||||
@ -329,7 +329,7 @@ __ioremap_29bit(unsigned long offset, unsigned long size, pgprot_t prot)
|
||||
}
|
||||
|
||||
static inline void __iomem *
|
||||
__ioremap_mode(unsigned long offset, unsigned long size, pgprot_t prot)
|
||||
__ioremap_mode(phys_addr_t offset, unsigned long size, pgprot_t prot)
|
||||
{
|
||||
void __iomem *ret;
|
||||
|
||||
@ -349,35 +349,32 @@ __ioremap_mode(unsigned long offset, unsigned long size, pgprot_t prot)
|
||||
#define __iounmap(addr) do { } while (0)
|
||||
#endif /* CONFIG_MMU */
|
||||
|
||||
static inline void __iomem *
|
||||
ioremap(unsigned long offset, unsigned long size)
|
||||
static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
|
||||
{
|
||||
return __ioremap_mode(offset, size, PAGE_KERNEL_NOCACHE);
|
||||
}
|
||||
|
||||
static inline void __iomem *
|
||||
ioremap_cache(unsigned long offset, unsigned long size)
|
||||
ioremap_cache(phys_addr_t offset, unsigned long size)
|
||||
{
|
||||
return __ioremap_mode(offset, size, PAGE_KERNEL);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HAVE_IOREMAP_PROT
|
||||
static inline void __iomem *
|
||||
ioremap_prot(resource_size_t offset, unsigned long size, unsigned long flags)
|
||||
ioremap_prot(phys_addr_t offset, unsigned long size, unsigned long flags)
|
||||
{
|
||||
return __ioremap_mode(offset, size, __pgprot(flags));
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_IOREMAP_FIXED
|
||||
extern void __iomem *ioremap_fixed(resource_size_t, unsigned long,
|
||||
unsigned long, pgprot_t);
|
||||
extern void __iomem *ioremap_fixed(phys_addr_t, unsigned long, pgprot_t);
|
||||
extern int iounmap_fixed(void __iomem *);
|
||||
extern void ioremap_fixed_init(void);
|
||||
#else
|
||||
static inline void __iomem *
|
||||
ioremap_fixed(resource_size_t phys_addr, unsigned long offset,
|
||||
unsigned long size, pgprot_t prot)
|
||||
ioremap_fixed(phys_addr_t phys_addr, unsigned long size, pgprot_t prot)
|
||||
{
|
||||
BUG();
|
||||
return NULL;
|
||||
|
@ -55,19 +55,29 @@ typedef struct {
|
||||
|
||||
#ifdef CONFIG_PMB
|
||||
/* arch/sh/mm/pmb.c */
|
||||
long pmb_remap(unsigned long virt, unsigned long phys,
|
||||
unsigned long size, pgprot_t prot);
|
||||
void pmb_unmap(unsigned long addr);
|
||||
void pmb_init(void);
|
||||
bool __in_29bit_mode(void);
|
||||
|
||||
void pmb_init(void);
|
||||
int pmb_bolt_mapping(unsigned long virt, phys_addr_t phys,
|
||||
unsigned long size, pgprot_t prot);
|
||||
void __iomem *pmb_remap_caller(phys_addr_t phys, unsigned long size,
|
||||
pgprot_t prot, void *caller);
|
||||
int pmb_unmap(void __iomem *addr);
|
||||
|
||||
#else
|
||||
static inline long pmb_remap(unsigned long virt, unsigned long phys,
|
||||
unsigned long size, pgprot_t prot)
|
||||
|
||||
static inline void __iomem *
|
||||
pmb_remap_caller(phys_addr_t phys, unsigned long size,
|
||||
pgprot_t prot, void *caller)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static inline int pmb_unmap(void __iomem *addr)
|
||||
{
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
#define pmb_unmap(addr) do { } while (0)
|
||||
#define pmb_init(addr) do { } while (0)
|
||||
|
||||
#ifdef CONFIG_29BIT
|
||||
@ -77,6 +87,13 @@ static inline long pmb_remap(unsigned long virt, unsigned long phys,
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_PMB */
|
||||
|
||||
static inline void __iomem *
|
||||
pmb_remap(phys_addr_t phys, unsigned long size, pgprot_t prot)
|
||||
{
|
||||
return pmb_remap_caller(phys, size, prot, __builtin_return_address(0));
|
||||
}
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __MMU_H */
|
||||
|
@ -11,7 +11,7 @@
|
||||
#ifndef ASM_SIU_H
|
||||
#define ASM_SIU_H
|
||||
|
||||
#include <asm/dma-sh.h>
|
||||
#include <asm/dmaengine.h>
|
||||
|
||||
struct device;
|
||||
|
||||
|
@ -35,7 +35,7 @@
|
||||
|
||||
#define pcibus_to_node(bus) ((void)(bus), -1)
|
||||
#define cpumask_of_pcibus(bus) (pcibus_to_node(bus) == -1 ? \
|
||||
CPU_MASK_ALL_PTR : \
|
||||
cpu_all_mask : \
|
||||
cpumask_of_node(pcibus_to_node(bus)))
|
||||
|
||||
#endif
|
||||
|
41
arch/sh/include/cpu-sh3/cpu/dma-register.h
Normal file
41
arch/sh/include/cpu-sh3/cpu/dma-register.h
Normal file
@ -0,0 +1,41 @@
|
||||
/*
|
||||
* SH3 CPU-specific DMA definitions, used by both DMA drivers
|
||||
*
|
||||
* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef CPU_DMA_REGISTER_H
|
||||
#define CPU_DMA_REGISTER_H
|
||||
|
||||
#define CHCR_TS_LOW_MASK 0x18
|
||||
#define CHCR_TS_LOW_SHIFT 3
|
||||
#define CHCR_TS_HIGH_MASK 0
|
||||
#define CHCR_TS_HIGH_SHIFT 0
|
||||
|
||||
#define DMAOR_INIT DMAOR_DME
|
||||
|
||||
/*
|
||||
* The SuperH DMAC supports a number of transmit sizes, we list them here,
|
||||
* with their respective values as they appear in the CHCR registers.
|
||||
*/
|
||||
enum {
|
||||
XMIT_SZ_8BIT,
|
||||
XMIT_SZ_16BIT,
|
||||
XMIT_SZ_32BIT,
|
||||
XMIT_SZ_128BIT,
|
||||
};
|
||||
|
||||
/* log2(size / 8) - used to calculate number of transfers */
|
||||
#define TS_SHIFT { \
|
||||
[XMIT_SZ_8BIT] = 0, \
|
||||
[XMIT_SZ_16BIT] = 1, \
|
||||
[XMIT_SZ_32BIT] = 2, \
|
||||
[XMIT_SZ_128BIT] = 4, \
|
||||
}
|
||||
|
||||
#define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT)
|
||||
|
||||
#endif
|
@ -20,31 +20,4 @@
|
||||
#define TS_32 0x00000010
|
||||
#define TS_128 0x00000018
|
||||
|
||||
#define CHCR_TS_LOW_MASK 0x18
|
||||
#define CHCR_TS_LOW_SHIFT 3
|
||||
#define CHCR_TS_HIGH_MASK 0
|
||||
#define CHCR_TS_HIGH_SHIFT 0
|
||||
|
||||
#define DMAOR_INIT DMAOR_DME
|
||||
|
||||
/*
|
||||
* The SuperH DMAC supports a number of transmit sizes, we list them here,
|
||||
* with their respective values as they appear in the CHCR registers.
|
||||
*/
|
||||
enum {
|
||||
XMIT_SZ_8BIT,
|
||||
XMIT_SZ_16BIT,
|
||||
XMIT_SZ_32BIT,
|
||||
XMIT_SZ_128BIT,
|
||||
};
|
||||
|
||||
#define TS_SHIFT { \
|
||||
[XMIT_SZ_8BIT] = 0, \
|
||||
[XMIT_SZ_16BIT] = 1, \
|
||||
[XMIT_SZ_32BIT] = 2, \
|
||||
[XMIT_SZ_128BIT] = 4, \
|
||||
}
|
||||
|
||||
#define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT)
|
||||
|
||||
#endif /* __ASM_CPU_SH3_DMA_H */
|
||||
|
112
arch/sh/include/cpu-sh4/cpu/dma-register.h
Normal file
112
arch/sh/include/cpu-sh4/cpu/dma-register.h
Normal file
@ -0,0 +1,112 @@
|
||||
/*
|
||||
* SH4 CPU-specific DMA definitions, used by both DMA drivers
|
||||
*
|
||||
* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef CPU_DMA_REGISTER_H
|
||||
#define CPU_DMA_REGISTER_H
|
||||
|
||||
/* SH7751/7760/7780 DMA IRQ sources */
|
||||
|
||||
#ifdef CONFIG_CPU_SH4A
|
||||
|
||||
#define DMAOR_INIT DMAOR_DME
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7730)
|
||||
#define CHCR_TS_LOW_MASK 0x00000018
|
||||
#define CHCR_TS_LOW_SHIFT 3
|
||||
#define CHCR_TS_HIGH_MASK 0
|
||||
#define CHCR_TS_HIGH_SHIFT 0
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7722) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7724)
|
||||
#define CHCR_TS_LOW_MASK 0x00000018
|
||||
#define CHCR_TS_LOW_SHIFT 3
|
||||
#define CHCR_TS_HIGH_MASK 0x00300000
|
||||
#define CHCR_TS_HIGH_SHIFT (20 - 2) /* 2 bits for shifted low TS */
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7764)
|
||||
#define CHCR_TS_LOW_MASK 0x00000018
|
||||
#define CHCR_TS_LOW_SHIFT 3
|
||||
#define CHCR_TS_HIGH_MASK 0
|
||||
#define CHCR_TS_HIGH_SHIFT 0
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
|
||||
#define CHCR_TS_LOW_MASK 0x00000018
|
||||
#define CHCR_TS_LOW_SHIFT 3
|
||||
#define CHCR_TS_HIGH_MASK 0
|
||||
#define CHCR_TS_HIGH_SHIFT 0
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
#define CHCR_TS_LOW_MASK 0x00000018
|
||||
#define CHCR_TS_LOW_SHIFT 3
|
||||
#define CHCR_TS_HIGH_MASK 0
|
||||
#define CHCR_TS_HIGH_SHIFT 0
|
||||
#else /* SH7785 */
|
||||
#define CHCR_TS_LOW_MASK 0x00000018
|
||||
#define CHCR_TS_LOW_SHIFT 3
|
||||
#define CHCR_TS_HIGH_MASK 0
|
||||
#define CHCR_TS_HIGH_SHIFT 0
|
||||
#endif
|
||||
|
||||
/* Transmit sizes and respective CHCR register values */
|
||||
enum {
|
||||
XMIT_SZ_8BIT = 0,
|
||||
XMIT_SZ_16BIT = 1,
|
||||
XMIT_SZ_32BIT = 2,
|
||||
XMIT_SZ_64BIT = 7,
|
||||
XMIT_SZ_128BIT = 3,
|
||||
XMIT_SZ_256BIT = 4,
|
||||
XMIT_SZ_128BIT_BLK = 0xb,
|
||||
XMIT_SZ_256BIT_BLK = 0xc,
|
||||
};
|
||||
|
||||
/* log2(size / 8) - used to calculate number of transfers */
|
||||
#define TS_SHIFT { \
|
||||
[XMIT_SZ_8BIT] = 0, \
|
||||
[XMIT_SZ_16BIT] = 1, \
|
||||
[XMIT_SZ_32BIT] = 2, \
|
||||
[XMIT_SZ_64BIT] = 3, \
|
||||
[XMIT_SZ_128BIT] = 4, \
|
||||
[XMIT_SZ_256BIT] = 5, \
|
||||
[XMIT_SZ_128BIT_BLK] = 4, \
|
||||
[XMIT_SZ_256BIT_BLK] = 5, \
|
||||
}
|
||||
|
||||
#define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \
|
||||
((((i) >> 2) & 3) << CHCR_TS_HIGH_SHIFT))
|
||||
|
||||
#else /* CONFIG_CPU_SH4A */
|
||||
|
||||
#define DMAOR_INIT (0x8000 | DMAOR_DME)
|
||||
|
||||
#define CHCR_TS_LOW_MASK 0x70
|
||||
#define CHCR_TS_LOW_SHIFT 4
|
||||
#define CHCR_TS_HIGH_MASK 0
|
||||
#define CHCR_TS_HIGH_SHIFT 0
|
||||
|
||||
/* Transmit sizes and respective CHCR register values */
|
||||
enum {
|
||||
XMIT_SZ_8BIT = 1,
|
||||
XMIT_SZ_16BIT = 2,
|
||||
XMIT_SZ_32BIT = 3,
|
||||
XMIT_SZ_64BIT = 0,
|
||||
XMIT_SZ_256BIT = 4,
|
||||
};
|
||||
|
||||
/* log2(size / 8) - used to calculate number of transfers */
|
||||
#define TS_SHIFT { \
|
||||
[XMIT_SZ_8BIT] = 0, \
|
||||
[XMIT_SZ_16BIT] = 1, \
|
||||
[XMIT_SZ_32BIT] = 2, \
|
||||
[XMIT_SZ_64BIT] = 3, \
|
||||
[XMIT_SZ_256BIT] = 5, \
|
||||
}
|
||||
|
||||
#define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT)
|
||||
|
||||
#endif /* CONFIG_CPU_SH4A */
|
||||
|
||||
#endif
|
@ -8,20 +8,12 @@
|
||||
#define DMAE0_IRQ 78 /* DMA Error IRQ*/
|
||||
#define SH_DMAC_BASE0 0xFE008020
|
||||
#define SH_DMARS_BASE0 0xFE009000
|
||||
#define CHCR_TS_LOW_MASK 0x00000018
|
||||
#define CHCR_TS_LOW_SHIFT 3
|
||||
#define CHCR_TS_HIGH_MASK 0
|
||||
#define CHCR_TS_HIGH_SHIFT 0
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
|
||||
#define DMTE0_IRQ 48
|
||||
#define DMTE4_IRQ 76
|
||||
#define DMAE0_IRQ 78 /* DMA Error IRQ*/
|
||||
#define SH_DMAC_BASE0 0xFE008020
|
||||
#define SH_DMARS_BASE0 0xFE009000
|
||||
#define CHCR_TS_LOW_MASK 0x00000018
|
||||
#define CHCR_TS_LOW_SHIFT 3
|
||||
#define CHCR_TS_HIGH_MASK 0x00300000
|
||||
#define CHCR_TS_HIGH_SHIFT 20
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7764)
|
||||
#define DMTE0_IRQ 34
|
||||
@ -29,10 +21,6 @@
|
||||
#define DMAE0_IRQ 38
|
||||
#define SH_DMAC_BASE0 0xFF608020
|
||||
#define SH_DMARS_BASE0 0xFF609000
|
||||
#define CHCR_TS_LOW_MASK 0x00000018
|
||||
#define CHCR_TS_LOW_SHIFT 3
|
||||
#define CHCR_TS_HIGH_MASK 0
|
||||
#define CHCR_TS_HIGH_SHIFT 0
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
|
||||
#define DMTE0_IRQ 48 /* DMAC0A*/
|
||||
#define DMTE4_IRQ 76 /* DMAC0B */
|
||||
@ -46,10 +34,6 @@
|
||||
#define SH_DMAC_BASE0 0xFE008020
|
||||
#define SH_DMAC_BASE1 0xFDC08020
|
||||
#define SH_DMARS_BASE0 0xFDC09000
|
||||
#define CHCR_TS_LOW_MASK 0x00000018
|
||||
#define CHCR_TS_LOW_SHIFT 3
|
||||
#define CHCR_TS_HIGH_MASK 0
|
||||
#define CHCR_TS_HIGH_SHIFT 0
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
|
||||
#define DMTE0_IRQ 48 /* DMAC0A*/
|
||||
#define DMTE4_IRQ 76 /* DMAC0B */
|
||||
@ -64,10 +48,6 @@
|
||||
#define SH_DMAC_BASE1 0xFDC08020
|
||||
#define SH_DMARS_BASE0 0xFE009000
|
||||
#define SH_DMARS_BASE1 0xFDC09000
|
||||
#define CHCR_TS_LOW_MASK 0x00000018
|
||||
#define CHCR_TS_LOW_SHIFT 3
|
||||
#define CHCR_TS_HIGH_MASK 0x00600000
|
||||
#define CHCR_TS_HIGH_SHIFT 21
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
#define DMTE0_IRQ 34
|
||||
#define DMTE4_IRQ 44
|
||||
@ -80,10 +60,6 @@
|
||||
#define SH_DMAC_BASE0 0xFC808020
|
||||
#define SH_DMAC_BASE1 0xFC818020
|
||||
#define SH_DMARS_BASE0 0xFC809000
|
||||
#define CHCR_TS_LOW_MASK 0x00000018
|
||||
#define CHCR_TS_LOW_SHIFT 3
|
||||
#define CHCR_TS_HIGH_MASK 0
|
||||
#define CHCR_TS_HIGH_SHIFT 0
|
||||
#else /* SH7785 */
|
||||
#define DMTE0_IRQ 33
|
||||
#define DMTE4_IRQ 37
|
||||
@ -97,10 +73,6 @@
|
||||
#define SH_DMAC_BASE0 0xFC808020
|
||||
#define SH_DMAC_BASE1 0xFCC08020
|
||||
#define SH_DMARS_BASE0 0xFC809000
|
||||
#define CHCR_TS_LOW_MASK 0x00000018
|
||||
#define CHCR_TS_LOW_SHIFT 3
|
||||
#define CHCR_TS_HIGH_MASK 0
|
||||
#define CHCR_TS_HIGH_SHIFT 0
|
||||
#endif
|
||||
|
||||
#define REQ_HE 0x000000C0
|
||||
@ -108,38 +80,4 @@
|
||||
#define REQ_LE 0x00000040
|
||||
#define TM_BURST 0x00000020
|
||||
|
||||
/*
|
||||
* The SuperH DMAC supports a number of transmit sizes, we list them here,
|
||||
* with their respective values as they appear in the CHCR registers.
|
||||
*
|
||||
* Defaults to a 64-bit transfer size.
|
||||
*/
|
||||
enum {
|
||||
XMIT_SZ_8BIT = 0,
|
||||
XMIT_SZ_16BIT = 1,
|
||||
XMIT_SZ_32BIT = 2,
|
||||
XMIT_SZ_64BIT = 7,
|
||||
XMIT_SZ_128BIT = 3,
|
||||
XMIT_SZ_256BIT = 4,
|
||||
XMIT_SZ_128BIT_BLK = 0xb,
|
||||
XMIT_SZ_256BIT_BLK = 0xc,
|
||||
};
|
||||
|
||||
/*
|
||||
* The DMA count is defined as the number of bytes to transfer.
|
||||
*/
|
||||
#define TS_SHIFT { \
|
||||
[XMIT_SZ_8BIT] = 0, \
|
||||
[XMIT_SZ_16BIT] = 1, \
|
||||
[XMIT_SZ_32BIT] = 2, \
|
||||
[XMIT_SZ_64BIT] = 3, \
|
||||
[XMIT_SZ_128BIT] = 4, \
|
||||
[XMIT_SZ_256BIT] = 5, \
|
||||
[XMIT_SZ_128BIT_BLK] = 4, \
|
||||
[XMIT_SZ_256BIT_BLK] = 5, \
|
||||
}
|
||||
|
||||
#define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \
|
||||
((((i) >> 2) & 3) << CHCR_TS_HIGH_SHIFT))
|
||||
|
||||
#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
|
||||
|
@ -5,9 +5,8 @@
|
||||
|
||||
#ifdef CONFIG_CPU_SH4A
|
||||
|
||||
#define DMAOR_INIT (DMAOR_DME)
|
||||
|
||||
#include <cpu/dma-sh4a.h>
|
||||
|
||||
#else /* CONFIG_CPU_SH4A */
|
||||
/*
|
||||
* SH7750/SH7751/SH7760
|
||||
@ -17,7 +16,6 @@
|
||||
#define DMTE6_IRQ 46
|
||||
#define DMAE0_IRQ 38
|
||||
|
||||
#define DMAOR_INIT (0x8000|DMAOR_DME)
|
||||
#define SH_DMAC_BASE0 0xffa00000
|
||||
#define SH_DMAC_BASE1 0xffa00070
|
||||
/* Definitions for the SuperH DMAC */
|
||||
@ -27,40 +25,8 @@
|
||||
#define TS_32 0x00000030
|
||||
#define TS_64 0x00000000
|
||||
|
||||
#define CHCR_TS_LOW_MASK 0x70
|
||||
#define CHCR_TS_LOW_SHIFT 4
|
||||
#define CHCR_TS_HIGH_MASK 0
|
||||
#define CHCR_TS_HIGH_SHIFT 0
|
||||
|
||||
#define DMAOR_COD 0x00000008
|
||||
|
||||
/*
|
||||
* The SuperH DMAC supports a number of transmit sizes, we list them here,
|
||||
* with their respective values as they appear in the CHCR registers.
|
||||
*
|
||||
* Defaults to a 64-bit transfer size.
|
||||
*/
|
||||
enum {
|
||||
XMIT_SZ_8BIT = 1,
|
||||
XMIT_SZ_16BIT = 2,
|
||||
XMIT_SZ_32BIT = 3,
|
||||
XMIT_SZ_64BIT = 0,
|
||||
XMIT_SZ_256BIT = 4,
|
||||
};
|
||||
|
||||
/*
|
||||
* The DMA count is defined as the number of bytes to transfer.
|
||||
*/
|
||||
#define TS_SHIFT { \
|
||||
[XMIT_SZ_8BIT] = 0, \
|
||||
[XMIT_SZ_16BIT] = 1, \
|
||||
[XMIT_SZ_32BIT] = 2, \
|
||||
[XMIT_SZ_64BIT] = 3, \
|
||||
[XMIT_SZ_256BIT] = 5, \
|
||||
}
|
||||
|
||||
#define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT)
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_CPU_SH4_DMA_H */
|
||||
|
@ -1,6 +1,7 @@
|
||||
#ifndef __ASM_SH_MIGOR_H
|
||||
#define __ASM_SH_MIGOR_H
|
||||
|
||||
#define PORT_MSELCRA 0xa4050180
|
||||
#define PORT_MSELCRB 0xa4050182
|
||||
#define BSC_CS4BCR 0xfec10010
|
||||
#define BSC_CS6ABCR 0xfec1001c
|
||||
|
@ -7,19 +7,167 @@
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/sh_timer.h>
|
||||
#include <linux/uio_driver.h>
|
||||
#include <linux/usb/m66592.h>
|
||||
#include <linux/sh_timer.h>
|
||||
|
||||
#include <asm/clock.h>
|
||||
#include <asm/dmaengine.h>
|
||||
#include <asm/mmzone.h>
|
||||
#include <asm/dma-sh.h>
|
||||
#include <asm/siu.h>
|
||||
|
||||
#include <cpu/dma-register.h>
|
||||
#include <cpu/sh7722.h>
|
||||
|
||||
static struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
|
||||
{
|
||||
.slave_id = SHDMA_SLAVE_SCIF0_TX,
|
||||
.addr = 0xffe0000c,
|
||||
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
|
||||
.mid_rid = 0x21,
|
||||
}, {
|
||||
.slave_id = SHDMA_SLAVE_SCIF0_RX,
|
||||
.addr = 0xffe00014,
|
||||
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
|
||||
.mid_rid = 0x22,
|
||||
}, {
|
||||
.slave_id = SHDMA_SLAVE_SCIF1_TX,
|
||||
.addr = 0xffe1000c,
|
||||
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
|
||||
.mid_rid = 0x25,
|
||||
}, {
|
||||
.slave_id = SHDMA_SLAVE_SCIF1_RX,
|
||||
.addr = 0xffe10014,
|
||||
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
|
||||
.mid_rid = 0x26,
|
||||
}, {
|
||||
.slave_id = SHDMA_SLAVE_SCIF2_TX,
|
||||
.addr = 0xffe2000c,
|
||||
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
|
||||
.mid_rid = 0x29,
|
||||
}, {
|
||||
.slave_id = SHDMA_SLAVE_SCIF2_RX,
|
||||
.addr = 0xffe20014,
|
||||
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
|
||||
.mid_rid = 0x2a,
|
||||
}, {
|
||||
.slave_id = SHDMA_SLAVE_SIUA_TX,
|
||||
.addr = 0xa454c098,
|
||||
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
|
||||
.mid_rid = 0xb1,
|
||||
}, {
|
||||
.slave_id = SHDMA_SLAVE_SIUA_RX,
|
||||
.addr = 0xa454c090,
|
||||
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
|
||||
.mid_rid = 0xb2,
|
||||
}, {
|
||||
.slave_id = SHDMA_SLAVE_SIUB_TX,
|
||||
.addr = 0xa454c09c,
|
||||
.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
|
||||
.mid_rid = 0xb5,
|
||||
}, {
|
||||
.slave_id = SHDMA_SLAVE_SIUB_RX,
|
||||
.addr = 0xa454c094,
|
||||
.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
|
||||
.mid_rid = 0xb6,
|
||||
},
|
||||
};
|
||||
|
||||
static struct sh_dmae_channel sh7722_dmae_channels[] = {
|
||||
{
|
||||
.offset = 0,
|
||||
.dmars = 0,
|
||||
.dmars_bit = 0,
|
||||
}, {
|
||||
.offset = 0x10,
|
||||
.dmars = 0,
|
||||
.dmars_bit = 8,
|
||||
}, {
|
||||
.offset = 0x20,
|
||||
.dmars = 4,
|
||||
.dmars_bit = 0,
|
||||
}, {
|
||||
.offset = 0x30,
|
||||
.dmars = 4,
|
||||
.dmars_bit = 8,
|
||||
}, {
|
||||
.offset = 0x50,
|
||||
.dmars = 8,
|
||||
.dmars_bit = 0,
|
||||
}, {
|
||||
.offset = 0x60,
|
||||
.dmars = 8,
|
||||
.dmars_bit = 8,
|
||||
}
|
||||
};
|
||||
|
||||
static unsigned int ts_shift[] = TS_SHIFT;
|
||||
|
||||
static struct sh_dmae_pdata dma_platform_data = {
|
||||
.slave = sh7722_dmae_slaves,
|
||||
.slave_num = ARRAY_SIZE(sh7722_dmae_slaves),
|
||||
.channel = sh7722_dmae_channels,
|
||||
.channel_num = ARRAY_SIZE(sh7722_dmae_channels),
|
||||
.ts_low_shift = CHCR_TS_LOW_SHIFT,
|
||||
.ts_low_mask = CHCR_TS_LOW_MASK,
|
||||
.ts_high_shift = CHCR_TS_HIGH_SHIFT,
|
||||
.ts_high_mask = CHCR_TS_HIGH_MASK,
|
||||
.ts_shift = ts_shift,
|
||||
.ts_shift_num = ARRAY_SIZE(ts_shift),
|
||||
.dmaor_init = DMAOR_INIT,
|
||||
};
|
||||
|
||||
static struct resource sh7722_dmae_resources[] = {
|
||||
[0] = {
|
||||
/* Channel registers and DMAOR */
|
||||
.start = 0xfe008020,
|
||||
.end = 0xfe00808f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
/* DMARSx */
|
||||
.start = 0xfe009000,
|
||||
.end = 0xfe00900b,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
/* DMA error IRQ */
|
||||
.start = 78,
|
||||
.end = 78,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
/* IRQ for channels 0-3 */
|
||||
.start = 48,
|
||||
.end = 51,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
/* IRQ for channels 4-5 */
|
||||
.start = 76,
|
||||
.end = 77,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
struct platform_device dma_device = {
|
||||
.name = "sh-dma-engine",
|
||||
.id = -1,
|
||||
.resource = sh7722_dmae_resources,
|
||||
.num_resources = ARRAY_SIZE(sh7722_dmae_resources),
|
||||
.dev = {
|
||||
.platform_data = &dma_platform_data,
|
||||
},
|
||||
.archdata = {
|
||||
.hwblk_id = HWBLK_DMAC,
|
||||
},
|
||||
};
|
||||
|
||||
/* Serial */
|
||||
static struct plat_sci_port scif0_platform_data = {
|
||||
.mapbase = 0xffe00000,
|
||||
@ -388,15 +536,36 @@ static struct platform_device tmu2_device = {
|
||||
},
|
||||
};
|
||||
|
||||
static struct sh_dmae_pdata dma_platform_data = {
|
||||
.mode = 0,
|
||||
static struct siu_platform siu_platform_data = {
|
||||
.dma_dev = &dma_device.dev,
|
||||
.dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX,
|
||||
.dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX,
|
||||
.dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX,
|
||||
.dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX,
|
||||
};
|
||||
|
||||
static struct platform_device dma_device = {
|
||||
.name = "sh-dma-engine",
|
||||
static struct resource siu_resources[] = {
|
||||
[0] = {
|
||||
.start = 0xa4540000,
|
||||
.end = 0xa454c10f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = 108,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device siu_device = {
|
||||
.name = "sh_siu",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &dma_platform_data,
|
||||
.dev = {
|
||||
.platform_data = &siu_platform_data,
|
||||
},
|
||||
.resource = siu_resources,
|
||||
.num_resources = ARRAY_SIZE(siu_resources),
|
||||
.archdata = {
|
||||
.hwblk_id = HWBLK_SIU,
|
||||
},
|
||||
};
|
||||
|
||||
@ -414,6 +583,7 @@ static struct platform_device *sh7722_devices[] __initdata = {
|
||||
&vpu_device,
|
||||
&veu_device,
|
||||
&jpu_device,
|
||||
&siu_device,
|
||||
&dma_device,
|
||||
};
|
||||
|
||||
|
@ -21,22 +21,189 @@
|
||||
#include <linux/sh_timer.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/notifier.h>
|
||||
|
||||
#include <asm/suspend.h>
|
||||
#include <asm/clock.h>
|
||||
#include <asm/dma-sh.h>
|
||||
#include <asm/dmaengine.h>
|
||||
#include <asm/mmzone.h>
|
||||
|
||||
#include <cpu/dma-register.h>
|
||||
#include <cpu/sh7724.h>
|
||||
|
||||
/* DMA */
|
||||
static struct sh_dmae_pdata dma_platform_data = {
|
||||
.mode = SHDMA_DMAOR1,
|
||||
static struct sh_dmae_channel sh7724_dmae0_channels[] = {
|
||||
{
|
||||
.offset = 0,
|
||||
.dmars = 0,
|
||||
.dmars_bit = 0,
|
||||
}, {
|
||||
.offset = 0x10,
|
||||
.dmars = 0,
|
||||
.dmars_bit = 8,
|
||||
}, {
|
||||
.offset = 0x20,
|
||||
.dmars = 4,
|
||||
.dmars_bit = 0,
|
||||
}, {
|
||||
.offset = 0x30,
|
||||
.dmars = 4,
|
||||
.dmars_bit = 8,
|
||||
}, {
|
||||
.offset = 0x50,
|
||||
.dmars = 8,
|
||||
.dmars_bit = 0,
|
||||
}, {
|
||||
.offset = 0x60,
|
||||
.dmars = 8,
|
||||
.dmars_bit = 8,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device dma_device = {
|
||||
.name = "sh-dma-engine",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &dma_platform_data,
|
||||
static struct sh_dmae_channel sh7724_dmae1_channels[] = {
|
||||
{
|
||||
.offset = 0,
|
||||
.dmars = 0,
|
||||
.dmars_bit = 0,
|
||||
}, {
|
||||
.offset = 0x10,
|
||||
.dmars = 0,
|
||||
.dmars_bit = 8,
|
||||
}, {
|
||||
.offset = 0x20,
|
||||
.dmars = 4,
|
||||
.dmars_bit = 0,
|
||||
}, {
|
||||
.offset = 0x30,
|
||||
.dmars = 4,
|
||||
.dmars_bit = 8,
|
||||
}, {
|
||||
.offset = 0x50,
|
||||
.dmars = 8,
|
||||
.dmars_bit = 0,
|
||||
}, {
|
||||
.offset = 0x60,
|
||||
.dmars = 8,
|
||||
.dmars_bit = 8,
|
||||
}
|
||||
};
|
||||
|
||||
static unsigned int ts_shift[] = TS_SHIFT;
|
||||
|
||||
static struct sh_dmae_pdata dma0_platform_data = {
|
||||
.channel = sh7724_dmae0_channels,
|
||||
.channel_num = ARRAY_SIZE(sh7724_dmae0_channels),
|
||||
.ts_low_shift = CHCR_TS_LOW_SHIFT,
|
||||
.ts_low_mask = CHCR_TS_LOW_MASK,
|
||||
.ts_high_shift = CHCR_TS_HIGH_SHIFT,
|
||||
.ts_high_mask = CHCR_TS_HIGH_MASK,
|
||||
.ts_shift = ts_shift,
|
||||
.ts_shift_num = ARRAY_SIZE(ts_shift),
|
||||
.dmaor_init = DMAOR_INIT,
|
||||
};
|
||||
|
||||
static struct sh_dmae_pdata dma1_platform_data = {
|
||||
.channel = sh7724_dmae1_channels,
|
||||
.channel_num = ARRAY_SIZE(sh7724_dmae1_channels),
|
||||
.ts_low_shift = CHCR_TS_LOW_SHIFT,
|
||||
.ts_low_mask = CHCR_TS_LOW_MASK,
|
||||
.ts_high_shift = CHCR_TS_HIGH_SHIFT,
|
||||
.ts_high_mask = CHCR_TS_HIGH_MASK,
|
||||
.ts_shift = ts_shift,
|
||||
.ts_shift_num = ARRAY_SIZE(ts_shift),
|
||||
.dmaor_init = DMAOR_INIT,
|
||||
};
|
||||
|
||||
/* Resource order important! */
|
||||
static struct resource sh7724_dmae0_resources[] = {
|
||||
{
|
||||
/* Channel registers and DMAOR */
|
||||
.start = 0xfe008020,
|
||||
.end = 0xfe00808f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
/* DMARSx */
|
||||
.start = 0xfe009000,
|
||||
.end = 0xfe00900b,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
/* DMA error IRQ */
|
||||
.start = 78,
|
||||
.end = 78,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
/* IRQ for channels 0-3 */
|
||||
.start = 48,
|
||||
.end = 51,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
/* IRQ for channels 4-5 */
|
||||
.start = 76,
|
||||
.end = 77,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
/* Resource order important! */
|
||||
static struct resource sh7724_dmae1_resources[] = {
|
||||
{
|
||||
/* Channel registers and DMAOR */
|
||||
.start = 0xfdc08020,
|
||||
.end = 0xfdc0808f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
/* DMARSx */
|
||||
.start = 0xfdc09000,
|
||||
.end = 0xfdc0900b,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
/* DMA error IRQ */
|
||||
.start = 74,
|
||||
.end = 74,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
/* IRQ for channels 0-3 */
|
||||
.start = 40,
|
||||
.end = 43,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
{
|
||||
/* IRQ for channels 4-5 */
|
||||
.start = 72,
|
||||
.end = 73,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device dma0_device = {
|
||||
.name = "sh-dma-engine",
|
||||
.id = 0,
|
||||
.resource = sh7724_dmae0_resources,
|
||||
.num_resources = ARRAY_SIZE(sh7724_dmae0_resources),
|
||||
.dev = {
|
||||
.platform_data = &dma0_platform_data,
|
||||
},
|
||||
.archdata = {
|
||||
.hwblk_id = HWBLK_DMAC0,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device dma1_device = {
|
||||
.name = "sh-dma-engine",
|
||||
.id = 1,
|
||||
.resource = sh7724_dmae1_resources,
|
||||
.num_resources = ARRAY_SIZE(sh7724_dmae1_resources),
|
||||
.dev = {
|
||||
.platform_data = &dma1_platform_data,
|
||||
},
|
||||
.archdata = {
|
||||
.hwblk_id = HWBLK_DMAC1,
|
||||
},
|
||||
};
|
||||
|
||||
@ -663,7 +830,8 @@ static struct platform_device *sh7724_devices[] __initdata = {
|
||||
&tmu3_device,
|
||||
&tmu4_device,
|
||||
&tmu5_device,
|
||||
&dma_device,
|
||||
&dma0_device,
|
||||
&dma1_device,
|
||||
&rtc_device,
|
||||
&iic0_device,
|
||||
&iic1_device,
|
||||
|
@ -13,7 +13,10 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/serial_sci.h>
|
||||
#include <linux/sh_timer.h>
|
||||
#include <asm/dma-sh.h>
|
||||
|
||||
#include <asm/dmaengine.h>
|
||||
|
||||
#include <cpu/dma-register.h>
|
||||
|
||||
static struct plat_sci_port scif0_platform_data = {
|
||||
.mapbase = 0xffe00000,
|
||||
@ -247,15 +250,131 @@ static struct platform_device rtc_device = {
|
||||
.resource = rtc_resources,
|
||||
};
|
||||
|
||||
static struct sh_dmae_pdata dma_platform_data = {
|
||||
.mode = (SHDMA_MIX_IRQ | SHDMA_DMAOR1),
|
||||
/* DMA */
|
||||
static struct sh_dmae_channel sh7780_dmae0_channels[] = {
|
||||
{
|
||||
.offset = 0,
|
||||
.dmars = 0,
|
||||
.dmars_bit = 0,
|
||||
}, {
|
||||
.offset = 0x10,
|
||||
.dmars = 0,
|
||||
.dmars_bit = 8,
|
||||
}, {
|
||||
.offset = 0x20,
|
||||
.dmars = 4,
|
||||
.dmars_bit = 0,
|
||||
}, {
|
||||
.offset = 0x30,
|
||||
.dmars = 4,
|
||||
.dmars_bit = 8,
|
||||
}, {
|
||||
.offset = 0x50,
|
||||
.dmars = 8,
|
||||
.dmars_bit = 0,
|
||||
}, {
|
||||
.offset = 0x60,
|
||||
.dmars = 8,
|
||||
.dmars_bit = 8,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device dma_device = {
|
||||
static struct sh_dmae_channel sh7780_dmae1_channels[] = {
|
||||
{
|
||||
.offset = 0,
|
||||
}, {
|
||||
.offset = 0x10,
|
||||
}, {
|
||||
.offset = 0x20,
|
||||
}, {
|
||||
.offset = 0x30,
|
||||
}, {
|
||||
.offset = 0x50,
|
||||
}, {
|
||||
.offset = 0x60,
|
||||
}
|
||||
};
|
||||
|
||||
static unsigned int ts_shift[] = TS_SHIFT;
|
||||
|
||||
static struct sh_dmae_pdata dma0_platform_data = {
|
||||
.channel = sh7780_dmae0_channels,
|
||||
.channel_num = ARRAY_SIZE(sh7780_dmae0_channels),
|
||||
.ts_low_shift = CHCR_TS_LOW_SHIFT,
|
||||
.ts_low_mask = CHCR_TS_LOW_MASK,
|
||||
.ts_high_shift = CHCR_TS_HIGH_SHIFT,
|
||||
.ts_high_mask = CHCR_TS_HIGH_MASK,
|
||||
.ts_shift = ts_shift,
|
||||
.ts_shift_num = ARRAY_SIZE(ts_shift),
|
||||
.dmaor_init = DMAOR_INIT,
|
||||
};
|
||||
|
||||
static struct sh_dmae_pdata dma1_platform_data = {
|
||||
.channel = sh7780_dmae1_channels,
|
||||
.channel_num = ARRAY_SIZE(sh7780_dmae1_channels),
|
||||
.ts_low_shift = CHCR_TS_LOW_SHIFT,
|
||||
.ts_low_mask = CHCR_TS_LOW_MASK,
|
||||
.ts_high_shift = CHCR_TS_HIGH_SHIFT,
|
||||
.ts_high_mask = CHCR_TS_HIGH_MASK,
|
||||
.ts_shift = ts_shift,
|
||||
.ts_shift_num = ARRAY_SIZE(ts_shift),
|
||||
.dmaor_init = DMAOR_INIT,
|
||||
};
|
||||
|
||||
static struct resource sh7780_dmae0_resources[] = {
|
||||
[0] = {
|
||||
/* Channel registers and DMAOR */
|
||||
.start = 0xfc808020,
|
||||
.end = 0xfc80808f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
/* DMARSx */
|
||||
.start = 0xfc809000,
|
||||
.end = 0xfc80900b,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
/* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */
|
||||
.start = 34,
|
||||
.end = 34,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource sh7780_dmae1_resources[] = {
|
||||
[0] = {
|
||||
/* Channel registers and DMAOR */
|
||||
.start = 0xfc818020,
|
||||
.end = 0xfc81808f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
/* DMAC1 has no DMARS */
|
||||
{
|
||||
/* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */
|
||||
.start = 46,
|
||||
.end = 46,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device dma0_device = {
|
||||
.name = "sh-dma-engine",
|
||||
.id = -1,
|
||||
.id = 0,
|
||||
.resource = sh7780_dmae0_resources,
|
||||
.num_resources = ARRAY_SIZE(sh7780_dmae0_resources),
|
||||
.dev = {
|
||||
.platform_data = &dma_platform_data,
|
||||
.platform_data = &dma0_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device dma1_device = {
|
||||
.name = "sh-dma-engine",
|
||||
.id = 1,
|
||||
.resource = sh7780_dmae1_resources,
|
||||
.num_resources = ARRAY_SIZE(sh7780_dmae1_resources),
|
||||
.dev = {
|
||||
.platform_data = &dma1_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
@ -269,7 +388,8 @@ static struct platform_device *sh7780_devices[] __initdata = {
|
||||
&tmu4_device,
|
||||
&tmu5_device,
|
||||
&rtc_device,
|
||||
&dma_device,
|
||||
&dma0_device,
|
||||
&dma1_device,
|
||||
};
|
||||
|
||||
static int __init sh7780_devices_setup(void)
|
||||
|
@ -14,9 +14,12 @@
|
||||
#include <linux/io.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/sh_timer.h>
|
||||
#include <asm/dma-sh.h>
|
||||
|
||||
#include <asm/dmaengine.h>
|
||||
#include <asm/mmzone.h>
|
||||
|
||||
#include <cpu/dma-register.h>
|
||||
|
||||
static struct plat_sci_port scif0_platform_data = {
|
||||
.mapbase = 0xffea0000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
@ -295,15 +298,131 @@ static struct platform_device tmu5_device = {
|
||||
.num_resources = ARRAY_SIZE(tmu5_resources),
|
||||
};
|
||||
|
||||
static struct sh_dmae_pdata dma_platform_data = {
|
||||
.mode = (SHDMA_MIX_IRQ | SHDMA_DMAOR1),
|
||||
/* DMA */
|
||||
static struct sh_dmae_channel sh7785_dmae0_channels[] = {
|
||||
{
|
||||
.offset = 0,
|
||||
.dmars = 0,
|
||||
.dmars_bit = 0,
|
||||
}, {
|
||||
.offset = 0x10,
|
||||
.dmars = 0,
|
||||
.dmars_bit = 8,
|
||||
}, {
|
||||
.offset = 0x20,
|
||||
.dmars = 4,
|
||||
.dmars_bit = 0,
|
||||
}, {
|
||||
.offset = 0x30,
|
||||
.dmars = 4,
|
||||
.dmars_bit = 8,
|
||||
}, {
|
||||
.offset = 0x50,
|
||||
.dmars = 8,
|
||||
.dmars_bit = 0,
|
||||
}, {
|
||||
.offset = 0x60,
|
||||
.dmars = 8,
|
||||
.dmars_bit = 8,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device dma_device = {
|
||||
static struct sh_dmae_channel sh7785_dmae1_channels[] = {
|
||||
{
|
||||
.offset = 0,
|
||||
}, {
|
||||
.offset = 0x10,
|
||||
}, {
|
||||
.offset = 0x20,
|
||||
}, {
|
||||
.offset = 0x30,
|
||||
}, {
|
||||
.offset = 0x50,
|
||||
}, {
|
||||
.offset = 0x60,
|
||||
}
|
||||
};
|
||||
|
||||
static unsigned int ts_shift[] = TS_SHIFT;
|
||||
|
||||
static struct sh_dmae_pdata dma0_platform_data = {
|
||||
.channel = sh7785_dmae0_channels,
|
||||
.channel_num = ARRAY_SIZE(sh7785_dmae0_channels),
|
||||
.ts_low_shift = CHCR_TS_LOW_SHIFT,
|
||||
.ts_low_mask = CHCR_TS_LOW_MASK,
|
||||
.ts_high_shift = CHCR_TS_HIGH_SHIFT,
|
||||
.ts_high_mask = CHCR_TS_HIGH_MASK,
|
||||
.ts_shift = ts_shift,
|
||||
.ts_shift_num = ARRAY_SIZE(ts_shift),
|
||||
.dmaor_init = DMAOR_INIT,
|
||||
};
|
||||
|
||||
static struct sh_dmae_pdata dma1_platform_data = {
|
||||
.channel = sh7785_dmae1_channels,
|
||||
.channel_num = ARRAY_SIZE(sh7785_dmae1_channels),
|
||||
.ts_low_shift = CHCR_TS_LOW_SHIFT,
|
||||
.ts_low_mask = CHCR_TS_LOW_MASK,
|
||||
.ts_high_shift = CHCR_TS_HIGH_SHIFT,
|
||||
.ts_high_mask = CHCR_TS_HIGH_MASK,
|
||||
.ts_shift = ts_shift,
|
||||
.ts_shift_num = ARRAY_SIZE(ts_shift),
|
||||
.dmaor_init = DMAOR_INIT,
|
||||
};
|
||||
|
||||
static struct resource sh7785_dmae0_resources[] = {
|
||||
[0] = {
|
||||
/* Channel registers and DMAOR */
|
||||
.start = 0xfc808020,
|
||||
.end = 0xfc80808f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
/* DMARSx */
|
||||
.start = 0xfc809000,
|
||||
.end = 0xfc80900b,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
{
|
||||
/* Real DMA error IRQ is 39, and channel IRQs are 33-38 */
|
||||
.start = 33,
|
||||
.end = 33,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource sh7785_dmae1_resources[] = {
|
||||
[0] = {
|
||||
/* Channel registers and DMAOR */
|
||||
.start = 0xfcc08020,
|
||||
.end = 0xfcc0808f,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
/* DMAC1 has no DMARS */
|
||||
{
|
||||
/* Real DMA error IRQ is 58, and channel IRQs are 52-57 */
|
||||
.start = 52,
|
||||
.end = 52,
|
||||
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device dma0_device = {
|
||||
.name = "sh-dma-engine",
|
||||
.id = -1,
|
||||
.id = 0,
|
||||
.resource = sh7785_dmae0_resources,
|
||||
.num_resources = ARRAY_SIZE(sh7785_dmae0_resources),
|
||||
.dev = {
|
||||
.platform_data = &dma_platform_data,
|
||||
.platform_data = &dma0_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device dma1_device = {
|
||||
.name = "sh-dma-engine",
|
||||
.id = 1,
|
||||
.resource = sh7785_dmae1_resources,
|
||||
.num_resources = ARRAY_SIZE(sh7785_dmae1_resources),
|
||||
.dev = {
|
||||
.platform_data = &dma1_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
@ -320,7 +439,8 @@ static struct platform_device *sh7785_devices[] __initdata = {
|
||||
&tmu3_device,
|
||||
&tmu4_device,
|
||||
&tmu5_device,
|
||||
&dma_device,
|
||||
&dma0_device,
|
||||
&dma1_device,
|
||||
};
|
||||
|
||||
static int __init sh7785_devices_setup(void)
|
||||
|
@ -143,26 +143,6 @@ static int arch_check_va_in_kernelspace(unsigned long va, u8 hbp_len)
|
||||
return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
|
||||
}
|
||||
|
||||
/*
|
||||
* Store a breakpoint's encoded address, length, and type.
|
||||
*/
|
||||
static int arch_store_info(struct perf_event *bp)
|
||||
{
|
||||
struct arch_hw_breakpoint *info = counter_arch_bp(bp);
|
||||
|
||||
/*
|
||||
* User-space requests will always have the address field populated
|
||||
* For kernel-addresses, either the address or symbol name can be
|
||||
* specified.
|
||||
*/
|
||||
if (info->name)
|
||||
info->address = (unsigned long)kallsyms_lookup_name(info->name);
|
||||
if (info->address)
|
||||
return 0;
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
int arch_bp_generic_fields(int sh_len, int sh_type,
|
||||
int *gen_len, int *gen_type)
|
||||
{
|
||||
@ -276,10 +256,12 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp,
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = arch_store_info(bp);
|
||||
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
/*
|
||||
* For kernel-addresses, either the address or symbol name can be
|
||||
* specified.
|
||||
*/
|
||||
if (info->name)
|
||||
info->address = (unsigned long)kallsyms_lookup_name(info->name);
|
||||
|
||||
/*
|
||||
* Check that the low-order bits of the address are appropriate
|
||||
|
@ -443,7 +443,7 @@ void __init setup_arch(char **cmdline_p)
|
||||
|
||||
nodes_clear(node_online_map);
|
||||
|
||||
/* Setup bootmem with available RAM */
|
||||
pmb_init();
|
||||
lmb_init();
|
||||
setup_memory();
|
||||
sparse_init();
|
||||
@ -452,7 +452,6 @@ void __init setup_arch(char **cmdline_p)
|
||||
conswitchp = &dummy_con;
|
||||
#endif
|
||||
paging_init();
|
||||
pmb_init();
|
||||
|
||||
ioremap_fixed_init();
|
||||
|
||||
|
@ -39,12 +39,12 @@ static int null_rtc_set_time(const time_t secs)
|
||||
void (*rtc_sh_get_time)(struct timespec *) = null_rtc_get_time;
|
||||
int (*rtc_sh_set_time)(const time_t) = null_rtc_set_time;
|
||||
|
||||
#ifdef CONFIG_GENERIC_CMOS_UPDATE
|
||||
void read_persistent_clock(struct timespec *ts)
|
||||
{
|
||||
rtc_sh_get_time(ts);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_GENERIC_CMOS_UPDATE
|
||||
int update_persistent_clock(struct timespec now)
|
||||
{
|
||||
return rtc_sh_set_time(now.tv_sec);
|
||||
@ -113,9 +113,5 @@ void __init time_init(void)
|
||||
hwblk_init();
|
||||
clk_init();
|
||||
|
||||
rtc_sh_get_time(&xtime);
|
||||
set_normalized_timespec(&wall_to_monotonic,
|
||||
-xtime.tv_sec, -xtime.tv_nsec);
|
||||
|
||||
late_time_init = sh_late_time_init;
|
||||
}
|
||||
|
@ -17,8 +17,7 @@ struct DWstruct {
|
||||
#error I feel sick.
|
||||
#endif
|
||||
|
||||
typedef union
|
||||
{
|
||||
typedef union {
|
||||
struct DWstruct s;
|
||||
long long ll;
|
||||
} DWunion;
|
||||
|
@ -34,17 +34,32 @@
|
||||
* caller shouldn't need to know that small detail.
|
||||
*/
|
||||
void __iomem * __init_refok
|
||||
__ioremap_caller(unsigned long phys_addr, unsigned long size,
|
||||
__ioremap_caller(phys_addr_t phys_addr, unsigned long size,
|
||||
pgprot_t pgprot, void *caller)
|
||||
{
|
||||
struct vm_struct *area;
|
||||
unsigned long offset, last_addr, addr, orig_addr;
|
||||
void __iomem *mapped;
|
||||
|
||||
/* Don't allow wraparound or zero size */
|
||||
last_addr = phys_addr + size - 1;
|
||||
if (!size || last_addr < phys_addr)
|
||||
return NULL;
|
||||
|
||||
/*
|
||||
* If we can't yet use the regular approach, go the fixmap route.
|
||||
*/
|
||||
if (!mem_init_done)
|
||||
return ioremap_fixed(phys_addr, size, pgprot);
|
||||
|
||||
/*
|
||||
* First try to remap through the PMB.
|
||||
* PMB entries are all pre-faulted.
|
||||
*/
|
||||
mapped = pmb_remap_caller(phys_addr, size, pgprot, caller);
|
||||
if (mapped && !IS_ERR(mapped))
|
||||
return mapped;
|
||||
|
||||
/*
|
||||
* Mappings have to be page-aligned
|
||||
*/
|
||||
@ -52,12 +67,6 @@ __ioremap_caller(unsigned long phys_addr, unsigned long size,
|
||||
phys_addr &= PAGE_MASK;
|
||||
size = PAGE_ALIGN(last_addr+1) - phys_addr;
|
||||
|
||||
/*
|
||||
* If we can't yet use the regular approach, go the fixmap route.
|
||||
*/
|
||||
if (!mem_init_done)
|
||||
return ioremap_fixed(phys_addr, offset, size, pgprot);
|
||||
|
||||
/*
|
||||
* Ok, go for it..
|
||||
*/
|
||||
@ -67,33 +76,10 @@ __ioremap_caller(unsigned long phys_addr, unsigned long size,
|
||||
area->phys_addr = phys_addr;
|
||||
orig_addr = addr = (unsigned long)area->addr;
|
||||
|
||||
#ifdef CONFIG_PMB
|
||||
/*
|
||||
* First try to remap through the PMB once a valid VMA has been
|
||||
* established. Smaller allocations (or the rest of the size
|
||||
* remaining after a PMB mapping due to the size not being
|
||||
* perfectly aligned on a PMB size boundary) are then mapped
|
||||
* through the UTLB using conventional page tables.
|
||||
*
|
||||
* PMB entries are all pre-faulted.
|
||||
*/
|
||||
if (unlikely(phys_addr >= P1SEG)) {
|
||||
unsigned long mapped;
|
||||
|
||||
mapped = pmb_remap(addr, phys_addr, size, pgprot);
|
||||
if (likely(mapped)) {
|
||||
addr += mapped;
|
||||
phys_addr += mapped;
|
||||
size -= mapped;
|
||||
}
|
||||
if (ioremap_page_range(addr, addr + size, phys_addr, pgprot)) {
|
||||
vunmap((void *)orig_addr);
|
||||
return NULL;
|
||||
}
|
||||
#endif
|
||||
|
||||
if (likely(size))
|
||||
if (ioremap_page_range(addr, addr + size, phys_addr, pgprot)) {
|
||||
vunmap((void *)orig_addr);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return (void __iomem *)(offset + (char *)orig_addr);
|
||||
}
|
||||
@ -133,23 +119,11 @@ void __iounmap(void __iomem *addr)
|
||||
if (iounmap_fixed(addr) == 0)
|
||||
return;
|
||||
|
||||
#ifdef CONFIG_PMB
|
||||
/*
|
||||
* Purge any PMB entries that may have been established for this
|
||||
* mapping, then proceed with conventional VMA teardown.
|
||||
*
|
||||
* XXX: Note that due to the way that remove_vm_area() does
|
||||
* matching of the resultant VMA, we aren't able to fast-forward
|
||||
* the address past the PMB space until the end of the VMA where
|
||||
* the page tables reside. As such, unmap_vm_area() will be
|
||||
* forced to linearly scan over the area until it finds the page
|
||||
* tables where PTEs that need to be unmapped actually reside,
|
||||
* which is far from optimal. Perhaps we need to use a separate
|
||||
* VMA for the PMB mappings?
|
||||
* -- PFM.
|
||||
* If the PMB handled it, there's nothing else to do.
|
||||
*/
|
||||
pmb_unmap(vaddr);
|
||||
#endif
|
||||
if (pmb_unmap(addr) == 0)
|
||||
return;
|
||||
|
||||
p = remove_vm_area((void *)(vaddr & PAGE_MASK));
|
||||
if (!p) {
|
||||
|
@ -45,14 +45,21 @@ void __init ioremap_fixed_init(void)
|
||||
}
|
||||
|
||||
void __init __iomem *
|
||||
ioremap_fixed(resource_size_t phys_addr, unsigned long offset,
|
||||
unsigned long size, pgprot_t prot)
|
||||
ioremap_fixed(phys_addr_t phys_addr, unsigned long size, pgprot_t prot)
|
||||
{
|
||||
enum fixed_addresses idx0, idx;
|
||||
struct ioremap_map *map;
|
||||
unsigned int nrpages;
|
||||
unsigned long offset;
|
||||
int i, slot;
|
||||
|
||||
/*
|
||||
* Mappings have to be page-aligned
|
||||
*/
|
||||
offset = phys_addr & ~PAGE_MASK;
|
||||
phys_addr &= PAGE_MASK;
|
||||
size = PAGE_ALIGN(phys_addr + size) - phys_addr;
|
||||
|
||||
slot = -1;
|
||||
for (i = 0; i < FIX_N_IOREMAPS; i++) {
|
||||
map = &ioremap_maps[i];
|
||||
|
@ -74,6 +74,9 @@ void __init setup_bootmem_node(int nid, unsigned long start, unsigned long end)
|
||||
start_pfn = start >> PAGE_SHIFT;
|
||||
end_pfn = end >> PAGE_SHIFT;
|
||||
|
||||
pmb_bolt_mapping((unsigned long)__va(start), start, end - start,
|
||||
PAGE_KERNEL);
|
||||
|
||||
lmb_add(start, end - start);
|
||||
|
||||
__add_active_range(nid, start_pfn, end_pfn);
|
||||
|
434
arch/sh/mm/pmb.c
434
arch/sh/mm/pmb.c
@ -23,7 +23,8 @@
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/rwlock.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/uaccess.h>
|
||||
@ -52,12 +53,24 @@ struct pmb_entry {
|
||||
struct pmb_entry *link;
|
||||
};
|
||||
|
||||
static struct {
|
||||
unsigned long size;
|
||||
int flag;
|
||||
} pmb_sizes[] = {
|
||||
{ .size = SZ_512M, .flag = PMB_SZ_512M, },
|
||||
{ .size = SZ_128M, .flag = PMB_SZ_128M, },
|
||||
{ .size = SZ_64M, .flag = PMB_SZ_64M, },
|
||||
{ .size = SZ_16M, .flag = PMB_SZ_16M, },
|
||||
};
|
||||
|
||||
static void pmb_unmap_entry(struct pmb_entry *, int depth);
|
||||
|
||||
static DEFINE_RWLOCK(pmb_rwlock);
|
||||
static struct pmb_entry pmb_entry_list[NR_PMB_ENTRIES];
|
||||
static DECLARE_BITMAP(pmb_map, NR_PMB_ENTRIES);
|
||||
|
||||
static unsigned int pmb_iomapping_enabled;
|
||||
|
||||
static __always_inline unsigned long mk_pmb_entry(unsigned int entry)
|
||||
{
|
||||
return (entry & PMB_E_MASK) << PMB_E_SHIFT;
|
||||
@ -73,6 +86,142 @@ static __always_inline unsigned long mk_pmb_data(unsigned int entry)
|
||||
return mk_pmb_entry(entry) | PMB_DATA;
|
||||
}
|
||||
|
||||
static __always_inline unsigned int pmb_ppn_in_range(unsigned long ppn)
|
||||
{
|
||||
return ppn >= __pa(memory_start) && ppn < __pa(memory_end);
|
||||
}
|
||||
|
||||
/*
|
||||
* Ensure that the PMB entries match our cache configuration.
|
||||
*
|
||||
* When we are in 32-bit address extended mode, CCR.CB becomes
|
||||
* invalid, so care must be taken to manually adjust cacheable
|
||||
* translations.
|
||||
*/
|
||||
static __always_inline unsigned long pmb_cache_flags(void)
|
||||
{
|
||||
unsigned long flags = 0;
|
||||
|
||||
#if defined(CONFIG_CACHE_OFF)
|
||||
flags |= PMB_WT | PMB_UB;
|
||||
#elif defined(CONFIG_CACHE_WRITETHROUGH)
|
||||
flags |= PMB_C | PMB_WT | PMB_UB;
|
||||
#elif defined(CONFIG_CACHE_WRITEBACK)
|
||||
flags |= PMB_C;
|
||||
#endif
|
||||
|
||||
return flags;
|
||||
}
|
||||
|
||||
/*
|
||||
* Convert typical pgprot value to the PMB equivalent
|
||||
*/
|
||||
static inline unsigned long pgprot_to_pmb_flags(pgprot_t prot)
|
||||
{
|
||||
unsigned long pmb_flags = 0;
|
||||
u64 flags = pgprot_val(prot);
|
||||
|
||||
if (flags & _PAGE_CACHABLE)
|
||||
pmb_flags |= PMB_C;
|
||||
if (flags & _PAGE_WT)
|
||||
pmb_flags |= PMB_WT | PMB_UB;
|
||||
|
||||
return pmb_flags;
|
||||
}
|
||||
|
||||
static inline bool pmb_can_merge(struct pmb_entry *a, struct pmb_entry *b)
|
||||
{
|
||||
return (b->vpn == (a->vpn + a->size)) &&
|
||||
(b->ppn == (a->ppn + a->size)) &&
|
||||
(b->flags == a->flags);
|
||||
}
|
||||
|
||||
static bool pmb_mapping_exists(unsigned long vaddr, phys_addr_t phys,
|
||||
unsigned long size)
|
||||
{
|
||||
int i;
|
||||
|
||||
read_lock(&pmb_rwlock);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
|
||||
struct pmb_entry *pmbe, *iter;
|
||||
unsigned long span;
|
||||
|
||||
if (!test_bit(i, pmb_map))
|
||||
continue;
|
||||
|
||||
pmbe = &pmb_entry_list[i];
|
||||
|
||||
/*
|
||||
* See if VPN and PPN are bounded by an existing mapping.
|
||||
*/
|
||||
if ((vaddr < pmbe->vpn) || (vaddr >= (pmbe->vpn + pmbe->size)))
|
||||
continue;
|
||||
if ((phys < pmbe->ppn) || (phys >= (pmbe->ppn + pmbe->size)))
|
||||
continue;
|
||||
|
||||
/*
|
||||
* Now see if we're in range of a simple mapping.
|
||||
*/
|
||||
if (size <= pmbe->size) {
|
||||
read_unlock(&pmb_rwlock);
|
||||
return true;
|
||||
}
|
||||
|
||||
span = pmbe->size;
|
||||
|
||||
/*
|
||||
* Finally for sizes that involve compound mappings, walk
|
||||
* the chain.
|
||||
*/
|
||||
for (iter = pmbe->link; iter; iter = iter->link)
|
||||
span += iter->size;
|
||||
|
||||
/*
|
||||
* Nothing else to do if the range requirements are met.
|
||||
*/
|
||||
if (size <= span) {
|
||||
read_unlock(&pmb_rwlock);
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
read_unlock(&pmb_rwlock);
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool pmb_size_valid(unsigned long size)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++)
|
||||
if (pmb_sizes[i].size == size)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static inline bool pmb_addr_valid(unsigned long addr, unsigned long size)
|
||||
{
|
||||
return (addr >= P1SEG && (addr + size - 1) < P3SEG);
|
||||
}
|
||||
|
||||
static inline bool pmb_prot_valid(pgprot_t prot)
|
||||
{
|
||||
return (pgprot_val(prot) & _PAGE_USER) == 0;
|
||||
}
|
||||
|
||||
static int pmb_size_to_flags(unsigned long size)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++)
|
||||
if (pmb_sizes[i].size == size)
|
||||
return pmb_sizes[i].flag;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pmb_alloc_entry(void)
|
||||
{
|
||||
int pos;
|
||||
@ -139,34 +288,23 @@ static void pmb_free(struct pmb_entry *pmbe)
|
||||
pmbe->link = NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Ensure that the PMB entries match our cache configuration.
|
||||
*
|
||||
* When we are in 32-bit address extended mode, CCR.CB becomes
|
||||
* invalid, so care must be taken to manually adjust cacheable
|
||||
* translations.
|
||||
*/
|
||||
static __always_inline unsigned long pmb_cache_flags(void)
|
||||
{
|
||||
unsigned long flags = 0;
|
||||
|
||||
#if defined(CONFIG_CACHE_WRITETHROUGH)
|
||||
flags |= PMB_C | PMB_WT | PMB_UB;
|
||||
#elif defined(CONFIG_CACHE_WRITEBACK)
|
||||
flags |= PMB_C;
|
||||
#endif
|
||||
|
||||
return flags;
|
||||
}
|
||||
|
||||
/*
|
||||
* Must be run uncached.
|
||||
*/
|
||||
static void __set_pmb_entry(struct pmb_entry *pmbe)
|
||||
{
|
||||
writel_uncached(pmbe->vpn | PMB_V, mk_pmb_addr(pmbe->entry));
|
||||
writel_uncached(pmbe->ppn | pmbe->flags | PMB_V,
|
||||
mk_pmb_data(pmbe->entry));
|
||||
unsigned long addr, data;
|
||||
|
||||
addr = mk_pmb_addr(pmbe->entry);
|
||||
data = mk_pmb_data(pmbe->entry);
|
||||
|
||||
jump_to_uncached();
|
||||
|
||||
/* Set V-bit */
|
||||
__raw_writel(pmbe->vpn | PMB_V, addr);
|
||||
__raw_writel(pmbe->ppn | pmbe->flags | PMB_V, data);
|
||||
|
||||
back_to_cached();
|
||||
}
|
||||
|
||||
static void __clear_pmb_entry(struct pmb_entry *pmbe)
|
||||
@ -194,144 +332,155 @@ static void set_pmb_entry(struct pmb_entry *pmbe)
|
||||
spin_unlock_irqrestore(&pmbe->lock, flags);
|
||||
}
|
||||
|
||||
static struct {
|
||||
unsigned long size;
|
||||
int flag;
|
||||
} pmb_sizes[] = {
|
||||
{ .size = SZ_512M, .flag = PMB_SZ_512M, },
|
||||
{ .size = SZ_128M, .flag = PMB_SZ_128M, },
|
||||
{ .size = SZ_64M, .flag = PMB_SZ_64M, },
|
||||
{ .size = SZ_16M, .flag = PMB_SZ_16M, },
|
||||
};
|
||||
|
||||
long pmb_remap(unsigned long vaddr, unsigned long phys,
|
||||
unsigned long size, pgprot_t prot)
|
||||
int pmb_bolt_mapping(unsigned long vaddr, phys_addr_t phys,
|
||||
unsigned long size, pgprot_t prot)
|
||||
{
|
||||
struct pmb_entry *pmbp, *pmbe;
|
||||
unsigned long wanted;
|
||||
int pmb_flags, i;
|
||||
long err;
|
||||
u64 flags;
|
||||
unsigned long orig_addr, orig_size;
|
||||
unsigned long flags, pmb_flags;
|
||||
int i, mapped;
|
||||
|
||||
flags = pgprot_val(prot);
|
||||
if (!pmb_addr_valid(vaddr, size))
|
||||
return -EFAULT;
|
||||
if (pmb_mapping_exists(vaddr, phys, size))
|
||||
return 0;
|
||||
|
||||
pmb_flags = PMB_WT | PMB_UB;
|
||||
orig_addr = vaddr;
|
||||
orig_size = size;
|
||||
|
||||
/* Convert typical pgprot value to the PMB equivalent */
|
||||
if (flags & _PAGE_CACHABLE) {
|
||||
pmb_flags |= PMB_C;
|
||||
|
||||
if ((flags & _PAGE_WT) == 0)
|
||||
pmb_flags &= ~(PMB_WT | PMB_UB);
|
||||
}
|
||||
flush_tlb_kernel_range(vaddr, vaddr + size);
|
||||
|
||||
pmb_flags = pgprot_to_pmb_flags(prot);
|
||||
pmbp = NULL;
|
||||
wanted = size;
|
||||
|
||||
again:
|
||||
for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++) {
|
||||
unsigned long flags;
|
||||
do {
|
||||
for (i = mapped = 0; i < ARRAY_SIZE(pmb_sizes); i++) {
|
||||
if (size < pmb_sizes[i].size)
|
||||
continue;
|
||||
|
||||
if (size < pmb_sizes[i].size)
|
||||
continue;
|
||||
pmbe = pmb_alloc(vaddr, phys, pmb_flags |
|
||||
pmb_sizes[i].flag, PMB_NO_ENTRY);
|
||||
if (IS_ERR(pmbe)) {
|
||||
pmb_unmap_entry(pmbp, mapped);
|
||||
return PTR_ERR(pmbe);
|
||||
}
|
||||
|
||||
pmbe = pmb_alloc(vaddr, phys, pmb_flags | pmb_sizes[i].flag,
|
||||
PMB_NO_ENTRY);
|
||||
if (IS_ERR(pmbe)) {
|
||||
err = PTR_ERR(pmbe);
|
||||
goto out;
|
||||
spin_lock_irqsave(&pmbe->lock, flags);
|
||||
|
||||
pmbe->size = pmb_sizes[i].size;
|
||||
|
||||
__set_pmb_entry(pmbe);
|
||||
|
||||
phys += pmbe->size;
|
||||
vaddr += pmbe->size;
|
||||
size -= pmbe->size;
|
||||
|
||||
/*
|
||||
* Link adjacent entries that span multiple PMB
|
||||
* entries for easier tear-down.
|
||||
*/
|
||||
if (likely(pmbp)) {
|
||||
spin_lock(&pmbp->lock);
|
||||
pmbp->link = pmbe;
|
||||
spin_unlock(&pmbp->lock);
|
||||
}
|
||||
|
||||
pmbp = pmbe;
|
||||
|
||||
/*
|
||||
* Instead of trying smaller sizes on every
|
||||
* iteration (even if we succeed in allocating
|
||||
* space), try using pmb_sizes[i].size again.
|
||||
*/
|
||||
i--;
|
||||
mapped++;
|
||||
|
||||
spin_unlock_irqrestore(&pmbe->lock, flags);
|
||||
}
|
||||
} while (size >= SZ_16M);
|
||||
|
||||
spin_lock_irqsave(&pmbe->lock, flags);
|
||||
flush_cache_vmap(orig_addr, orig_addr + orig_size);
|
||||
|
||||
__set_pmb_entry(pmbe);
|
||||
|
||||
phys += pmb_sizes[i].size;
|
||||
vaddr += pmb_sizes[i].size;
|
||||
size -= pmb_sizes[i].size;
|
||||
|
||||
pmbe->size = pmb_sizes[i].size;
|
||||
|
||||
/*
|
||||
* Link adjacent entries that span multiple PMB entries
|
||||
* for easier tear-down.
|
||||
*/
|
||||
if (likely(pmbp)) {
|
||||
spin_lock(&pmbp->lock);
|
||||
pmbp->link = pmbe;
|
||||
spin_unlock(&pmbp->lock);
|
||||
}
|
||||
|
||||
pmbp = pmbe;
|
||||
|
||||
/*
|
||||
* Instead of trying smaller sizes on every iteration
|
||||
* (even if we succeed in allocating space), try using
|
||||
* pmb_sizes[i].size again.
|
||||
*/
|
||||
i--;
|
||||
|
||||
spin_unlock_irqrestore(&pmbe->lock, flags);
|
||||
}
|
||||
|
||||
if (size >= SZ_16M)
|
||||
goto again;
|
||||
|
||||
return wanted - size;
|
||||
|
||||
out:
|
||||
pmb_unmap_entry(pmbp, NR_PMB_ENTRIES);
|
||||
|
||||
return err;
|
||||
return 0;
|
||||
}
|
||||
|
||||
void pmb_unmap(unsigned long addr)
|
||||
void __iomem *pmb_remap_caller(phys_addr_t phys, unsigned long size,
|
||||
pgprot_t prot, void *caller)
|
||||
{
|
||||
unsigned long vaddr;
|
||||
phys_addr_t offset, last_addr;
|
||||
phys_addr_t align_mask;
|
||||
unsigned long aligned;
|
||||
struct vm_struct *area;
|
||||
int i, ret;
|
||||
|
||||
if (!pmb_iomapping_enabled)
|
||||
return NULL;
|
||||
|
||||
/*
|
||||
* Small mappings need to go through the TLB.
|
||||
*/
|
||||
if (size < SZ_16M)
|
||||
return ERR_PTR(-EINVAL);
|
||||
if (!pmb_prot_valid(prot))
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++)
|
||||
if (size >= pmb_sizes[i].size)
|
||||
break;
|
||||
|
||||
last_addr = phys + size;
|
||||
align_mask = ~(pmb_sizes[i].size - 1);
|
||||
offset = phys & ~align_mask;
|
||||
phys &= align_mask;
|
||||
aligned = ALIGN(last_addr, pmb_sizes[i].size) - phys;
|
||||
|
||||
/*
|
||||
* XXX: This should really start from uncached_end, but this
|
||||
* causes the MMU to reset, so for now we restrict it to the
|
||||
* 0xb000...0xc000 range.
|
||||
*/
|
||||
area = __get_vm_area_caller(aligned, VM_IOREMAP, 0xb0000000,
|
||||
P3SEG, caller);
|
||||
if (!area)
|
||||
return NULL;
|
||||
|
||||
area->phys_addr = phys;
|
||||
vaddr = (unsigned long)area->addr;
|
||||
|
||||
ret = pmb_bolt_mapping(vaddr, phys, size, prot);
|
||||
if (unlikely(ret != 0))
|
||||
return ERR_PTR(ret);
|
||||
|
||||
return (void __iomem *)(offset + (char *)vaddr);
|
||||
}
|
||||
|
||||
int pmb_unmap(void __iomem *addr)
|
||||
{
|
||||
struct pmb_entry *pmbe = NULL;
|
||||
int i;
|
||||
unsigned long vaddr = (unsigned long __force)addr;
|
||||
int i, found = 0;
|
||||
|
||||
read_lock(&pmb_rwlock);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pmb_entry_list); i++) {
|
||||
if (test_bit(i, pmb_map)) {
|
||||
pmbe = &pmb_entry_list[i];
|
||||
if (pmbe->vpn == addr)
|
||||
if (pmbe->vpn == vaddr) {
|
||||
found = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
read_unlock(&pmb_rwlock);
|
||||
|
||||
pmb_unmap_entry(pmbe, NR_PMB_ENTRIES);
|
||||
}
|
||||
if (found) {
|
||||
pmb_unmap_entry(pmbe, NR_PMB_ENTRIES);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool pmb_can_merge(struct pmb_entry *a, struct pmb_entry *b)
|
||||
{
|
||||
return (b->vpn == (a->vpn + a->size)) &&
|
||||
(b->ppn == (a->ppn + a->size)) &&
|
||||
(b->flags == a->flags);
|
||||
}
|
||||
|
||||
static bool pmb_size_valid(unsigned long size)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++)
|
||||
if (pmb_sizes[i].size == size)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static int pmb_size_to_flags(unsigned long size)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(pmb_sizes); i++)
|
||||
if (pmb_sizes[i].size == size)
|
||||
return pmb_sizes[i].flag;
|
||||
|
||||
return 0;
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static void __pmb_unmap_entry(struct pmb_entry *pmbe, int depth)
|
||||
@ -351,6 +500,8 @@ static void __pmb_unmap_entry(struct pmb_entry *pmbe, int depth)
|
||||
*/
|
||||
__clear_pmb_entry(pmbe);
|
||||
|
||||
flush_cache_vunmap(pmbe->vpn, pmbe->vpn + pmbe->size);
|
||||
|
||||
pmbe = pmblink->link;
|
||||
|
||||
pmb_free(pmblink);
|
||||
@ -369,11 +520,6 @@ static void pmb_unmap_entry(struct pmb_entry *pmbe, int depth)
|
||||
write_unlock_irqrestore(&pmb_rwlock, flags);
|
||||
}
|
||||
|
||||
static __always_inline unsigned int pmb_ppn_in_range(unsigned long ppn)
|
||||
{
|
||||
return ppn >= __pa(memory_start) && ppn < __pa(memory_end);
|
||||
}
|
||||
|
||||
static void __init pmb_notify(void)
|
||||
{
|
||||
int i;
|
||||
@ -625,6 +771,18 @@ static void __init pmb_resize(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
static int __init early_pmb(char *p)
|
||||
{
|
||||
if (!p)
|
||||
return 0;
|
||||
|
||||
if (strstr(p, "iomap"))
|
||||
pmb_iomapping_enabled = 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
early_param("pmb", early_pmb);
|
||||
|
||||
void __init pmb_init(void)
|
||||
{
|
||||
/* Synchronize software state */
|
||||
@ -713,7 +871,7 @@ static int __init pmb_debugfs_init(void)
|
||||
|
||||
return 0;
|
||||
}
|
||||
postcore_initcall(pmb_debugfs_init);
|
||||
subsys_initcall(pmb_debugfs_init);
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int pmb_sysdev_suspend(struct sys_device *dev, pm_message_t state)
|
||||
|
@ -24,8 +24,10 @@
|
||||
#include <linux/delay.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <cpu/dma.h>
|
||||
#include <asm/dma-sh.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
|
||||
#include <asm/dmaengine.h>
|
||||
|
||||
#include "shdma.h"
|
||||
|
||||
/* DMA descriptor control */
|
||||
@ -38,30 +40,32 @@ enum sh_dmae_desc_status {
|
||||
};
|
||||
|
||||
#define NR_DESCS_PER_CHANNEL 32
|
||||
/*
|
||||
* Define the default configuration for dual address memory-memory transfer.
|
||||
* The 0x400 value represents auto-request, external->external.
|
||||
*
|
||||
* And this driver set 4byte burst mode.
|
||||
* If you want to change mode, you need to change RS_DEFAULT of value.
|
||||
* (ex 1byte burst mode -> (RS_DUAL & ~TS_32)
|
||||
*/
|
||||
#define RS_DEFAULT (RS_DUAL)
|
||||
/* Default MEMCPY transfer size = 2^2 = 4 bytes */
|
||||
#define LOG2_DEFAULT_XFER_SIZE 2
|
||||
|
||||
/* A bitmask with bits enough for enum sh_dmae_slave_chan_id */
|
||||
static unsigned long sh_dmae_slave_used[BITS_TO_LONGS(SHDMA_SLAVE_NUMBER)];
|
||||
|
||||
static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all);
|
||||
|
||||
#define SH_DMAC_CHAN_BASE(id) (dma_base_addr[id])
|
||||
static void sh_dmae_writel(struct sh_dmae_chan *sh_dc, u32 data, u32 reg)
|
||||
{
|
||||
ctrl_outl(data, SH_DMAC_CHAN_BASE(sh_dc->id) + reg);
|
||||
__raw_writel(data, sh_dc->base + reg / sizeof(u32));
|
||||
}
|
||||
|
||||
static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
|
||||
{
|
||||
return ctrl_inl(SH_DMAC_CHAN_BASE(sh_dc->id) + reg);
|
||||
return __raw_readl(sh_dc->base + reg / sizeof(u32));
|
||||
}
|
||||
|
||||
static u16 dmaor_read(struct sh_dmae_device *shdev)
|
||||
{
|
||||
return __raw_readw(shdev->chan_reg + DMAOR / sizeof(u32));
|
||||
}
|
||||
|
||||
static void dmaor_write(struct sh_dmae_device *shdev, u16 data)
|
||||
{
|
||||
__raw_writew(data, shdev->chan_reg + DMAOR / sizeof(u32));
|
||||
}
|
||||
|
||||
/*
|
||||
@ -69,24 +73,23 @@ static u32 sh_dmae_readl(struct sh_dmae_chan *sh_dc, u32 reg)
|
||||
*
|
||||
* SH7780 has two DMAOR register
|
||||
*/
|
||||
static void sh_dmae_ctl_stop(int id)
|
||||
static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
|
||||
{
|
||||
unsigned short dmaor = dmaor_read_reg(id);
|
||||
unsigned short dmaor = dmaor_read(shdev);
|
||||
|
||||
dmaor &= ~(DMAOR_NMIF | DMAOR_AE);
|
||||
dmaor_write_reg(id, dmaor);
|
||||
dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
|
||||
}
|
||||
|
||||
static int sh_dmae_rst(int id)
|
||||
static int sh_dmae_rst(struct sh_dmae_device *shdev)
|
||||
{
|
||||
unsigned short dmaor;
|
||||
|
||||
sh_dmae_ctl_stop(id);
|
||||
dmaor = dmaor_read_reg(id) | DMAOR_INIT;
|
||||
sh_dmae_ctl_stop(shdev);
|
||||
dmaor = dmaor_read(shdev) | shdev->pdata->dmaor_init;
|
||||
|
||||
dmaor_write_reg(id, dmaor);
|
||||
if (dmaor_read_reg(id) & (DMAOR_AE | DMAOR_NMIF)) {
|
||||
pr_warning(KERN_ERR "dma-sh: Can't initialize DMAOR.\n");
|
||||
dmaor_write(shdev, dmaor);
|
||||
if (dmaor_read(shdev) & (DMAOR_AE | DMAOR_NMIF)) {
|
||||
pr_warning("dma-sh: Can't initialize DMAOR.\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
return 0;
|
||||
@ -102,13 +105,36 @@ static bool dmae_is_busy(struct sh_dmae_chan *sh_chan)
|
||||
return false; /* waiting */
|
||||
}
|
||||
|
||||
static unsigned int ts_shift[] = TS_SHIFT;
|
||||
static inline unsigned int calc_xmit_shift(u32 chcr)
|
||||
static unsigned int calc_xmit_shift(struct sh_dmae_chan *sh_chan, u32 chcr)
|
||||
{
|
||||
int cnt = ((chcr & CHCR_TS_LOW_MASK) >> CHCR_TS_LOW_SHIFT) |
|
||||
((chcr & CHCR_TS_HIGH_MASK) >> CHCR_TS_HIGH_SHIFT);
|
||||
struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
|
||||
struct sh_dmae_device, common);
|
||||
struct sh_dmae_pdata *pdata = shdev->pdata;
|
||||
int cnt = ((chcr & pdata->ts_low_mask) >> pdata->ts_low_shift) |
|
||||
((chcr & pdata->ts_high_mask) >> pdata->ts_high_shift);
|
||||
|
||||
return ts_shift[cnt];
|
||||
if (cnt >= pdata->ts_shift_num)
|
||||
cnt = 0;
|
||||
|
||||
return pdata->ts_shift[cnt];
|
||||
}
|
||||
|
||||
static u32 log2size_to_chcr(struct sh_dmae_chan *sh_chan, int l2size)
|
||||
{
|
||||
struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
|
||||
struct sh_dmae_device, common);
|
||||
struct sh_dmae_pdata *pdata = shdev->pdata;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < pdata->ts_shift_num; i++)
|
||||
if (pdata->ts_shift[i] == l2size)
|
||||
break;
|
||||
|
||||
if (i == pdata->ts_shift_num)
|
||||
i = 0;
|
||||
|
||||
return ((i << pdata->ts_low_shift) & pdata->ts_low_mask) |
|
||||
((i << pdata->ts_high_shift) & pdata->ts_high_mask);
|
||||
}
|
||||
|
||||
static void dmae_set_reg(struct sh_dmae_chan *sh_chan, struct sh_dmae_regs *hw)
|
||||
@ -136,8 +162,13 @@ static void dmae_halt(struct sh_dmae_chan *sh_chan)
|
||||
|
||||
static void dmae_init(struct sh_dmae_chan *sh_chan)
|
||||
{
|
||||
u32 chcr = RS_DEFAULT; /* default is DUAL mode */
|
||||
sh_chan->xmit_shift = calc_xmit_shift(chcr);
|
||||
/*
|
||||
* Default configuration for dual address memory-memory transfer.
|
||||
* 0x400 represents auto-request.
|
||||
*/
|
||||
u32 chcr = DM_INC | SM_INC | 0x400 | log2size_to_chcr(sh_chan,
|
||||
LOG2_DEFAULT_XFER_SIZE);
|
||||
sh_chan->xmit_shift = calc_xmit_shift(sh_chan, chcr);
|
||||
sh_dmae_writel(sh_chan, chcr, CHCR);
|
||||
}
|
||||
|
||||
@ -147,37 +178,26 @@ static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
|
||||
if (dmae_is_busy(sh_chan))
|
||||
return -EBUSY;
|
||||
|
||||
sh_chan->xmit_shift = calc_xmit_shift(val);
|
||||
sh_chan->xmit_shift = calc_xmit_shift(sh_chan, val);
|
||||
sh_dmae_writel(sh_chan, val, CHCR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define DMARS_SHIFT 8
|
||||
#define DMARS_CHAN_MSK 0x01
|
||||
static int dmae_set_dmars(struct sh_dmae_chan *sh_chan, u16 val)
|
||||
{
|
||||
u32 addr;
|
||||
int shift = 0;
|
||||
struct sh_dmae_device *shdev = container_of(sh_chan->common.device,
|
||||
struct sh_dmae_device, common);
|
||||
struct sh_dmae_pdata *pdata = shdev->pdata;
|
||||
struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id];
|
||||
u16 __iomem *addr = shdev->dmars + chan_pdata->dmars / sizeof(u16);
|
||||
int shift = chan_pdata->dmars_bit;
|
||||
|
||||
if (dmae_is_busy(sh_chan))
|
||||
return -EBUSY;
|
||||
|
||||
if (sh_chan->id & DMARS_CHAN_MSK)
|
||||
shift = DMARS_SHIFT;
|
||||
|
||||
if (sh_chan->id < 6)
|
||||
/* DMA0RS0 - DMA0RS2 */
|
||||
addr = SH_DMARS_BASE0 + (sh_chan->id / 2) * 4;
|
||||
#ifdef SH_DMARS_BASE1
|
||||
else if (sh_chan->id < 12)
|
||||
/* DMA1RS0 - DMA1RS2 */
|
||||
addr = SH_DMARS_BASE1 + ((sh_chan->id - 6) / 2) * 4;
|
||||
#endif
|
||||
else
|
||||
return -EINVAL;
|
||||
|
||||
ctrl_outw((val << shift) | (ctrl_inw(addr) & (0xFF00 >> shift)), addr);
|
||||
__raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
|
||||
addr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -251,15 +271,15 @@ static struct sh_dmae_slave_config *sh_dmae_find_slave(
|
||||
struct dma_device *dma_dev = sh_chan->common.device;
|
||||
struct sh_dmae_device *shdev = container_of(dma_dev,
|
||||
struct sh_dmae_device, common);
|
||||
struct sh_dmae_pdata *pdata = &shdev->pdata;
|
||||
struct sh_dmae_pdata *pdata = shdev->pdata;
|
||||
int i;
|
||||
|
||||
if ((unsigned)slave_id >= SHDMA_SLAVE_NUMBER)
|
||||
return NULL;
|
||||
|
||||
for (i = 0; i < pdata->config_num; i++)
|
||||
if (pdata->config[i].slave_id == slave_id)
|
||||
return pdata->config + i;
|
||||
for (i = 0; i < pdata->slave_num; i++)
|
||||
if (pdata->slave[i].slave_id == slave_id)
|
||||
return pdata->slave + i;
|
||||
|
||||
return NULL;
|
||||
}
|
||||
@ -270,6 +290,8 @@ static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
|
||||
struct sh_desc *desc;
|
||||
struct sh_dmae_slave *param = chan->private;
|
||||
|
||||
pm_runtime_get_sync(sh_chan->dev);
|
||||
|
||||
/*
|
||||
* This relies on the guarantee from dmaengine that alloc_chan_resources
|
||||
* never runs concurrently with itself or free_chan_resources.
|
||||
@ -288,9 +310,8 @@ static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
|
||||
|
||||
dmae_set_dmars(sh_chan, cfg->mid_rid);
|
||||
dmae_set_chcr(sh_chan, cfg->chcr);
|
||||
} else {
|
||||
if ((sh_dmae_readl(sh_chan, CHCR) & 0x700) != 0x400)
|
||||
dmae_set_chcr(sh_chan, RS_DEFAULT);
|
||||
} else if ((sh_dmae_readl(sh_chan, CHCR) & 0xf00) != 0x400) {
|
||||
dmae_init(sh_chan);
|
||||
}
|
||||
|
||||
spin_lock_bh(&sh_chan->desc_lock);
|
||||
@ -312,6 +333,9 @@ static int sh_dmae_alloc_chan_resources(struct dma_chan *chan)
|
||||
}
|
||||
spin_unlock_bh(&sh_chan->desc_lock);
|
||||
|
||||
if (!sh_chan->descs_allocated)
|
||||
pm_runtime_put(sh_chan->dev);
|
||||
|
||||
return sh_chan->descs_allocated;
|
||||
}
|
||||
|
||||
@ -323,6 +347,7 @@ static void sh_dmae_free_chan_resources(struct dma_chan *chan)
|
||||
struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
|
||||
struct sh_desc *desc, *_desc;
|
||||
LIST_HEAD(list);
|
||||
int descs = sh_chan->descs_allocated;
|
||||
|
||||
dmae_halt(sh_chan);
|
||||
|
||||
@ -343,6 +368,9 @@ static void sh_dmae_free_chan_resources(struct dma_chan *chan)
|
||||
|
||||
spin_unlock_bh(&sh_chan->desc_lock);
|
||||
|
||||
if (descs > 0)
|
||||
pm_runtime_put(sh_chan->dev);
|
||||
|
||||
list_for_each_entry_safe(desc, _desc, &list, node)
|
||||
kfree(desc);
|
||||
}
|
||||
@ -559,6 +587,19 @@ static void sh_dmae_terminate_all(struct dma_chan *chan)
|
||||
if (!chan)
|
||||
return;
|
||||
|
||||
dmae_halt(sh_chan);
|
||||
|
||||
spin_lock_bh(&sh_chan->desc_lock);
|
||||
if (!list_empty(&sh_chan->ld_queue)) {
|
||||
/* Record partial transfer */
|
||||
struct sh_desc *desc = list_entry(sh_chan->ld_queue.next,
|
||||
struct sh_desc, node);
|
||||
desc->partial = (desc->hw.tcr - sh_dmae_readl(sh_chan, TCR)) <<
|
||||
sh_chan->xmit_shift;
|
||||
|
||||
}
|
||||
spin_unlock_bh(&sh_chan->desc_lock);
|
||||
|
||||
sh_dmae_chan_ld_cleanup(sh_chan, true);
|
||||
}
|
||||
|
||||
@ -661,7 +702,7 @@ static void sh_dmae_chan_ld_cleanup(struct sh_dmae_chan *sh_chan, bool all)
|
||||
|
||||
static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
|
||||
{
|
||||
struct sh_desc *sd;
|
||||
struct sh_desc *desc;
|
||||
|
||||
spin_lock_bh(&sh_chan->desc_lock);
|
||||
/* DMA work check */
|
||||
@ -671,10 +712,13 @@ static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
|
||||
}
|
||||
|
||||
/* Find the first not transferred desciptor */
|
||||
list_for_each_entry(sd, &sh_chan->ld_queue, node)
|
||||
if (sd->mark == DESC_SUBMITTED) {
|
||||
list_for_each_entry(desc, &sh_chan->ld_queue, node)
|
||||
if (desc->mark == DESC_SUBMITTED) {
|
||||
dev_dbg(sh_chan->dev, "Queue #%d to %d: %u@%x -> %x\n",
|
||||
desc->async_tx.cookie, sh_chan->id,
|
||||
desc->hw.tcr, desc->hw.sar, desc->hw.dar);
|
||||
/* Get the ld start address from ld_queue */
|
||||
dmae_set_reg(sh_chan, &sd->hw);
|
||||
dmae_set_reg(sh_chan, &desc->hw);
|
||||
dmae_start(sh_chan);
|
||||
break;
|
||||
}
|
||||
@ -696,6 +740,7 @@ static enum dma_status sh_dmae_is_complete(struct dma_chan *chan,
|
||||
struct sh_dmae_chan *sh_chan = to_sh_chan(chan);
|
||||
dma_cookie_t last_used;
|
||||
dma_cookie_t last_complete;
|
||||
enum dma_status status;
|
||||
|
||||
sh_dmae_chan_ld_cleanup(sh_chan, false);
|
||||
|
||||
@ -709,7 +754,27 @@ static enum dma_status sh_dmae_is_complete(struct dma_chan *chan,
|
||||
if (used)
|
||||
*used = last_used;
|
||||
|
||||
return dma_async_is_complete(cookie, last_complete, last_used);
|
||||
spin_lock_bh(&sh_chan->desc_lock);
|
||||
|
||||
status = dma_async_is_complete(cookie, last_complete, last_used);
|
||||
|
||||
/*
|
||||
* If we don't find cookie on the queue, it has been aborted and we have
|
||||
* to report error
|
||||
*/
|
||||
if (status != DMA_SUCCESS) {
|
||||
struct sh_desc *desc;
|
||||
status = DMA_ERROR;
|
||||
list_for_each_entry(desc, &sh_chan->ld_queue, node)
|
||||
if (desc->cookie == cookie) {
|
||||
status = DMA_IN_PROGRESS;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
spin_unlock_bh(&sh_chan->desc_lock);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static irqreturn_t sh_dmae_interrupt(int irq, void *data)
|
||||
@ -732,40 +797,32 @@ static irqreturn_t sh_dmae_interrupt(int irq, void *data)
|
||||
#if defined(CONFIG_CPU_SH4)
|
||||
static irqreturn_t sh_dmae_err(int irq, void *data)
|
||||
{
|
||||
int err = 0;
|
||||
struct sh_dmae_device *shdev = (struct sh_dmae_device *)data;
|
||||
int i;
|
||||
|
||||
/* IRQ Multi */
|
||||
if (shdev->pdata.mode & SHDMA_MIX_IRQ) {
|
||||
int __maybe_unused cnt = 0;
|
||||
switch (irq) {
|
||||
#if defined(DMTE6_IRQ) && defined(DMAE1_IRQ)
|
||||
case DMTE6_IRQ:
|
||||
cnt++;
|
||||
#endif
|
||||
case DMTE0_IRQ:
|
||||
if (dmaor_read_reg(cnt) & (DMAOR_NMIF | DMAOR_AE)) {
|
||||
disable_irq(irq);
|
||||
return IRQ_HANDLED;
|
||||
/* halt the dma controller */
|
||||
sh_dmae_ctl_stop(shdev);
|
||||
|
||||
/* We cannot detect, which channel caused the error, have to reset all */
|
||||
for (i = 0; i < SH_DMAC_MAX_CHANNELS; i++) {
|
||||
struct sh_dmae_chan *sh_chan = shdev->chan[i];
|
||||
if (sh_chan) {
|
||||
struct sh_desc *desc;
|
||||
/* Stop the channel */
|
||||
dmae_halt(sh_chan);
|
||||
/* Complete all */
|
||||
list_for_each_entry(desc, &sh_chan->ld_queue, node) {
|
||||
struct dma_async_tx_descriptor *tx = &desc->async_tx;
|
||||
desc->mark = DESC_IDLE;
|
||||
if (tx->callback)
|
||||
tx->callback(tx->callback_param);
|
||||
}
|
||||
default:
|
||||
return IRQ_NONE;
|
||||
list_splice_init(&sh_chan->ld_queue, &sh_chan->ld_free);
|
||||
}
|
||||
} else {
|
||||
/* reset dma controller */
|
||||
err = sh_dmae_rst(0);
|
||||
if (err)
|
||||
return err;
|
||||
#ifdef SH_DMAC_BASE1
|
||||
if (shdev->pdata.mode & SHDMA_DMAOR1) {
|
||||
err = sh_dmae_rst(1);
|
||||
if (err)
|
||||
return err;
|
||||
}
|
||||
#endif
|
||||
disable_irq(irq);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
sh_dmae_rst(shdev);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -796,19 +853,12 @@ static void dmae_do_tasklet(unsigned long data)
|
||||
sh_dmae_chan_ld_cleanup(sh_chan, false);
|
||||
}
|
||||
|
||||
static unsigned int get_dmae_irq(unsigned int id)
|
||||
{
|
||||
unsigned int irq = 0;
|
||||
if (id < ARRAY_SIZE(dmte_irq_map))
|
||||
irq = dmte_irq_map[id];
|
||||
return irq;
|
||||
}
|
||||
|
||||
static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id)
|
||||
static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id,
|
||||
int irq, unsigned long flags)
|
||||
{
|
||||
int err;
|
||||
unsigned int irq = get_dmae_irq(id);
|
||||
unsigned long irqflags = IRQF_DISABLED;
|
||||
struct sh_dmae_channel *chan_pdata = &shdev->pdata->channel[id];
|
||||
struct platform_device *pdev = to_platform_device(shdev->common.dev);
|
||||
struct sh_dmae_chan *new_sh_chan;
|
||||
|
||||
/* alloc channel */
|
||||
@ -819,8 +869,13 @@ static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* copy struct dma_device */
|
||||
new_sh_chan->common.device = &shdev->common;
|
||||
|
||||
new_sh_chan->dev = shdev->common.dev;
|
||||
new_sh_chan->id = id;
|
||||
new_sh_chan->irq = irq;
|
||||
new_sh_chan->base = shdev->chan_reg + chan_pdata->offset / sizeof(u32);
|
||||
|
||||
/* Init DMA tasklet */
|
||||
tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet,
|
||||
@ -835,29 +890,20 @@ static int __devinit sh_dmae_chan_probe(struct sh_dmae_device *shdev, int id)
|
||||
INIT_LIST_HEAD(&new_sh_chan->ld_queue);
|
||||
INIT_LIST_HEAD(&new_sh_chan->ld_free);
|
||||
|
||||
/* copy struct dma_device */
|
||||
new_sh_chan->common.device = &shdev->common;
|
||||
|
||||
/* Add the channel to DMA device channel list */
|
||||
list_add_tail(&new_sh_chan->common.device_node,
|
||||
&shdev->common.channels);
|
||||
shdev->common.chancnt++;
|
||||
|
||||
if (shdev->pdata.mode & SHDMA_MIX_IRQ) {
|
||||
irqflags = IRQF_SHARED;
|
||||
#if defined(DMTE6_IRQ)
|
||||
if (irq >= DMTE6_IRQ)
|
||||
irq = DMTE6_IRQ;
|
||||
else
|
||||
#endif
|
||||
irq = DMTE0_IRQ;
|
||||
}
|
||||
|
||||
snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
|
||||
"sh-dmae%d", new_sh_chan->id);
|
||||
if (pdev->id >= 0)
|
||||
snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
|
||||
"sh-dmae%d.%d", pdev->id, new_sh_chan->id);
|
||||
else
|
||||
snprintf(new_sh_chan->dev_id, sizeof(new_sh_chan->dev_id),
|
||||
"sh-dma%d", new_sh_chan->id);
|
||||
|
||||
/* set up channel irq */
|
||||
err = request_irq(irq, &sh_dmae_interrupt, irqflags,
|
||||
err = request_irq(irq, &sh_dmae_interrupt, flags,
|
||||
new_sh_chan->dev_id, new_sh_chan);
|
||||
if (err) {
|
||||
dev_err(shdev->common.dev, "DMA channel %d request_irq error "
|
||||
@ -881,12 +927,12 @@ static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
|
||||
|
||||
for (i = shdev->common.chancnt - 1 ; i >= 0 ; i--) {
|
||||
if (shdev->chan[i]) {
|
||||
struct sh_dmae_chan *shchan = shdev->chan[i];
|
||||
if (!(shdev->pdata.mode & SHDMA_MIX_IRQ))
|
||||
free_irq(dmte_irq_map[i], shchan);
|
||||
struct sh_dmae_chan *sh_chan = shdev->chan[i];
|
||||
|
||||
list_del(&shchan->common.device_node);
|
||||
kfree(shchan);
|
||||
free_irq(sh_chan->irq, sh_chan);
|
||||
|
||||
list_del(&sh_chan->common.device_node);
|
||||
kfree(sh_chan);
|
||||
shdev->chan[i] = NULL;
|
||||
}
|
||||
}
|
||||
@ -895,47 +941,84 @@ static void sh_dmae_chan_remove(struct sh_dmae_device *shdev)
|
||||
|
||||
static int __init sh_dmae_probe(struct platform_device *pdev)
|
||||
{
|
||||
int err = 0, cnt, ecnt;
|
||||
unsigned long irqflags = IRQF_DISABLED;
|
||||
#if defined(CONFIG_CPU_SH4)
|
||||
int eirq[] = { DMAE0_IRQ,
|
||||
#if defined(DMAE1_IRQ)
|
||||
DMAE1_IRQ
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
struct sh_dmae_pdata *pdata = pdev->dev.platform_data;
|
||||
unsigned long irqflags = IRQF_DISABLED,
|
||||
chan_flag[SH_DMAC_MAX_CHANNELS] = {};
|
||||
int errirq, chan_irq[SH_DMAC_MAX_CHANNELS];
|
||||
int err, i, irq_cnt = 0, irqres = 0;
|
||||
struct sh_dmae_device *shdev;
|
||||
struct resource *chan, *dmars, *errirq_res, *chanirq_res;
|
||||
|
||||
/* get platform data */
|
||||
if (!pdev->dev.platform_data)
|
||||
if (!pdata || !pdata->channel_num)
|
||||
return -ENODEV;
|
||||
|
||||
chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
/* DMARS area is optional, if absent, this controller cannot do slave DMA */
|
||||
dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
/*
|
||||
* IRQ resources:
|
||||
* 1. there always must be at least one IRQ IO-resource. On SH4 it is
|
||||
* the error IRQ, in which case it is the only IRQ in this resource:
|
||||
* start == end. If it is the only IRQ resource, all channels also
|
||||
* use the same IRQ.
|
||||
* 2. DMA channel IRQ resources can be specified one per resource or in
|
||||
* ranges (start != end)
|
||||
* 3. iff all events (channels and, optionally, error) on this
|
||||
* controller use the same IRQ, only one IRQ resource can be
|
||||
* specified, otherwise there must be one IRQ per channel, even if
|
||||
* some of them are equal
|
||||
* 4. if all IRQs on this controller are equal or if some specific IRQs
|
||||
* specify IORESOURCE_IRQ_SHAREABLE in their resources, they will be
|
||||
* requested with the IRQF_SHARED flag
|
||||
*/
|
||||
errirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (!chan || !errirq_res)
|
||||
return -ENODEV;
|
||||
|
||||
if (!request_mem_region(chan->start, resource_size(chan), pdev->name)) {
|
||||
dev_err(&pdev->dev, "DMAC register region already claimed\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
if (dmars && !request_mem_region(dmars->start, resource_size(dmars), pdev->name)) {
|
||||
dev_err(&pdev->dev, "DMAC DMARS region already claimed\n");
|
||||
err = -EBUSY;
|
||||
goto ermrdmars;
|
||||
}
|
||||
|
||||
err = -ENOMEM;
|
||||
shdev = kzalloc(sizeof(struct sh_dmae_device), GFP_KERNEL);
|
||||
if (!shdev) {
|
||||
dev_err(&pdev->dev, "No enough memory\n");
|
||||
return -ENOMEM;
|
||||
dev_err(&pdev->dev, "Not enough memory\n");
|
||||
goto ealloc;
|
||||
}
|
||||
|
||||
shdev->chan_reg = ioremap(chan->start, resource_size(chan));
|
||||
if (!shdev->chan_reg)
|
||||
goto emapchan;
|
||||
if (dmars) {
|
||||
shdev->dmars = ioremap(dmars->start, resource_size(dmars));
|
||||
if (!shdev->dmars)
|
||||
goto emapdmars;
|
||||
}
|
||||
|
||||
/* platform data */
|
||||
memcpy(&shdev->pdata, pdev->dev.platform_data,
|
||||
sizeof(struct sh_dmae_pdata));
|
||||
shdev->pdata = pdata;
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
pm_runtime_get_sync(&pdev->dev);
|
||||
|
||||
/* reset dma controller */
|
||||
err = sh_dmae_rst(0);
|
||||
err = sh_dmae_rst(shdev);
|
||||
if (err)
|
||||
goto rst_err;
|
||||
|
||||
/* SH7780/85/23 has DMAOR1 */
|
||||
if (shdev->pdata.mode & SHDMA_DMAOR1) {
|
||||
err = sh_dmae_rst(1);
|
||||
if (err)
|
||||
goto rst_err;
|
||||
}
|
||||
|
||||
INIT_LIST_HEAD(&shdev->common.channels);
|
||||
|
||||
dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask);
|
||||
dma_cap_set(DMA_SLAVE, shdev->common.cap_mask);
|
||||
if (dmars)
|
||||
dma_cap_set(DMA_SLAVE, shdev->common.cap_mask);
|
||||
|
||||
shdev->common.device_alloc_chan_resources
|
||||
= sh_dmae_alloc_chan_resources;
|
||||
@ -950,37 +1033,72 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
|
||||
|
||||
shdev->common.dev = &pdev->dev;
|
||||
/* Default transfer size of 32 bytes requires 32-byte alignment */
|
||||
shdev->common.copy_align = 5;
|
||||
shdev->common.copy_align = LOG2_DEFAULT_XFER_SIZE;
|
||||
|
||||
#if defined(CONFIG_CPU_SH4)
|
||||
/* Non Mix IRQ mode SH7722/SH7730 etc... */
|
||||
if (shdev->pdata.mode & SHDMA_MIX_IRQ) {
|
||||
chanirq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
|
||||
|
||||
if (!chanirq_res)
|
||||
chanirq_res = errirq_res;
|
||||
else
|
||||
irqres++;
|
||||
|
||||
if (chanirq_res == errirq_res ||
|
||||
(errirq_res->flags & IORESOURCE_BITS) == IORESOURCE_IRQ_SHAREABLE)
|
||||
irqflags = IRQF_SHARED;
|
||||
eirq[0] = DMTE0_IRQ;
|
||||
#if defined(DMTE6_IRQ) && defined(DMAE1_IRQ)
|
||||
eirq[1] = DMTE6_IRQ;
|
||||
#endif
|
||||
|
||||
errirq = errirq_res->start;
|
||||
|
||||
err = request_irq(errirq, sh_dmae_err, irqflags,
|
||||
"DMAC Address Error", shdev);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev,
|
||||
"DMA failed requesting irq #%d, error %d\n",
|
||||
errirq, err);
|
||||
goto eirq_err;
|
||||
}
|
||||
|
||||
for (ecnt = 0 ; ecnt < ARRAY_SIZE(eirq); ecnt++) {
|
||||
err = request_irq(eirq[ecnt], sh_dmae_err, irqflags,
|
||||
"DMAC Address Error", shdev);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "DMA device request_irq"
|
||||
"error (irq %d) with return %d\n",
|
||||
eirq[ecnt], err);
|
||||
goto eirq_err;
|
||||
}
|
||||
}
|
||||
#else
|
||||
chanirq_res = errirq_res;
|
||||
#endif /* CONFIG_CPU_SH4 */
|
||||
|
||||
if (chanirq_res->start == chanirq_res->end &&
|
||||
!platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
|
||||
/* Special case - all multiplexed */
|
||||
for (; irq_cnt < pdata->channel_num; irq_cnt++) {
|
||||
chan_irq[irq_cnt] = chanirq_res->start;
|
||||
chan_flag[irq_cnt] = IRQF_SHARED;
|
||||
}
|
||||
} else {
|
||||
do {
|
||||
for (i = chanirq_res->start; i <= chanirq_res->end; i++) {
|
||||
if ((errirq_res->flags & IORESOURCE_BITS) ==
|
||||
IORESOURCE_IRQ_SHAREABLE)
|
||||
chan_flag[irq_cnt] = IRQF_SHARED;
|
||||
else
|
||||
chan_flag[irq_cnt] = IRQF_DISABLED;
|
||||
dev_dbg(&pdev->dev,
|
||||
"Found IRQ %d for channel %d\n",
|
||||
i, irq_cnt);
|
||||
chan_irq[irq_cnt++] = i;
|
||||
}
|
||||
chanirq_res = platform_get_resource(pdev,
|
||||
IORESOURCE_IRQ, ++irqres);
|
||||
} while (irq_cnt < pdata->channel_num && chanirq_res);
|
||||
}
|
||||
|
||||
if (irq_cnt < pdata->channel_num)
|
||||
goto eirqres;
|
||||
|
||||
/* Create DMA Channel */
|
||||
for (cnt = 0 ; cnt < MAX_DMA_CHANNELS ; cnt++) {
|
||||
err = sh_dmae_chan_probe(shdev, cnt);
|
||||
for (i = 0; i < pdata->channel_num; i++) {
|
||||
err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
|
||||
if (err)
|
||||
goto chan_probe_err;
|
||||
}
|
||||
|
||||
pm_runtime_put(&pdev->dev);
|
||||
|
||||
platform_set_drvdata(pdev, shdev);
|
||||
dma_async_device_register(&shdev->common);
|
||||
|
||||
@ -988,13 +1106,24 @@ static int __init sh_dmae_probe(struct platform_device *pdev)
|
||||
|
||||
chan_probe_err:
|
||||
sh_dmae_chan_remove(shdev);
|
||||
|
||||
eirqres:
|
||||
#if defined(CONFIG_CPU_SH4)
|
||||
free_irq(errirq, shdev);
|
||||
eirq_err:
|
||||
for (ecnt-- ; ecnt >= 0; ecnt--)
|
||||
free_irq(eirq[ecnt], shdev);
|
||||
|
||||
#endif
|
||||
rst_err:
|
||||
pm_runtime_put(&pdev->dev);
|
||||
if (dmars)
|
||||
iounmap(shdev->dmars);
|
||||
emapdmars:
|
||||
iounmap(shdev->chan_reg);
|
||||
emapchan:
|
||||
kfree(shdev);
|
||||
ealloc:
|
||||
if (dmars)
|
||||
release_mem_region(dmars->start, resource_size(dmars));
|
||||
ermrdmars:
|
||||
release_mem_region(chan->start, resource_size(chan));
|
||||
|
||||
return err;
|
||||
}
|
||||
@ -1002,36 +1131,39 @@ rst_err:
|
||||
static int __exit sh_dmae_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
|
||||
struct resource *res;
|
||||
int errirq = platform_get_irq(pdev, 0);
|
||||
|
||||
dma_async_device_unregister(&shdev->common);
|
||||
|
||||
if (shdev->pdata.mode & SHDMA_MIX_IRQ) {
|
||||
free_irq(DMTE0_IRQ, shdev);
|
||||
#if defined(DMTE6_IRQ)
|
||||
free_irq(DMTE6_IRQ, shdev);
|
||||
#endif
|
||||
}
|
||||
if (errirq > 0)
|
||||
free_irq(errirq, shdev);
|
||||
|
||||
/* channel data remove */
|
||||
sh_dmae_chan_remove(shdev);
|
||||
|
||||
if (!(shdev->pdata.mode & SHDMA_MIX_IRQ)) {
|
||||
free_irq(DMAE0_IRQ, shdev);
|
||||
#if defined(DMAE1_IRQ)
|
||||
free_irq(DMAE1_IRQ, shdev);
|
||||
#endif
|
||||
}
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
if (shdev->dmars)
|
||||
iounmap(shdev->dmars);
|
||||
iounmap(shdev->chan_reg);
|
||||
|
||||
kfree(shdev);
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (res)
|
||||
release_mem_region(res->start, resource_size(res));
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
|
||||
if (res)
|
||||
release_mem_region(res->start, resource_size(res));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void sh_dmae_shutdown(struct platform_device *pdev)
|
||||
{
|
||||
struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
|
||||
sh_dmae_ctl_stop(0);
|
||||
if (shdev->pdata.mode & SHDMA_DMAOR1)
|
||||
sh_dmae_ctl_stop(1);
|
||||
sh_dmae_ctl_stop(shdev);
|
||||
}
|
||||
|
||||
static struct platform_driver sh_dmae_driver = {
|
||||
|
@ -17,24 +17,10 @@
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/list.h>
|
||||
|
||||
#include <asm/dmaengine.h>
|
||||
|
||||
#define SH_DMA_TCR_MAX 0x00FFFFFF /* 16MB */
|
||||
|
||||
struct sh_dmae_regs {
|
||||
u32 sar; /* SAR / source address */
|
||||
u32 dar; /* DAR / destination address */
|
||||
u32 tcr; /* TCR / transfer count */
|
||||
};
|
||||
|
||||
struct sh_desc {
|
||||
struct sh_dmae_regs hw;
|
||||
struct list_head node;
|
||||
struct dma_async_tx_descriptor async_tx;
|
||||
enum dma_data_direction direction;
|
||||
dma_cookie_t cookie;
|
||||
int chunks;
|
||||
int mark;
|
||||
};
|
||||
|
||||
struct device;
|
||||
|
||||
struct sh_dmae_chan {
|
||||
@ -47,14 +33,18 @@ struct sh_dmae_chan {
|
||||
struct tasklet_struct tasklet; /* Tasklet */
|
||||
int descs_allocated; /* desc count */
|
||||
int xmit_shift; /* log_2(bytes_per_xfer) */
|
||||
int irq;
|
||||
int id; /* Raw id of this channel */
|
||||
u32 __iomem *base;
|
||||
char dev_id[16]; /* unique name per DMAC of channel */
|
||||
};
|
||||
|
||||
struct sh_dmae_device {
|
||||
struct dma_device common;
|
||||
struct sh_dmae_chan *chan[MAX_DMA_CHANNELS];
|
||||
struct sh_dmae_pdata pdata;
|
||||
struct sh_dmae_chan *chan[SH_DMAC_MAX_CHANNELS];
|
||||
struct sh_dmae_pdata *pdata;
|
||||
u32 __iomem *chan_reg;
|
||||
u16 __iomem *dmars;
|
||||
};
|
||||
|
||||
#define to_sh_chan(chan) container_of(chan, struct sh_dmae_chan, common)
|
||||
|
@ -1009,6 +1009,10 @@ config SERIAL_SH_SCI_CONSOLE
|
||||
depends on SERIAL_SH_SCI=y
|
||||
select SERIAL_CORE_CONSOLE
|
||||
|
||||
config SERIAL_SH_SCI_DMA
|
||||
bool "DMA support"
|
||||
depends on SERIAL_SH_SCI && SH_DMAE && EXPERIMENTAL
|
||||
|
||||
config SERIAL_PNX8XXX
|
||||
bool "Enable PNX8XXX SoCs' UART Support"
|
||||
depends on MIPS && (SOC_PNX8550 || SOC_PNX833X)
|
||||
|
@ -48,6 +48,9 @@
|
||||
#include <linux/ctype.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/scatterlist.h>
|
||||
#include <linux/timer.h>
|
||||
|
||||
#ifdef CONFIG_SUPERH
|
||||
#include <asm/sh_bios.h>
|
||||
@ -84,6 +87,27 @@ struct sci_port {
|
||||
struct clk *dclk;
|
||||
|
||||
struct list_head node;
|
||||
struct dma_chan *chan_tx;
|
||||
struct dma_chan *chan_rx;
|
||||
#ifdef CONFIG_SERIAL_SH_SCI_DMA
|
||||
struct device *dma_dev;
|
||||
enum sh_dmae_slave_chan_id slave_tx;
|
||||
enum sh_dmae_slave_chan_id slave_rx;
|
||||
struct dma_async_tx_descriptor *desc_tx;
|
||||
struct dma_async_tx_descriptor *desc_rx[2];
|
||||
dma_cookie_t cookie_tx;
|
||||
dma_cookie_t cookie_rx[2];
|
||||
dma_cookie_t active_rx;
|
||||
struct scatterlist sg_tx;
|
||||
unsigned int sg_len_tx;
|
||||
struct scatterlist sg_rx[2];
|
||||
size_t buf_len_rx;
|
||||
struct sh_dmae_slave param_tx;
|
||||
struct sh_dmae_slave param_rx;
|
||||
struct work_struct work_tx;
|
||||
struct work_struct work_rx;
|
||||
struct timer_list rx_timer;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct sh_sci_priv {
|
||||
@ -269,29 +293,44 @@ static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7785) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7786)
|
||||
static inline int scif_txroom(struct uart_port *port)
|
||||
static int scif_txfill(struct uart_port *port)
|
||||
{
|
||||
return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
|
||||
return sci_in(port, SCTFDR) & 0xff;
|
||||
}
|
||||
|
||||
static inline int scif_rxroom(struct uart_port *port)
|
||||
static int scif_txroom(struct uart_port *port)
|
||||
{
|
||||
return SCIF_TXROOM_MAX - scif_txfill(port);
|
||||
}
|
||||
|
||||
static int scif_rxfill(struct uart_port *port)
|
||||
{
|
||||
return sci_in(port, SCRFDR) & 0xff;
|
||||
}
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
|
||||
static inline int scif_txroom(struct uart_port *port)
|
||||
static int scif_txfill(struct uart_port *port)
|
||||
{
|
||||
if ((port->mapbase == 0xffe00000) ||
|
||||
(port->mapbase == 0xffe08000)) {
|
||||
if (port->mapbase == 0xffe00000 ||
|
||||
port->mapbase == 0xffe08000)
|
||||
/* SCIF0/1*/
|
||||
return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);
|
||||
} else {
|
||||
return sci_in(port, SCTFDR) & 0xff;
|
||||
else
|
||||
/* SCIF2 */
|
||||
return SCIF2_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
|
||||
}
|
||||
return sci_in(port, SCFDR) >> 8;
|
||||
}
|
||||
|
||||
static inline int scif_rxroom(struct uart_port *port)
|
||||
static int scif_txroom(struct uart_port *port)
|
||||
{
|
||||
if (port->mapbase == 0xffe00000 ||
|
||||
port->mapbase == 0xffe08000)
|
||||
/* SCIF0/1*/
|
||||
return SCIF_TXROOM_MAX - scif_txfill(port);
|
||||
else
|
||||
/* SCIF2 */
|
||||
return SCIF2_TXROOM_MAX - scif_txfill(port);
|
||||
}
|
||||
|
||||
static int scif_rxfill(struct uart_port *port)
|
||||
{
|
||||
if ((port->mapbase == 0xffe00000) ||
|
||||
(port->mapbase == 0xffe08000)) {
|
||||
@ -303,23 +342,33 @@ static inline int scif_rxroom(struct uart_port *port)
|
||||
}
|
||||
}
|
||||
#else
|
||||
static inline int scif_txroom(struct uart_port *port)
|
||||
static int scif_txfill(struct uart_port *port)
|
||||
{
|
||||
return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8);
|
||||
return sci_in(port, SCFDR) >> 8;
|
||||
}
|
||||
|
||||
static inline int scif_rxroom(struct uart_port *port)
|
||||
static int scif_txroom(struct uart_port *port)
|
||||
{
|
||||
return SCIF_TXROOM_MAX - scif_txfill(port);
|
||||
}
|
||||
|
||||
static int scif_rxfill(struct uart_port *port)
|
||||
{
|
||||
return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline int sci_txroom(struct uart_port *port)
|
||||
static int sci_txfill(struct uart_port *port)
|
||||
{
|
||||
return (sci_in(port, SCxSR) & SCI_TDRE) != 0;
|
||||
return !(sci_in(port, SCxSR) & SCI_TDRE);
|
||||
}
|
||||
|
||||
static inline int sci_rxroom(struct uart_port *port)
|
||||
static int sci_txroom(struct uart_port *port)
|
||||
{
|
||||
return !sci_txfill(port);
|
||||
}
|
||||
|
||||
static int sci_rxfill(struct uart_port *port)
|
||||
{
|
||||
return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
|
||||
}
|
||||
@ -406,9 +455,9 @@ static inline void sci_receive_chars(struct uart_port *port)
|
||||
|
||||
while (1) {
|
||||
if (port->type == PORT_SCI)
|
||||
count = sci_rxroom(port);
|
||||
count = sci_rxfill(port);
|
||||
else
|
||||
count = scif_rxroom(port);
|
||||
count = scif_rxfill(port);
|
||||
|
||||
/* Don't copy more bytes than there is room for in the buffer */
|
||||
count = tty_buffer_request_room(tty, count);
|
||||
@ -453,10 +502,10 @@ static inline void sci_receive_chars(struct uart_port *port)
|
||||
}
|
||||
|
||||
/* Store data and status */
|
||||
if (status&SCxSR_FER(port)) {
|
||||
if (status & SCxSR_FER(port)) {
|
||||
flag = TTY_FRAME;
|
||||
dev_notice(port->dev, "frame error\n");
|
||||
} else if (status&SCxSR_PER(port)) {
|
||||
} else if (status & SCxSR_PER(port)) {
|
||||
flag = TTY_PARITY;
|
||||
dev_notice(port->dev, "parity error\n");
|
||||
} else
|
||||
@ -618,13 +667,39 @@ static inline int sci_handle_breaks(struct uart_port *port)
|
||||
return copied;
|
||||
}
|
||||
|
||||
static irqreturn_t sci_rx_interrupt(int irq, void *port)
|
||||
static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
|
||||
{
|
||||
#ifdef CONFIG_SERIAL_SH_SCI_DMA
|
||||
struct uart_port *port = ptr;
|
||||
struct sci_port *s = to_sci_port(port);
|
||||
|
||||
if (s->chan_rx) {
|
||||
unsigned long tout;
|
||||
u16 scr = sci_in(port, SCSCR);
|
||||
u16 ssr = sci_in(port, SCxSR);
|
||||
|
||||
/* Disable future Rx interrupts */
|
||||
sci_out(port, SCSCR, scr & ~SCI_CTRL_FLAGS_RIE);
|
||||
/* Clear current interrupt */
|
||||
sci_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
|
||||
/* Calculate delay for 1.5 DMA buffers */
|
||||
tout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
|
||||
port->fifosize / 2;
|
||||
dev_dbg(port->dev, "Rx IRQ: setup timeout in %lu ms\n",
|
||||
tout * 1000 / HZ);
|
||||
if (tout < 2)
|
||||
tout = 2;
|
||||
mod_timer(&s->rx_timer, jiffies + tout);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* I think sci_receive_chars has to be called irrespective
|
||||
* of whether the I_IXOFF is set, otherwise, how is the interrupt
|
||||
* to be disabled?
|
||||
*/
|
||||
sci_receive_chars(port);
|
||||
sci_receive_chars(ptr);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
@ -680,6 +755,7 @@ static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
|
||||
{
|
||||
unsigned short ssr_status, scr_status, err_enabled;
|
||||
struct uart_port *port = ptr;
|
||||
struct sci_port *s = to_sci_port(port);
|
||||
irqreturn_t ret = IRQ_NONE;
|
||||
|
||||
ssr_status = sci_in(port, SCxSR);
|
||||
@ -687,10 +763,15 @@ static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
|
||||
err_enabled = scr_status & (SCI_CTRL_FLAGS_REIE | SCI_CTRL_FLAGS_RIE);
|
||||
|
||||
/* Tx Interrupt */
|
||||
if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCI_CTRL_FLAGS_TIE))
|
||||
if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCI_CTRL_FLAGS_TIE) &&
|
||||
!s->chan_tx)
|
||||
ret = sci_tx_interrupt(irq, ptr);
|
||||
/* Rx Interrupt */
|
||||
if ((ssr_status & SCxSR_RDxF(port)) && (scr_status & SCI_CTRL_FLAGS_RIE))
|
||||
/*
|
||||
* Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
|
||||
* DR flags
|
||||
*/
|
||||
if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
|
||||
(scr_status & SCI_CTRL_FLAGS_RIE))
|
||||
ret = sci_rx_interrupt(irq, ptr);
|
||||
/* Error Interrupt */
|
||||
if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
|
||||
@ -699,6 +780,10 @@ static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
|
||||
if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
|
||||
ret = sci_br_interrupt(irq, ptr);
|
||||
|
||||
WARN_ONCE(ret == IRQ_NONE,
|
||||
"%s: %d IRQ %d, status %x, control %x\n", __func__,
|
||||
irq, port->line, ssr_status, scr_status);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -800,7 +885,9 @@ static void sci_free_irq(struct sci_port *port)
|
||||
static unsigned int sci_tx_empty(struct uart_port *port)
|
||||
{
|
||||
unsigned short status = sci_in(port, SCxSR);
|
||||
return status & SCxSR_TEND(port) ? TIOCSER_TEMT : 0;
|
||||
unsigned short in_tx_fifo = scif_txfill(port);
|
||||
|
||||
return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
|
||||
}
|
||||
|
||||
static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
|
||||
@ -812,16 +899,297 @@ static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
|
||||
|
||||
static unsigned int sci_get_mctrl(struct uart_port *port)
|
||||
{
|
||||
/* This routine is used for geting signals of: DTR, DCD, DSR, RI,
|
||||
/* This routine is used for getting signals of: DTR, DCD, DSR, RI,
|
||||
and CTS/RTS */
|
||||
|
||||
return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SERIAL_SH_SCI_DMA
|
||||
static void sci_dma_tx_complete(void *arg)
|
||||
{
|
||||
struct sci_port *s = arg;
|
||||
struct uart_port *port = &s->port;
|
||||
struct circ_buf *xmit = &port->state->xmit;
|
||||
unsigned long flags;
|
||||
|
||||
dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
|
||||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
xmit->tail += s->sg_tx.length;
|
||||
xmit->tail &= UART_XMIT_SIZE - 1;
|
||||
|
||||
port->icount.tx += s->sg_tx.length;
|
||||
|
||||
async_tx_ack(s->desc_tx);
|
||||
s->cookie_tx = -EINVAL;
|
||||
s->desc_tx = NULL;
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
|
||||
if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
|
||||
uart_write_wakeup(port);
|
||||
|
||||
if (uart_circ_chars_pending(xmit))
|
||||
schedule_work(&s->work_tx);
|
||||
}
|
||||
|
||||
/* Locking: called with port lock held */
|
||||
static int sci_dma_rx_push(struct sci_port *s, struct tty_struct *tty,
|
||||
size_t count)
|
||||
{
|
||||
struct uart_port *port = &s->port;
|
||||
int i, active, room;
|
||||
|
||||
room = tty_buffer_request_room(tty, count);
|
||||
|
||||
if (s->active_rx == s->cookie_rx[0]) {
|
||||
active = 0;
|
||||
} else if (s->active_rx == s->cookie_rx[1]) {
|
||||
active = 1;
|
||||
} else {
|
||||
dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (room < count)
|
||||
dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
|
||||
count - room);
|
||||
if (!room)
|
||||
return room;
|
||||
|
||||
for (i = 0; i < room; i++)
|
||||
tty_insert_flip_char(tty, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
|
||||
TTY_NORMAL);
|
||||
|
||||
port->icount.rx += room;
|
||||
|
||||
return room;
|
||||
}
|
||||
|
||||
static void sci_dma_rx_complete(void *arg)
|
||||
{
|
||||
struct sci_port *s = arg;
|
||||
struct uart_port *port = &s->port;
|
||||
struct tty_struct *tty = port->state->port.tty;
|
||||
unsigned long flags;
|
||||
int count;
|
||||
|
||||
dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
|
||||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
|
||||
count = sci_dma_rx_push(s, tty, s->buf_len_rx);
|
||||
|
||||
mod_timer(&s->rx_timer, jiffies + msecs_to_jiffies(5));
|
||||
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
|
||||
if (count)
|
||||
tty_flip_buffer_push(tty);
|
||||
|
||||
schedule_work(&s->work_rx);
|
||||
}
|
||||
|
||||
static void sci_start_rx(struct uart_port *port);
|
||||
static void sci_start_tx(struct uart_port *port);
|
||||
|
||||
static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
|
||||
{
|
||||
struct dma_chan *chan = s->chan_rx;
|
||||
struct uart_port *port = &s->port;
|
||||
|
||||
s->chan_rx = NULL;
|
||||
s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
|
||||
dma_release_channel(chan);
|
||||
dma_free_coherent(port->dev, s->buf_len_rx * 2,
|
||||
sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
|
||||
if (enable_pio)
|
||||
sci_start_rx(port);
|
||||
}
|
||||
|
||||
static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
|
||||
{
|
||||
struct dma_chan *chan = s->chan_tx;
|
||||
struct uart_port *port = &s->port;
|
||||
|
||||
s->chan_tx = NULL;
|
||||
s->cookie_tx = -EINVAL;
|
||||
dma_release_channel(chan);
|
||||
if (enable_pio)
|
||||
sci_start_tx(port);
|
||||
}
|
||||
|
||||
static void sci_submit_rx(struct sci_port *s)
|
||||
{
|
||||
struct dma_chan *chan = s->chan_rx;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
struct scatterlist *sg = &s->sg_rx[i];
|
||||
struct dma_async_tx_descriptor *desc;
|
||||
|
||||
desc = chan->device->device_prep_slave_sg(chan,
|
||||
sg, 1, DMA_FROM_DEVICE, DMA_PREP_INTERRUPT);
|
||||
|
||||
if (desc) {
|
||||
s->desc_rx[i] = desc;
|
||||
desc->callback = sci_dma_rx_complete;
|
||||
desc->callback_param = s;
|
||||
s->cookie_rx[i] = desc->tx_submit(desc);
|
||||
}
|
||||
|
||||
if (!desc || s->cookie_rx[i] < 0) {
|
||||
if (i) {
|
||||
async_tx_ack(s->desc_rx[0]);
|
||||
s->cookie_rx[0] = -EINVAL;
|
||||
}
|
||||
if (desc) {
|
||||
async_tx_ack(desc);
|
||||
s->cookie_rx[i] = -EINVAL;
|
||||
}
|
||||
dev_warn(s->port.dev,
|
||||
"failed to re-start DMA, using PIO\n");
|
||||
sci_rx_dma_release(s, true);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
s->active_rx = s->cookie_rx[0];
|
||||
|
||||
dma_async_issue_pending(chan);
|
||||
}
|
||||
|
||||
static void work_fn_rx(struct work_struct *work)
|
||||
{
|
||||
struct sci_port *s = container_of(work, struct sci_port, work_rx);
|
||||
struct uart_port *port = &s->port;
|
||||
struct dma_async_tx_descriptor *desc;
|
||||
int new;
|
||||
|
||||
if (s->active_rx == s->cookie_rx[0]) {
|
||||
new = 0;
|
||||
} else if (s->active_rx == s->cookie_rx[1]) {
|
||||
new = 1;
|
||||
} else {
|
||||
dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
|
||||
return;
|
||||
}
|
||||
desc = s->desc_rx[new];
|
||||
|
||||
if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
|
||||
DMA_SUCCESS) {
|
||||
/* Handle incomplete DMA receive */
|
||||
struct tty_struct *tty = port->state->port.tty;
|
||||
struct dma_chan *chan = s->chan_rx;
|
||||
struct sh_desc *sh_desc = container_of(desc, struct sh_desc,
|
||||
async_tx);
|
||||
unsigned long flags;
|
||||
int count;
|
||||
|
||||
chan->device->device_terminate_all(chan);
|
||||
dev_dbg(port->dev, "Read %u bytes with cookie %d\n",
|
||||
sh_desc->partial, sh_desc->cookie);
|
||||
|
||||
spin_lock_irqsave(&port->lock, flags);
|
||||
count = sci_dma_rx_push(s, tty, sh_desc->partial);
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
|
||||
if (count)
|
||||
tty_flip_buffer_push(tty);
|
||||
|
||||
sci_submit_rx(s);
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
s->cookie_rx[new] = desc->tx_submit(desc);
|
||||
if (s->cookie_rx[new] < 0) {
|
||||
dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
|
||||
sci_rx_dma_release(s, true);
|
||||
return;
|
||||
}
|
||||
|
||||
dev_dbg(port->dev, "%s: cookie %d #%d\n", __func__,
|
||||
s->cookie_rx[new], new);
|
||||
|
||||
s->active_rx = s->cookie_rx[!new];
|
||||
}
|
||||
|
||||
static void work_fn_tx(struct work_struct *work)
|
||||
{
|
||||
struct sci_port *s = container_of(work, struct sci_port, work_tx);
|
||||
struct dma_async_tx_descriptor *desc;
|
||||
struct dma_chan *chan = s->chan_tx;
|
||||
struct uart_port *port = &s->port;
|
||||
struct circ_buf *xmit = &port->state->xmit;
|
||||
struct scatterlist *sg = &s->sg_tx;
|
||||
|
||||
/*
|
||||
* DMA is idle now.
|
||||
* Port xmit buffer is already mapped, and it is one page... Just adjust
|
||||
* offsets and lengths. Since it is a circular buffer, we have to
|
||||
* transmit till the end, and then the rest. Take the port lock to get a
|
||||
* consistent xmit buffer state.
|
||||
*/
|
||||
spin_lock_irq(&port->lock);
|
||||
sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
|
||||
sg->dma_address = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
|
||||
sg->offset;
|
||||
sg->length = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
|
||||
CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
|
||||
sg->dma_length = sg->length;
|
||||
spin_unlock_irq(&port->lock);
|
||||
|
||||
BUG_ON(!sg->length);
|
||||
|
||||
desc = chan->device->device_prep_slave_sg(chan,
|
||||
sg, s->sg_len_tx, DMA_TO_DEVICE,
|
||||
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
||||
if (!desc) {
|
||||
/* switch to PIO */
|
||||
sci_tx_dma_release(s, true);
|
||||
return;
|
||||
}
|
||||
|
||||
dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
|
||||
|
||||
spin_lock_irq(&port->lock);
|
||||
s->desc_tx = desc;
|
||||
desc->callback = sci_dma_tx_complete;
|
||||
desc->callback_param = s;
|
||||
spin_unlock_irq(&port->lock);
|
||||
s->cookie_tx = desc->tx_submit(desc);
|
||||
if (s->cookie_tx < 0) {
|
||||
dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
|
||||
/* switch to PIO */
|
||||
sci_tx_dma_release(s, true);
|
||||
return;
|
||||
}
|
||||
|
||||
dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n", __func__,
|
||||
xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
|
||||
|
||||
dma_async_issue_pending(chan);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void sci_start_tx(struct uart_port *port)
|
||||
{
|
||||
unsigned short ctrl;
|
||||
|
||||
#ifdef CONFIG_SERIAL_SH_SCI_DMA
|
||||
struct sci_port *s = to_sci_port(port);
|
||||
|
||||
if (s->chan_tx) {
|
||||
if (!uart_circ_empty(&s->port.state->xmit) && s->cookie_tx < 0)
|
||||
schedule_work(&s->work_tx);
|
||||
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
|
||||
ctrl = sci_in(port, SCSCR);
|
||||
ctrl |= SCI_CTRL_FLAGS_TIE;
|
||||
@ -838,13 +1206,12 @@ static void sci_stop_tx(struct uart_port *port)
|
||||
sci_out(port, SCSCR, ctrl);
|
||||
}
|
||||
|
||||
static void sci_start_rx(struct uart_port *port, unsigned int tty_start)
|
||||
static void sci_start_rx(struct uart_port *port)
|
||||
{
|
||||
unsigned short ctrl;
|
||||
unsigned short ctrl = SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
|
||||
|
||||
/* Set RIE (Receive Interrupt Enable) bit in SCSCR */
|
||||
ctrl = sci_in(port, SCSCR);
|
||||
ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE;
|
||||
ctrl |= sci_in(port, SCSCR);
|
||||
sci_out(port, SCSCR, ctrl);
|
||||
}
|
||||
|
||||
@ -868,16 +1235,154 @@ static void sci_break_ctl(struct uart_port *port, int break_state)
|
||||
/* Nothing here yet .. */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SERIAL_SH_SCI_DMA
|
||||
static bool filter(struct dma_chan *chan, void *slave)
|
||||
{
|
||||
struct sh_dmae_slave *param = slave;
|
||||
|
||||
dev_dbg(chan->device->dev, "%s: slave ID %d\n", __func__,
|
||||
param->slave_id);
|
||||
|
||||
if (param->dma_dev == chan->device->dev) {
|
||||
chan->private = param;
|
||||
return true;
|
||||
} else {
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
static void rx_timer_fn(unsigned long arg)
|
||||
{
|
||||
struct sci_port *s = (struct sci_port *)arg;
|
||||
struct uart_port *port = &s->port;
|
||||
|
||||
u16 scr = sci_in(port, SCSCR);
|
||||
sci_out(port, SCSCR, scr | SCI_CTRL_FLAGS_RIE);
|
||||
dev_dbg(port->dev, "DMA Rx timed out\n");
|
||||
schedule_work(&s->work_rx);
|
||||
}
|
||||
|
||||
static void sci_request_dma(struct uart_port *port)
|
||||
{
|
||||
struct sci_port *s = to_sci_port(port);
|
||||
struct sh_dmae_slave *param;
|
||||
struct dma_chan *chan;
|
||||
dma_cap_mask_t mask;
|
||||
int nent;
|
||||
|
||||
dev_dbg(port->dev, "%s: port %d DMA %p\n", __func__,
|
||||
port->line, s->dma_dev);
|
||||
|
||||
if (!s->dma_dev)
|
||||
return;
|
||||
|
||||
dma_cap_zero(mask);
|
||||
dma_cap_set(DMA_SLAVE, mask);
|
||||
|
||||
param = &s->param_tx;
|
||||
|
||||
/* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
|
||||
param->slave_id = s->slave_tx;
|
||||
param->dma_dev = s->dma_dev;
|
||||
|
||||
s->cookie_tx = -EINVAL;
|
||||
chan = dma_request_channel(mask, filter, param);
|
||||
dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
|
||||
if (chan) {
|
||||
s->chan_tx = chan;
|
||||
sg_init_table(&s->sg_tx, 1);
|
||||
/* UART circular tx buffer is an aligned page. */
|
||||
BUG_ON((int)port->state->xmit.buf & ~PAGE_MASK);
|
||||
sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
|
||||
UART_XMIT_SIZE, (int)port->state->xmit.buf & ~PAGE_MASK);
|
||||
nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
|
||||
if (!nent)
|
||||
sci_tx_dma_release(s, false);
|
||||
else
|
||||
dev_dbg(port->dev, "%s: mapped %d@%p to %x\n", __func__,
|
||||
sg_dma_len(&s->sg_tx),
|
||||
port->state->xmit.buf, sg_dma_address(&s->sg_tx));
|
||||
|
||||
s->sg_len_tx = nent;
|
||||
|
||||
INIT_WORK(&s->work_tx, work_fn_tx);
|
||||
}
|
||||
|
||||
param = &s->param_rx;
|
||||
|
||||
/* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
|
||||
param->slave_id = s->slave_rx;
|
||||
param->dma_dev = s->dma_dev;
|
||||
|
||||
chan = dma_request_channel(mask, filter, param);
|
||||
dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
|
||||
if (chan) {
|
||||
dma_addr_t dma[2];
|
||||
void *buf[2];
|
||||
int i;
|
||||
|
||||
s->chan_rx = chan;
|
||||
|
||||
s->buf_len_rx = 2 * max(16, (int)port->fifosize);
|
||||
buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
|
||||
&dma[0], GFP_KERNEL);
|
||||
|
||||
if (!buf[0]) {
|
||||
dev_warn(port->dev,
|
||||
"failed to allocate dma buffer, using PIO\n");
|
||||
sci_rx_dma_release(s, true);
|
||||
return;
|
||||
}
|
||||
|
||||
buf[1] = buf[0] + s->buf_len_rx;
|
||||
dma[1] = dma[0] + s->buf_len_rx;
|
||||
|
||||
for (i = 0; i < 2; i++) {
|
||||
struct scatterlist *sg = &s->sg_rx[i];
|
||||
|
||||
sg_init_table(sg, 1);
|
||||
sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
|
||||
(int)buf[i] & ~PAGE_MASK);
|
||||
sg->dma_address = dma[i];
|
||||
sg->dma_length = sg->length;
|
||||
}
|
||||
|
||||
INIT_WORK(&s->work_rx, work_fn_rx);
|
||||
setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
|
||||
|
||||
sci_submit_rx(s);
|
||||
}
|
||||
}
|
||||
|
||||
static void sci_free_dma(struct uart_port *port)
|
||||
{
|
||||
struct sci_port *s = to_sci_port(port);
|
||||
|
||||
if (!s->dma_dev)
|
||||
return;
|
||||
|
||||
if (s->chan_tx)
|
||||
sci_tx_dma_release(s, false);
|
||||
if (s->chan_rx)
|
||||
sci_rx_dma_release(s, false);
|
||||
}
|
||||
#endif
|
||||
|
||||
static int sci_startup(struct uart_port *port)
|
||||
{
|
||||
struct sci_port *s = to_sci_port(port);
|
||||
|
||||
dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
|
||||
|
||||
if (s->enable)
|
||||
s->enable(port);
|
||||
|
||||
sci_request_irq(s);
|
||||
#ifdef CONFIG_SERIAL_SH_SCI_DMA
|
||||
sci_request_dma(port);
|
||||
#endif
|
||||
sci_start_tx(port);
|
||||
sci_start_rx(port, 1);
|
||||
sci_start_rx(port);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -886,8 +1391,13 @@ static void sci_shutdown(struct uart_port *port)
|
||||
{
|
||||
struct sci_port *s = to_sci_port(port);
|
||||
|
||||
dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
|
||||
|
||||
sci_stop_rx(port);
|
||||
sci_stop_tx(port);
|
||||
#ifdef CONFIG_SERIAL_SH_SCI_DMA
|
||||
sci_free_dma(port);
|
||||
#endif
|
||||
sci_free_irq(s);
|
||||
|
||||
if (s->disable)
|
||||
@ -937,6 +1447,9 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
|
||||
|
||||
sci_out(port, SCSMR, smr_val);
|
||||
|
||||
dev_dbg(port->dev, "%s: SMR %x, t %x, SCSCR %x\n", __func__, smr_val, t,
|
||||
SCSCR_INIT(port));
|
||||
|
||||
if (t > 0) {
|
||||
if (t >= 256) {
|
||||
sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1);
|
||||
@ -954,7 +1467,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
|
||||
sci_out(port, SCSCR, SCSCR_INIT(port));
|
||||
|
||||
if ((termios->c_cflag & CREAD) != 0)
|
||||
sci_start_rx(port, 0);
|
||||
sci_start_rx(port);
|
||||
}
|
||||
|
||||
static const char *sci_type(struct uart_port *port)
|
||||
@ -1049,19 +1562,21 @@ static void __devinit sci_init_single(struct platform_device *dev,
|
||||
unsigned int index,
|
||||
struct plat_sci_port *p)
|
||||
{
|
||||
sci_port->port.ops = &sci_uart_ops;
|
||||
sci_port->port.iotype = UPIO_MEM;
|
||||
sci_port->port.line = index;
|
||||
struct uart_port *port = &sci_port->port;
|
||||
|
||||
port->ops = &sci_uart_ops;
|
||||
port->iotype = UPIO_MEM;
|
||||
port->line = index;
|
||||
|
||||
switch (p->type) {
|
||||
case PORT_SCIFA:
|
||||
sci_port->port.fifosize = 64;
|
||||
port->fifosize = 64;
|
||||
break;
|
||||
case PORT_SCIF:
|
||||
sci_port->port.fifosize = 16;
|
||||
port->fifosize = 16;
|
||||
break;
|
||||
default:
|
||||
sci_port->port.fifosize = 1;
|
||||
port->fifosize = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
@ -1070,19 +1585,28 @@ static void __devinit sci_init_single(struct platform_device *dev,
|
||||
sci_port->dclk = clk_get(&dev->dev, "peripheral_clk");
|
||||
sci_port->enable = sci_clk_enable;
|
||||
sci_port->disable = sci_clk_disable;
|
||||
sci_port->port.dev = &dev->dev;
|
||||
port->dev = &dev->dev;
|
||||
}
|
||||
|
||||
sci_port->break_timer.data = (unsigned long)sci_port;
|
||||
sci_port->break_timer.function = sci_break_timer;
|
||||
init_timer(&sci_port->break_timer);
|
||||
|
||||
sci_port->port.mapbase = p->mapbase;
|
||||
sci_port->port.membase = p->membase;
|
||||
port->mapbase = p->mapbase;
|
||||
port->membase = p->membase;
|
||||
|
||||
sci_port->port.irq = p->irqs[SCIx_TXI_IRQ];
|
||||
sci_port->port.flags = p->flags;
|
||||
sci_port->type = sci_port->port.type = p->type;
|
||||
port->irq = p->irqs[SCIx_TXI_IRQ];
|
||||
port->flags = p->flags;
|
||||
sci_port->type = port->type = p->type;
|
||||
|
||||
#ifdef CONFIG_SERIAL_SH_SCI_DMA
|
||||
sci_port->dma_dev = p->dma_dev;
|
||||
sci_port->slave_tx = p->dma_slave_tx;
|
||||
sci_port->slave_rx = p->dma_slave_rx;
|
||||
|
||||
dev_dbg(port->dev, "%s: DMA device %p, tx %d, rx %d\n", __func__,
|
||||
p->dma_dev, p->dma_slave_tx, p->dma_slave_rx);
|
||||
#endif
|
||||
|
||||
memcpy(&sci_port->irqs, &p->irqs, sizeof(p->irqs));
|
||||
}
|
||||
|
@ -2,6 +2,7 @@
|
||||
#define __LINUX_SERIAL_SCI_H
|
||||
|
||||
#include <linux/serial_core.h>
|
||||
#include <asm/dmaengine.h>
|
||||
|
||||
/*
|
||||
* Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
|
||||
@ -16,6 +17,8 @@ enum {
|
||||
SCIx_NR_IRQS,
|
||||
};
|
||||
|
||||
struct device;
|
||||
|
||||
/*
|
||||
* Platform device specific platform_data struct
|
||||
*/
|
||||
@ -26,6 +29,9 @@ struct plat_sci_port {
|
||||
unsigned int type; /* SCI / SCIF / IRDA */
|
||||
upf_t flags; /* UPF_* flags */
|
||||
char *clk; /* clock string */
|
||||
struct device *dma_dev;
|
||||
enum sh_dmae_slave_chan_id dma_slave_tx;
|
||||
enum sh_dmae_slave_chan_id dma_slave_rx;
|
||||
};
|
||||
|
||||
#endif /* __LINUX_SERIAL_SCI_H */
|
||||
|
@ -72,7 +72,7 @@ struct siu_firmware {
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/dma-sh.h>
|
||||
#include <asm/dmaengine.h>
|
||||
|
||||
#include <sound/core.h>
|
||||
#include <sound/pcm.h>
|
||||
|
@ -32,7 +32,7 @@
|
||||
#include <sound/pcm_params.h>
|
||||
#include <sound/soc-dai.h>
|
||||
|
||||
#include <asm/dma-sh.h>
|
||||
#include <asm/dmaengine.h>
|
||||
#include <asm/siu.h>
|
||||
|
||||
#include "siu.h"
|
||||
|
Loading…
Reference in New Issue
Block a user