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Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next

Browse Source 
- Ilia's PMPEG improvements
- MSI fixes, and another attempt at enabling by default
- Initial GK208 support, just modesetting
- "Old" PM code gone, new infrastructure and various different stages of support (depending which chipset / ram type etc) is in its place.  This includes support that goes beyond what the previous code was capable of.  User control has been deliberately sabotaged, it's not safe to use still.
- Thermal management / fan control that's been present for a while is turned ON by default now.
- Misc other fixes that have accumulated

* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (74 commits)
  drm/nouveau/fb: implement various bits of work towards memory reclocking
  drm/nouveau: implement a simple sysfs interface to new pm code
  drm/nouveau/device: initial control object class, with pstate control methods
  drm/nouveau/clk: implement power state and engine clock control in core
  drm/nouveau/volt: implement voltage control in core
  drm/nouveau/bios: parsing for various tables required for power management
  drm/nouveau/perfmon: initial infrastructure to expose performance counters
  drm/nouveau/bus: add interfaces/helpers for sequencer
  drm/nouveau/bus: make external class definitions pointers
  drm/nouveau/pwr: initial implementation
  drm/nouveau/therm: update target fanspeed outside of therm lock
  drm/nouveau/therm: automatic mode by default
  drm/nouveau/therm: no toggle fan control either if we can't guarantee no pwm connected
  drm/nvc0/therm: allow fan control if we've killed the vbios ppwr ucode
  drm/nouveau/therm: if no bios trip/linear info, default to perf-suggested speed
  drm/nouveau/therm: add hook for clk to suggest fanspeed to therm
  drm/nouveau/pwr: assign a subdev id for upcoming implementation
  drm/nouveau/gpio: return different error code for not found vs invalid
  drm/nouveau/drm/pm: remove everything except the hwmon interfaces to THERM
  drm/nouveau/core: make all info-level messages silent for runtime pm
  ...
This commit is contained in:
Dave Airlie 2013-11-08 16:01:02 +10:00
commit 4a15cdffa9
233 changed files with 19492 additions and 6883 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
drivers/gpu/drm/nouveau/Makefile
View File

@ -28,7 +28,9 @@ nouveau-y += core/subdev/bar/nv50.o
nouveau-y += core/subdev/bar/nvc0.o
nouveau-y += core/subdev/bios/base.o
nouveau-y += core/subdev/bios/bit.o
nouveau-y += core/subdev/bios/boost.o
nouveau-y += core/subdev/bios/conn.o
nouveau-y += core/subdev/bios/cstep.o
nouveau-y += core/subdev/bios/dcb.o
nouveau-y += core/subdev/bios/disp.o
nouveau-y += core/subdev/bios/dp.o
@ -39,17 +41,26 @@ nouveau-y += core/subdev/bios/init.o
nouveau-y += core/subdev/bios/mxm.o
nouveau-y += core/subdev/bios/perf.o
nouveau-y += core/subdev/bios/pll.o
nouveau-y += core/subdev/bios/rammap.o
nouveau-y += core/subdev/bios/timing.o
nouveau-y += core/subdev/bios/therm.o
nouveau-y += core/subdev/bios/vmap.o
nouveau-y += core/subdev/bios/volt.o
nouveau-y += core/subdev/bios/xpio.o
nouveau-y += core/subdev/bus/hwsq.o
nouveau-y += core/subdev/bus/nv04.o
nouveau-y += core/subdev/bus/nv31.o
nouveau-y += core/subdev/bus/nv50.o
nouveau-y += core/subdev/bus/nv94.o
nouveau-y += core/subdev/bus/nvc0.o
nouveau-y += core/subdev/clock/base.o
nouveau-y += core/subdev/clock/nv04.o
nouveau-y += core/subdev/clock/nv40.o
nouveau-y += core/subdev/clock/nv50.o
nouveau-y += core/subdev/clock/nv84.o
nouveau-y += core/subdev/clock/nva3.o
nouveau-y += core/subdev/clock/nvc0.o
nouveau-y += core/subdev/clock/nve0.o
nouveau-y += core/subdev/clock/pllnv04.o
nouveau-y += core/subdev/clock/pllnva3.o
nouveau-y += core/subdev/devinit/base.o
@ -78,7 +89,12 @@ nouveau-y += core/subdev/fb/nv47.o
nouveau-y += core/subdev/fb/nv49.o
nouveau-y += core/subdev/fb/nv4e.o
nouveau-y += core/subdev/fb/nv50.o
nouveau-y += core/subdev/fb/nv84.o
nouveau-y += core/subdev/fb/nva3.o
nouveau-y += core/subdev/fb/nvaa.o
nouveau-y += core/subdev/fb/nvaf.o
nouveau-y += core/subdev/fb/nvc0.o
nouveau-y += core/subdev/fb/nve0.o
nouveau-y += core/subdev/fb/ramnv04.o
nouveau-y += core/subdev/fb/ramnv10.o
nouveau-y += core/subdev/fb/ramnv1a.o
@ -89,7 +105,12 @@ nouveau-y += core/subdev/fb/ramnv44.o
nouveau-y += core/subdev/fb/ramnv49.o
nouveau-y += core/subdev/fb/ramnv4e.o
nouveau-y += core/subdev/fb/ramnv50.o
nouveau-y += core/subdev/fb/ramnva3.o
nouveau-y += core/subdev/fb/ramnvaa.o
nouveau-y += core/subdev/fb/ramnvc0.o
nouveau-y += core/subdev/fb/ramnve0.o
nouveau-y += core/subdev/fb/sddr3.o
nouveau-y += core/subdev/fb/gddr5.o
nouveau-y += core/subdev/gpio/base.o
nouveau-y += core/subdev/gpio/nv10.o
nouveau-y += core/subdev/gpio/nv50.o
@ -113,13 +134,22 @@ nouveau-y += core/subdev/instmem/nv50.o
nouveau-y += core/subdev/ltcg/nvc0.o
nouveau-y += core/subdev/mc/base.o
nouveau-y += core/subdev/mc/nv04.o
nouveau-y += core/subdev/mc/nv40.o
nouveau-y += core/subdev/mc/nv44.o
nouveau-y += core/subdev/mc/nv50.o
nouveau-y += core/subdev/mc/nv94.o
nouveau-y += core/subdev/mc/nv98.o
nouveau-y += core/subdev/mc/nvc0.o
nouveau-y += core/subdev/mc/nvc3.o
nouveau-y += core/subdev/mxm/base.o
nouveau-y += core/subdev/mxm/mxms.o
nouveau-y += core/subdev/mxm/nv50.o
nouveau-y += core/subdev/pwr/base.o
nouveau-y += core/subdev/pwr/memx.o
nouveau-y += core/subdev/pwr/nva3.o
nouveau-y += core/subdev/pwr/nvc0.o
nouveau-y += core/subdev/pwr/nvd0.o
nouveau-y += core/subdev/pwr/nv108.o
nouveau-y += core/subdev/therm/base.o
nouveau-y += core/subdev/therm/fan.o
nouveau-y += core/subdev/therm/fannil.o
@ -140,6 +170,9 @@ nouveau-y += core/subdev/vm/nv41.o
nouveau-y += core/subdev/vm/nv44.o
nouveau-y += core/subdev/vm/nv50.o
nouveau-y += core/subdev/vm/nvc0.o
nouveau-y += core/subdev/volt/base.o
nouveau-y += core/subdev/volt/gpio.o
nouveau-y += core/subdev/volt/nv40.o
nouveau-y += core/engine/falcon.o
nouveau-y += core/engine/xtensa.o
@ -158,6 +191,7 @@ nouveau-y += core/engine/copy/nve0.o
nouveau-y += core/engine/crypt/nv84.o
nouveau-y += core/engine/crypt/nv98.o
nouveau-y += core/engine/device/base.o
nouveau-y += core/engine/device/ctrl.o
nouveau-y += core/engine/device/nv04.o
nouveau-y += core/engine/device/nv10.o
nouveau-y += core/engine/device/nv20.o
@ -227,8 +261,18 @@ nouveau-y += core/engine/graph/nve4.o
nouveau-y += core/engine/graph/nvf0.o
nouveau-y += core/engine/mpeg/nv31.o
nouveau-y += core/engine/mpeg/nv40.o
nouveau-y += core/engine/mpeg/nv44.o
nouveau-y += core/engine/mpeg/nv50.o
nouveau-y += core/engine/mpeg/nv84.o
nouveau-y += core/engine/perfmon/base.o
nouveau-y += core/engine/perfmon/daemon.o
nouveau-y += core/engine/perfmon/nv40.o
nouveau-y += core/engine/perfmon/nv50.o
nouveau-y += core/engine/perfmon/nv84.o
nouveau-y += core/engine/perfmon/nva3.o
nouveau-y += core/engine/perfmon/nvc0.o
nouveau-y += core/engine/perfmon/nve0.o
nouveau-y += core/engine/perfmon/nvf0.o
nouveau-y += core/engine/ppp/nv98.o
nouveau-y += core/engine/ppp/nvc0.o
nouveau-y += core/engine/software/nv04.o
@ -260,9 +304,7 @@ include $(src)/dispnv04/Makefile
nouveau-y += nv50_display.o
# drm/pm
nouveau-y += nouveau_pm.o nouveau_volt.o nouveau_perf.o
nouveau-y += nv04_pm.o nv40_pm.o nv50_pm.o nva3_pm.o nvc0_pm.o
nouveau-y += nouveau_mem.o
nouveau-y += nouveau_hwmon.o nouveau_sysfs.o
# other random bits
nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o

137
drivers/gpu/drm/nouveau/core/core/event.c
View File

@ -23,62 +23,114 @@
#include <core/os.h>
#include <core/event.h>
static void
nouveau_event_put_locked(struct nouveau_event *event, int index,
struct nouveau_eventh *handler)
{
if (!--event->index[index].refs) {
if (event->disable)
event->disable(event, index);
}
list_del(&handler->head);
}
void
nouveau_event_put(struct nouveau_event *event, int index,
struct nouveau_eventh *handler)
nouveau_event_put(struct nouveau_eventh *handler)
{
struct nouveau_event *event = handler->event;
unsigned long flags;
spin_lock_irqsave(&event->lock, flags);
if (index < event->index_nr)
nouveau_event_put_locked(event, index, handler);
spin_unlock_irqrestore(&event->lock, flags);
}
void
nouveau_event_get(struct nouveau_event *event, int index,
struct nouveau_eventh *handler)
{
unsigned long flags;
spin_lock_irqsave(&event->lock, flags);
if (index < event->index_nr) {
list_add(&handler->head, &event->index[index].list);
if (!event->index[index].refs++) {
if (event->enable)
event->enable(event, index);
if (__test_and_clear_bit(NVKM_EVENT_ENABLE, &handler->flags)) {
spin_lock_irqsave(&event->refs_lock, flags);
if (!--event->index[handler->index].refs) {
if (event->disable)
event->disable(event, handler->index);
}
spin_unlock_irqrestore(&event->refs_lock, flags);
}
spin_unlock_irqrestore(&event->lock, flags);
}
void
nouveau_event_get(struct nouveau_eventh *handler)
{
struct nouveau_event *event = handler->event;
unsigned long flags;
if (!__test_and_set_bit(NVKM_EVENT_ENABLE, &handler->flags)) {
spin_lock_irqsave(&event->refs_lock, flags);
if (!event->index[handler->index].refs++) {
if (event->enable)
event->enable(event, handler->index);
}
spin_unlock_irqrestore(&event->refs_lock, flags);
}
}
static void
nouveau_event_fini(struct nouveau_eventh *handler)
{
struct nouveau_event *event = handler->event;
unsigned long flags;
nouveau_event_put(handler);
spin_lock_irqsave(&event->list_lock, flags);
list_del(&handler->head);
spin_unlock_irqrestore(&event->list_lock, flags);
}
static int
nouveau_event_init(struct nouveau_event *event, int index,
int (*func)(void *, int), void *priv,
struct nouveau_eventh *handler)
{
unsigned long flags;
if (index >= event->index_nr)
return -EINVAL;
handler->event = event;
handler->flags = 0;
handler->index = index;
handler->func = func;
handler->priv = priv;
spin_lock_irqsave(&event->list_lock, flags);
list_add_tail(&handler->head, &event->index[index].list);
spin_unlock_irqrestore(&event->list_lock, flags);
return 0;
}
int
nouveau_event_new(struct nouveau_event *event, int index,
int (*func)(void *, int), void *priv,
struct nouveau_eventh **phandler)
{
struct nouveau_eventh *handler;
int ret = -ENOMEM;
handler = *phandler = kmalloc(sizeof(*handler), GFP_KERNEL);
if (handler) {
ret = nouveau_event_init(event, index, func, priv, handler);
if (ret)
kfree(handler);
}
return ret;
}
void
nouveau_event_ref(struct nouveau_eventh *handler, struct nouveau_eventh **ref)
{
BUG_ON(handler != NULL);
if (*ref) {
nouveau_event_fini(*ref);
kfree(*ref);
}
*ref = handler;
}
void
nouveau_event_trigger(struct nouveau_event *event, int index)
{
struct nouveau_eventh *handler, *temp;
struct nouveau_eventh *handler;
unsigned long flags;
if (index >= event->index_nr)
if (WARN_ON(index >= event->index_nr))
return;
spin_lock_irqsave(&event->lock, flags);
list_for_each_entry_safe(handler, temp, &event->index[index].list, head) {
if (handler->func(handler, index) == NVKM_EVENT_DROP) {
nouveau_event_put_locked(event, index, handler);
}
spin_lock_irqsave(&event->list_lock, flags);
list_for_each_entry(handler, &event->index[index].list, head) {
if (test_bit(NVKM_EVENT_ENABLE, &handler->flags) &&
handler->func(handler->priv, index) == NVKM_EVENT_DROP)
nouveau_event_put(handler);
}
spin_unlock_irqrestore(&event->lock, flags);
spin_unlock_irqrestore(&event->list_lock, flags);
}
void
@ -102,7 +154,8 @@ nouveau_event_create(int index_nr, struct nouveau_event **pevent)
if (!event)
return -ENOMEM;
spin_lock_init(&event->lock);
spin_lock_init(&event->list_lock);
spin_lock_init(&event->refs_lock);
for (i = 0; i < index_nr; i++)
INIT_LIST_HEAD(&event->index[i].list);
event->index_nr = index_nr;

11
drivers/gpu/drm/nouveau/core/core/option.c
View File

@ -25,15 +25,6 @@
#include <core/option.h>
#include <core/debug.h>
/* compares unterminated string 'str' with zero-terminated string 'cmp' */
static inline int
strncasecmpz(const char *str, const char *cmp, size_t len)
{
if (strlen(cmp) != len)
return len;
return strncasecmp(str, cmp, len);
}
const char *
nouveau_stropt(const char *optstr, const char *opt, int *arglen)
{
@ -105,7 +96,7 @@ nouveau_dbgopt(const char *optstr, const char *sub)
else if (!strncasecmpz(optstr, "warn", len))
level = NV_DBG_WARN;
else if (!strncasecmpz(optstr, "info", len))
level = NV_DBG_INFO;
level = NV_DBG_INFO_NORMAL;
else if (!strncasecmpz(optstr, "debug", len))
level = NV_DBG_DEBUG;
else if (!strncasecmpz(optstr, "trace", len))

45
drivers/gpu/drm/nouveau/core/core/printk.c
View File

@ -27,16 +27,38 @@
#include <core/subdev.h>
#include <core/printk.h>
int nv_printk_suspend_level = NV_DBG_DEBUG;
int nv_info_debug_level = NV_DBG_INFO_NORMAL;
void
nv_printk_(struct nouveau_object *object, const char *pfx, int level,
const char *fmt, ...)
nv_printk_(struct nouveau_object *object, int level, const char *fmt, ...)
{
static const char name[] = { '!', 'E', 'W', ' ', 'D', 'T', 'P', 'S' };
const char *pfx;
char mfmt[256];
va_list args;
switch (level) {
case NV_DBG_FATAL:
pfx = KERN_CRIT;
break;
case NV_DBG_ERROR:
pfx = KERN_ERR;
break;
case NV_DBG_WARN:
pfx = KERN_WARNING;
break;
case NV_DBG_INFO_NORMAL:
pfx = KERN_INFO;
break;
case NV_DBG_DEBUG:
case NV_DBG_PARANOIA:
case NV_DBG_TRACE:
case NV_DBG_SPAM:
default:
pfx = KERN_DEBUG;
break;
}
if (object && !nv_iclass(object, NV_CLIENT_CLASS)) {
struct nouveau_object *device = object;
struct nouveau_object *subdev = object;
@ -74,20 +96,3 @@ nv_printk_(struct nouveau_object *object, const char *pfx, int level,
vprintk(mfmt, args);
va_end(args);
}
#define CONV_LEVEL(x) case NV_DBG_##x: return NV_PRINTK_##x
const char *nv_printk_level_to_pfx(int level)
{
switch (level) {
CONV_LEVEL(FATAL);
CONV_LEVEL(ERROR);
CONV_LEVEL(WARN);
CONV_LEVEL(INFO);
CONV_LEVEL(DEBUG);
CONV_LEVEL(PARANOIA);
CONV_LEVEL(TRACE);
CONV_LEVEL(SPAM);
}
return NV_PRINTK_DEBUG;
}

56
drivers/gpu/drm/nouveau/core/engine/device/base.c
View File

@ -29,7 +29,7 @@
#include <core/class.h>
#include <engine/device.h>
#include "priv.h"
static DEFINE_MUTEX(nv_devices_mutex);
static LIST_HEAD(nv_devices);
@ -75,7 +75,9 @@ static const u64 disable_map[] = {
[NVDEV_SUBDEV_BAR] = NV_DEVICE_DISABLE_CORE,
[NVDEV_SUBDEV_VOLT] = NV_DEVICE_DISABLE_CORE,
[NVDEV_SUBDEV_THERM] = NV_DEVICE_DISABLE_CORE,
[NVDEV_SUBDEV_PWR] = NV_DEVICE_DISABLE_CORE,
[NVDEV_ENGINE_DMAOBJ] = NV_DEVICE_DISABLE_CORE,
[NVDEV_ENGINE_PERFMON] = NV_DEVICE_DISABLE_CORE,
[NVDEV_ENGINE_FIFO] = NV_DEVICE_DISABLE_FIFO,
[NVDEV_ENGINE_SW] = NV_DEVICE_DISABLE_FIFO,
[NVDEV_ENGINE_GR] = NV_DEVICE_DISABLE_GRAPH,
@ -87,7 +89,7 @@ static const u64 disable_map[] = {
[NVDEV_ENGINE_PPP] = NV_DEVICE_DISABLE_PPP,
[NVDEV_ENGINE_COPY0] = NV_DEVICE_DISABLE_COPY0,
[NVDEV_ENGINE_COPY1] = NV_DEVICE_DISABLE_COPY1,
[NVDEV_ENGINE_UNK1C1] = NV_DEVICE_DISABLE_UNK1C1,
[NVDEV_ENGINE_VIC] = NV_DEVICE_DISABLE_VIC,
[NVDEV_ENGINE_VENC] = NV_DEVICE_DISABLE_VENC,
[NVDEV_ENGINE_DISP] = NV_DEVICE_DISABLE_DISP,
[NVDEV_SUBDEV_NR] = 0,
@ -119,10 +121,12 @@ nouveau_devobj_ctor(struct nouveau_object *parent,
return -ENODEV;
}
ret = nouveau_parent_create(parent, nv_object(device), oclass, 0, NULL,
ret = nouveau_parent_create(parent, nv_object(device), oclass, 0,
nouveau_control_oclass,
(1ULL << NVDEV_ENGINE_DMAOBJ) |
(1ULL << NVDEV_ENGINE_FIFO) |
(1ULL << NVDEV_ENGINE_DISP), &devobj);
(1ULL << NVDEV_ENGINE_DISP) |
(1ULL << NVDEV_ENGINE_PERFMON), &devobj);
*pobject = nv_object(devobj);
if (ret)
return ret;
@ -158,22 +162,29 @@ nouveau_devobj_ctor(struct nouveau_object *parent,
iounmap(map);
/* determine chipset and derive architecture from it */
if ((boot0 & 0x0f000000) > 0) {
device->chipset = (boot0 & 0xff00000) >> 20;
switch (device->chipset & 0xf0) {
case 0x10: device->card_type = NV_10; break;
case 0x20: device->card_type = NV_20; break;
case 0x30: device->card_type = NV_30; break;
case 0x40:
case 0x60: device->card_type = NV_40; break;
case 0x50:
case 0x80:
case 0x90:
case 0xa0: device->card_type = NV_50; break;
case 0xc0: device->card_type = NV_C0; break;
case 0xd0: device->card_type = NV_D0; break;
case 0xe0:
case 0xf0: device->card_type = NV_E0; break;
if ((boot0 & 0x1f000000) > 0) {
device->chipset = (boot0 & 0x1ff00000) >> 20;
switch (device->chipset & 0x1f0) {
case 0x010: {
if (0x461 & (1 << (device->chipset & 0xf)))
device->card_type = NV_10;
else
device->card_type = NV_11;
break;
}
case 0x020: device->card_type = NV_20; break;
case 0x030: device->card_type = NV_30; break;
case 0x040:
case 0x060: device->card_type = NV_40; break;
case 0x050:
case 0x080:
case 0x090:
case 0x0a0: device->card_type = NV_50; break;
case 0x0c0: device->card_type = NV_C0; break;
case 0x0d0: device->card_type = NV_D0; break;
case 0x0e0:
case 0x0f0:
case 0x100: device->card_type = NV_E0; break;
default:
break;
}
@ -188,7 +199,8 @@ nouveau_devobj_ctor(struct nouveau_object *parent,
switch (device->card_type) {
case NV_04: ret = nv04_identify(device); break;
case NV_10: ret = nv10_identify(device); break;
case NV_10:
case NV_11: ret = nv10_identify(device); break;
case NV_20: ret = nv20_identify(device); break;
case NV_30: ret = nv30_identify(device); break;
case NV_40: ret = nv40_identify(device); break;
@ -212,7 +224,7 @@ nouveau_devobj_ctor(struct nouveau_object *parent,
nv_info(device, "Family : NV%02X\n", device->card_type);
/* determine frequency of timing crystal */
if ( device->chipset < 0x17 ||
if ( device->card_type <= NV_10 || device->chipset < 0x17 ||
(device->chipset >= 0x20 && device->chipset < 0x25))
strap &= 0x00000040;
else

144
drivers/gpu/drm/nouveau/core/engine/device/ctrl.c Normal file
View File

@ -0,0 +1,144 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include <core/object.h>
#include <core/class.h>
#include <subdev/clock.h>
#include "priv.h"
static int
nouveau_control_mthd_pstate_info(struct nouveau_object *object, u32 mthd,
void *data, u32 size)
{
struct nouveau_clock *clk = nouveau_clock(object);
struct nv_control_pstate_info *args = data;
if (size < sizeof(*args))
return -EINVAL;
if (clk) {
args->count = clk->state_nr;
args->ustate = clk->ustate;
args->pstate = clk->pstate;
} else {
args->count = 0;
args->ustate = NV_CONTROL_PSTATE_INFO_USTATE_DISABLE;
args->pstate = NV_CONTROL_PSTATE_INFO_PSTATE_UNKNOWN;
}
return 0;
}
static int
nouveau_control_mthd_pstate_attr(struct nouveau_object *object, u32 mthd,
void *data, u32 size)
{
struct nouveau_clock *clk = nouveau_clock(object);
struct nv_control_pstate_attr *args = data;
struct nouveau_clocks *domain;
struct nouveau_pstate *pstate;
struct nouveau_cstate *cstate;
int i = 0, j = -1;
u32 lo, hi;
if ((size < sizeof(*args)) || !clk ||
(args->state >= 0 && args->state >= clk->state_nr))
return -EINVAL;
domain = clk->domains;
while (domain->name != nv_clk_src_max) {
if (domain->mname && ++j == args->index)
break;
domain++;
}
if (domain->name == nv_clk_src_max)
return -EINVAL;
if (args->state != NV_CONTROL_PSTATE_ATTR_STATE_CURRENT) {
list_for_each_entry(pstate, &clk->states, head) {
if (i++ == args->state)
break;
}
lo = pstate->base.domain[domain->name];
hi = lo;
list_for_each_entry(cstate, &pstate->list, head) {
lo = min(lo, cstate->domain[domain->name]);
hi = max(hi, cstate->domain[domain->name]);
}
args->state = pstate->pstate;
} else {
lo = max(clk->read(clk, domain->name), 0);
hi = lo;
}
snprintf(args->name, sizeof(args->name), "%s", domain->mname);
snprintf(args->unit, sizeof(args->unit), "MHz");
args->min = lo / domain->mdiv;
args->max = hi / domain->mdiv;
args->index = 0;
while ((++domain)->name != nv_clk_src_max) {
if (domain->mname) {
args->index = ++j;
break;
}
}
return 0;
}
static int
nouveau_control_mthd_pstate_user(struct nouveau_object *object, u32 mthd,
void *data, u32 size)
{
struct nouveau_clock *clk = nouveau_clock(object);
struct nv_control_pstate_user *args = data;
if (size < sizeof(*args) || !clk)
return -EINVAL;
return nouveau_clock_ustate(clk, args->state);
}
struct nouveau_oclass
nouveau_control_oclass[] = {
{ .handle = NV_CONTROL_CLASS,
.ofuncs = &nouveau_object_ofuncs,
.omthds = (struct nouveau_omthds[]) {
{ NV_CONTROL_PSTATE_INFO,
NV_CONTROL_PSTATE_INFO, nouveau_control_mthd_pstate_info },
{ NV_CONTROL_PSTATE_ATTR,
NV_CONTROL_PSTATE_ATTR, nouveau_control_mthd_pstate_attr },
{ NV_CONTROL_PSTATE_USER,
NV_CONTROL_PSTATE_USER, nouveau_control_mthd_pstate_user },
{},
},
},
{}
};

20
drivers/gpu/drm/nouveau/core/engine/device/nv04.c
View File

@ -50,15 +50,15 @@ nv04_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv04_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv04_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv04_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
@ -68,15 +68,15 @@ nv04_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv05_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv04_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv04_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv04_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv04_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv04_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv04_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;

76
drivers/gpu/drm/nouveau/core/engine/device/nv10.c
View File

@ -52,10 +52,10 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
@ -69,15 +69,15 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
@ -88,15 +88,15 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
@ -107,15 +107,15 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv1a_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
@ -126,15 +126,15 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv10_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
@ -145,15 +145,15 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
@ -164,15 +164,15 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv1a_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv1a_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
@ -183,15 +183,15 @@ nv10_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv10_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;

40
drivers/gpu/drm/nouveau/core/engine/device/nv20.c
View File

@ -53,15 +53,15 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv20_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv20_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv20_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
@ -72,15 +72,15 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
@ -91,15 +91,15 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv25_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
@ -110,15 +110,15 @@ nv20_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv25_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv2a_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;

50
drivers/gpu/drm/nouveau/core/engine/device/nv30.c
View File

@ -53,15 +53,15 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv30_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
@ -72,15 +72,15 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv04_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv35_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv35_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
break;
@ -91,15 +91,15 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv30_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv30_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv30_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
@ -111,15 +111,15 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv20_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv36_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv36_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv35_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
@ -131,15 +131,15 @@ nv30_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_I2C ] = &nv04_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv04_clock_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv10_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv10_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv04_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv17_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv34_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv31_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;

218
drivers/gpu/drm/nouveau/core/engine/device/nv40.c
View File

@ -35,6 +35,7 @@
#include <subdev/fb.h>
#include <subdev/instmem.h>
#include <subdev/vm.h>
#include <subdev/volt.h>
#include <engine/device.h>
#include <engine/dmaobj.h>
@ -43,6 +44,7 @@
#include <engine/graph.h>
#include <engine/mpeg.h>
#include <engine/disp.h>
#include <engine/perfmon.h>
int
nv40_identify(struct nouveau_device *device)
@ -56,18 +58,20 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x41:
device->cname = "NV41";
@ -77,18 +81,20 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv41_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x42:
device->cname = "NV42";
@ -98,18 +104,20 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv41_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x43:
device->cname = "NV43";
@ -119,18 +127,20 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv41_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv41_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x45:
device->cname = "NV45";
@ -140,18 +150,20 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv40_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x47:
device->cname = "G70";
@ -161,18 +173,20 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv47_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv47_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x49:
device->cname = "G71";
@ -182,18 +196,20 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv49_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x4b:
device->cname = "G73";
@ -203,18 +219,20 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv40_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv49_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv49_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv41_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x44:
device->cname = "NV44";
@ -224,18 +242,20 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv44_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x46:
device->cname = "G72";
@ -245,18 +265,20 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x4a:
device->cname = "NV44A";
@ -266,18 +288,20 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv44_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv44_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x4c:
device->cname = "C61";
@ -287,18 +311,20 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x4e:
device->cname = "C51";
@ -308,18 +334,20 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv4e_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv4e_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x63:
device->cname = "C73";
@ -329,18 +357,20 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x67:
device->cname = "C67";
@ -350,18 +380,20 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
case 0x68:
device->cname = "C68";
@ -371,18 +403,20 @@ nv40_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv44_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv31_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv46_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv44_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv40_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv10_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv44_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv40_perfmon_oclass;
break;
default:
nv_fatal(device, "unknown Curie chipset\n");

195
drivers/gpu/drm/nouveau/core/engine/device/nv50.c
View File

@ -36,6 +36,8 @@
#include <subdev/instmem.h>
#include <subdev/vm.h>
#include <subdev/bar.h>
#include <subdev/pwr.h>
#include <subdev/volt.h>
#include <engine/device.h>
#include <engine/dmaobj.h>
@ -49,6 +51,7 @@
#include <engine/ppp.h>
#include <engine/copy.h>
#include <engine/disp.h>
#include <engine/perfmon.h>
int
nv50_identify(struct nouveau_device *device)
@ -59,257 +62,277 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv50_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv50_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv50_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv50_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv50_perfmon_oclass;
break;
case 0x84:
device->cname = "G84";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv84_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break;
case 0x86:
device->cname = "G86";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv84_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break;
case 0x92:
device->cname = "G92";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv84_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break;
case 0x94:
device->cname = "G94";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break;
case 0x96:
device->cname = "G96";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv94_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break;
case 0x98:
device->cname = "G98";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break;
case 0xa0:
device->cname = "G200";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv50_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nv84_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva0_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break;
case 0xaa:
device->cname = "MCP77/MCP78";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break;
case 0xac:
device->cname = "MCP79/MCP7A";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nv94_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = nv84_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nv84_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvaa_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nv94_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
break;
case 0xa3:
device->cname = "GT215";
@ -320,16 +343,18 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
@ -337,6 +362,7 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
break;
case 0xa5:
device->cname = "GT216";
@ -347,22 +373,25 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
break;
case 0xa8:
device->cname = "GT218";
@ -373,22 +402,25 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nva3_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
break;
case 0xaf:
device->cname = "MCP89";
@ -399,22 +431,25 @@ nv50_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nva3_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nv50_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nv98_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nv94_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvaf_fb_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nva3_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nv84_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = nva3_perfmon_oclass;
break;
default:
nv_fatal(device, "unknown Tesla chipset\n");

118
drivers/gpu/drm/nouveau/core/engine/device/nvc0.c
View File

@ -38,6 +38,8 @@
#include <subdev/instmem.h>
#include <subdev/vm.h>
#include <subdev/bar.h>
#include <subdev/pwr.h>
#include <subdev/volt.h>
#include <engine/device.h>
#include <engine/dmaobj.h>
@ -49,6 +51,7 @@
#include <engine/ppp.h>
#include <engine/copy.h>
#include <engine/disp.h>
#include <engine/perfmon.h>
int
nvc0_identify(struct nouveau_device *device)
@ -63,18 +66,20 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc0_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
@ -82,6 +87,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
case 0xc4:
device->cname = "GF104";
@ -92,18 +98,20 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
@ -111,6 +119,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
case 0xc3:
device->cname = "GF106";
@ -121,24 +130,27 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
case 0xce:
device->cname = "GF114";
@ -149,18 +161,20 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
@ -168,6 +182,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
case 0xcf:
device->cname = "GF116";
@ -178,18 +193,20 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc3_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
@ -197,6 +214,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
case 0xc1:
device->cname = "GF108";
@ -207,24 +225,27 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc1_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
case 0xc8:
device->cname = "GF110";
@ -235,18 +256,20 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nva3_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvc0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvc8_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
@ -254,6 +277,7 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nva3_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
case 0xd9:
device->cname = "GF119";
@ -264,24 +288,27 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvd9_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nvd0_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
case 0xd7:
device->cname = "GF117";
@ -292,24 +319,25 @@ nvc0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nvc0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvd7_graph_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nvd0_disp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nvc0_perfmon_oclass;
break;
default:
nv_fatal(device, "unknown Fermi chipset\n");

99
drivers/gpu/drm/nouveau/core/engine/device/nve0.c
View File

@ -38,6 +38,8 @@
#include <subdev/instmem.h>
#include <subdev/vm.h>
#include <subdev/bar.h>
#include <subdev/pwr.h>
#include <subdev/volt.h>
#include <engine/device.h>
#include <engine/dmaobj.h>
@ -49,6 +51,7 @@
#include <engine/bsp.h>
#include <engine/vp.h>
#include <engine/ppp.h>
#include <engine/perfmon.h>
int
nve0_identify(struct nouveau_device *device)
@ -59,22 +62,24 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
@ -83,28 +88,31 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
break;
case 0xe7:
device->cname = "GK107";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
@ -113,28 +121,31 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
break;
case 0xe6:
device->cname = "GK106";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nve4_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nve0_disp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
@ -143,28 +154,31 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
break;
case 0xf0:
device->cname = "GK110";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = &nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nvd0_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = &nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass;
device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass;
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
@ -174,6 +188,43 @@ nve0_identify(struct nouveau_device *device)
device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
#endif
device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass;
break;
case 0x108:
device->cname = "GK208";
device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
device->oclass[NVDEV_SUBDEV_GPIO ] = &nve0_gpio_oclass;
device->oclass[NVDEV_SUBDEV_I2C ] = &nvd0_i2c_oclass;
device->oclass[NVDEV_SUBDEV_CLOCK ] = &nve0_clock_oclass;
device->oclass[NVDEV_SUBDEV_THERM ] = &nvd0_therm_oclass;
device->oclass[NVDEV_SUBDEV_MXM ] = &nv50_mxm_oclass;
device->oclass[NVDEV_SUBDEV_DEVINIT] = &nvc0_devinit_oclass;
device->oclass[NVDEV_SUBDEV_MC ] = nvc3_mc_oclass;
device->oclass[NVDEV_SUBDEV_BUS ] = nvc0_bus_oclass;
device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
device->oclass[NVDEV_SUBDEV_FB ] = nve0_fb_oclass;
device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
device->oclass[NVDEV_SUBDEV_IBUS ] = &nve0_ibus_oclass;
device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
device->oclass[NVDEV_SUBDEV_PWR ] = &nv108_pwr_oclass;
device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass;
device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvd0_dmaeng_oclass;
#if 0
device->oclass[NVDEV_ENGINE_FIFO ] = nve0_fifo_oclass;
device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
device->oclass[NVDEV_ENGINE_GR ] = nvf0_graph_oclass;
#endif
device->oclass[NVDEV_ENGINE_DISP ] = &nvf0_disp_oclass;
#if 0
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
#endif
break;
default:

8
drivers/gpu/drm/nouveau/core/engine/device/priv.h Normal file
View File

@ -0,0 +1,8 @@
#ifndef __NVKM_DEVICE_PRIV_H__
#define __NVKM_DEVICE_PRIV_H__
#include <engine/device.h>
extern struct nouveau_oclass nouveau_control_oclass[];
#endif

52
drivers/gpu/drm/nouveau/core/engine/disp/dport.c
View File

@ -70,17 +70,10 @@ dp_set_link_config(struct dp_state *dp)
};
u32 lnkcmp;
u8 sink[2];
int ret;
DBG("%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
/* set desired link configuration on the sink */
sink[0] = dp->link_bw / 27000;
sink[1] = dp->link_nr;
if (dp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP)
sink[1] |= DPCD_LC01_ENHANCED_FRAME_EN;
nv_wraux(dp->aux, DPCD_LC00, sink, 2);
/* set desired link configuration on the source */
if ((lnkcmp = dp->info.lnkcmp)) {
if (dp->version < 0x30) {
@ -96,10 +89,22 @@ dp_set_link_config(struct dp_state *dp)
nvbios_exec(&init);
}
return dp->func->lnk_ctl(dp->disp, dp->outp, dp->head,
dp->link_nr, dp->link_bw / 27000,
dp->dpcd[DPCD_RC02] &
DPCD_RC02_ENHANCED_FRAME_CAP);
ret = dp->func->lnk_ctl(dp->disp, dp->outp, dp->head,
dp->link_nr, dp->link_bw / 27000,
dp->dpcd[DPCD_RC02] &
DPCD_RC02_ENHANCED_FRAME_CAP);
if (ret) {
ERR("lnk_ctl failed with %d\n", ret);
return ret;
}
/* set desired link configuration on the sink */
sink[0] = dp->link_bw / 27000;
sink[1] = dp->link_nr;
if (dp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP)
sink[1] |= DPCD_LC01_ENHANCED_FRAME_EN;
return nv_wraux(dp->aux, DPCD_LC00, sink, 2);
}
static void
@ -294,8 +299,17 @@ nouveau_dp_train(struct nouveau_disp *disp, const struct nouveau_dp_func *func,
ret = nv_rdaux(dp->aux, 0x00000, dp->dpcd, sizeof(dp->dpcd));
if (ret) {
/* it's possible the display has been unplugged before we
* get here. we still need to execute the full set of
* vbios scripts, and program the OR at a high enough
* frequency to satisfy the target mode. failure to do
* so results at best in an UPDATE hanging, and at worst
* with PDISP running away to join the circus.
*/
dp->dpcd[1] = link_bw[0] / 27000;
dp->dpcd[2] = 4;
dp->dpcd[3] = 0x00;
ERR("failed to read DPCD\n");
return ret;
}
/* adjust required bandwidth for 8B/10B coding overhead */
@ -308,7 +322,7 @@ nouveau_dp_train(struct nouveau_disp *disp, const struct nouveau_dp_func *func,
while (*link_bw > (dp->dpcd[1] * 27000))
link_bw++;
while (link_bw[0]) {
while ((ret = -EIO) && link_bw[0]) {
/* find minimum required lane count at this link rate */
dp->link_nr = dp->dpcd[2] & DPCD_RC02_MAX_LANE_COUNT;
while ((dp->link_nr >> 1) * link_bw[0] > datarate)
@ -328,8 +342,10 @@ nouveau_dp_train(struct nouveau_disp *disp, const struct nouveau_dp_func *func,
!dp_link_train_eq(dp))
break;
} else
if (ret >= 1) {
/* dp_set_link_config() handled training */
if (ret) {
/* dp_set_link_config() handled training, or
* we failed to communicate with the sink.
*/
break;
}
@ -339,8 +355,10 @@ nouveau_dp_train(struct nouveau_disp *disp, const struct nouveau_dp_func *func,
/* finish link training */
dp_set_training_pattern(dp, 0);
if (ret < 0)
ERR("link training failed\n");
/* execute post-train script from vbios */
dp_link_train_fini(dp);
return true;
return (ret < 0) ? false : true;
}

9
drivers/gpu/drm/nouveau/core/engine/disp/nv04.c
View File

@ -59,6 +59,7 @@ nv04_disp_intr(struct nouveau_subdev *subdev)
struct nv04_disp_priv *priv = (void *)subdev;
u32 crtc0 = nv_rd32(priv, 0x600100);
u32 crtc1 = nv_rd32(priv, 0x602100);
u32 pvideo;
if (crtc0 & 0x00000001) {
nouveau_event_trigger(priv->base.vblank, 0);
@ -69,6 +70,14 @@ nv04_disp_intr(struct nouveau_subdev *subdev)
nouveau_event_trigger(priv->base.vblank, 1);
nv_wr32(priv, 0x602100, 0x00000001);
}
if (nv_device(priv)->chipset >= 0x10 &&
nv_device(priv)->chipset <= 0x40) {
pvideo = nv_rd32(priv, 0x8100);
if (pvideo & ~0x11)
nv_info(priv, "PVIDEO intr: %08x\n", pvideo);
nv_wr32(priv, 0x8100, pvideo);
}
}
static int

9
drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
View File

@ -541,6 +541,15 @@ nvd0_disp_base_init(struct nouveau_object *object)
nv_wr32(priv, 0x6100a0, 0x00000000);
nv_wr32(priv, 0x6100b0, 0x00000307);
/* disable underflow reporting, preventing an intermittent issue
* on some nve4 boards where the production vbios left this
* setting enabled by default.
*
* ftp://download.nvidia.com/open-gpu-doc/gk104-disable-underflow-reporting/1/gk104-disable-underflow-reporting.txt
*/
for (i = 0; i < priv->head.nr; i++)
nv_mask(priv, 0x616308 + (i * 0x800), 0x00000111, 0x00000010);
return 0;
}

12
drivers/gpu/drm/nouveau/core/engine/disp/sornv94.c
View File

@ -97,8 +97,9 @@ nv94_sor_dp_drv_ctl(struct nouveau_disp *disp, struct dcb_output *outp,
{
struct nouveau_bios *bios = nouveau_bios(disp);
struct nv50_disp_priv *priv = (void *)disp;
const u32 shift = nv94_sor_dp_lane_map(priv, lane);
const u32 loff = nv94_sor_loff(outp);
u32 addr, shift = nv94_sor_dp_lane_map(priv, lane);
u32 addr, data[3];
u8 ver, hdr, cnt, len;
struct nvbios_dpout info;
struct nvbios_dpcfg ocfg;
@ -113,9 +114,12 @@ nv94_sor_dp_drv_ctl(struct nouveau_disp *disp, struct dcb_output *outp,
if (!addr)
return -EINVAL;
nv_mask(priv, 0x61c118 + loff, 0x000000ff << shift, ocfg.drv << shift);
nv_mask(priv, 0x61c120 + loff, 0x000000ff << shift, ocfg.pre << shift);
nv_mask(priv, 0x61c130 + loff, 0x0000ff00, ocfg.unk << 8);
data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift);
data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift);
data[2] = nv_rd32(priv, 0x61c130 + loff) & ~(0x0000ff00);
nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.drv << shift));
nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pre << shift));
nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.unk << 8));
return 0;
}

12
drivers/gpu/drm/nouveau/core/engine/disp/sornvd0.c
View File

@ -93,8 +93,9 @@ nvd0_sor_dp_drv_ctl(struct nouveau_disp *disp, struct dcb_output *outp,
{
struct nouveau_bios *bios = nouveau_bios(disp);
struct nv50_disp_priv *priv = (void *)disp;
const u32 shift = nvd0_sor_dp_lane_map(priv, lane);
const u32 loff = nvd0_sor_loff(outp);
u32 addr, shift = nvd0_sor_dp_lane_map(priv, lane);
u32 addr, data[3];
u8 ver, hdr, cnt, len;
struct nvbios_dpout info;
struct nvbios_dpcfg ocfg;
@ -109,9 +110,12 @@ nvd0_sor_dp_drv_ctl(struct nouveau_disp *disp, struct dcb_output *outp,
if (!addr)
return -EINVAL;
nv_mask(priv, 0x61c118 + loff, 0x000000ff << shift, ocfg.drv << shift);
nv_mask(priv, 0x61c120 + loff, 0x000000ff << shift, ocfg.pre << shift);
nv_mask(priv, 0x61c130 + loff, 0x0000ff00, ocfg.unk << 8);
data[0] = nv_rd32(priv, 0x61c118 + loff) & ~(0x000000ff << shift);
data[1] = nv_rd32(priv, 0x61c120 + loff) & ~(0x000000ff << shift);
data[2] = nv_rd32(priv, 0x61c130 + loff) & ~(0x0000ff00);
nv_wr32(priv, 0x61c118 + loff, data[0] | (ocfg.drv << shift));
nv_wr32(priv, 0x61c120 + loff, data[1] | (ocfg.pre << shift));
nv_wr32(priv, 0x61c130 + loff, data[2] | (ocfg.unk << 8));
nv_mask(priv, 0x61c13c + loff, 0x00000000, 0x00000000);
return 0;
}

4
drivers/gpu/drm/nouveau/core/engine/fifo/nv04.c
View File

@ -632,8 +632,8 @@ nv04_fifo_init(struct nouveau_object *object)
return 0;
}
struct nouveau_oclass
nv04_fifo_oclass = {
struct nouveau_oclass *
nv04_fifo_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(FIFO, 0x04),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_fifo_ctor,

4
drivers/gpu/drm/nouveau/core/engine/fifo/nv10.c
View File

@ -159,8 +159,8 @@ nv10_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
struct nouveau_oclass
nv10_fifo_oclass = {
struct nouveau_oclass *
nv10_fifo_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(FIFO, 0x10),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv10_fifo_ctor,

4
drivers/gpu/drm/nouveau/core/engine/fifo/nv17.c
View File

@ -196,8 +196,8 @@ nv17_fifo_init(struct nouveau_object *object)
return 0;
}
struct nouveau_oclass
nv17_fifo_oclass = {
struct nouveau_oclass *
nv17_fifo_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(FIFO, 0x17),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv17_fifo_ctor,

4
drivers/gpu/drm/nouveau/core/engine/fifo/nv40.c
View File

@ -337,8 +337,8 @@ nv40_fifo_init(struct nouveau_object *object)
return 0;
}
struct nouveau_oclass
nv40_fifo_oclass = {
struct nouveau_oclass *
nv40_fifo_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(FIFO, 0x40),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv40_fifo_ctor,

4
drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
View File

@ -502,8 +502,8 @@ nv50_fifo_init(struct nouveau_object *object)
return 0;
}
struct nouveau_oclass
nv50_fifo_oclass = {
struct nouveau_oclass *
nv50_fifo_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(FIFO, 0x50),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_fifo_ctor,

10
drivers/gpu/drm/nouveau/core/engine/fifo/nv84.c
View File

@ -144,7 +144,7 @@ nv84_fifo_object_attach(struct nouveau_object *parent,
case NVDEV_ENGINE_COPY0 : context |= 0x00300000; break;
case NVDEV_ENGINE_VP : context |= 0x00400000; break;
case NVDEV_ENGINE_CRYPT :
case NVDEV_ENGINE_UNK1C1: context |= 0x00500000; break;
case NVDEV_ENGINE_VIC : context |= 0x00500000; break;
case NVDEV_ENGINE_BSP : context |= 0x00600000; break;
default:
return -EINVAL;
@ -180,7 +180,7 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
(1ULL << NVDEV_ENGINE_BSP) |
(1ULL << NVDEV_ENGINE_PPP) |
(1ULL << NVDEV_ENGINE_COPY0) |
(1ULL << NVDEV_ENGINE_UNK1C1), &chan);
(1ULL << NVDEV_ENGINE_VIC), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@ -243,7 +243,7 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
(1ULL << NVDEV_ENGINE_BSP) |
(1ULL << NVDEV_ENGINE_PPP) |
(1ULL << NVDEV_ENGINE_COPY0) |
(1ULL << NVDEV_ENGINE_UNK1C1), &chan);
(1ULL << NVDEV_ENGINE_VIC), &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
@ -435,8 +435,8 @@ nv84_fifo_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
struct nouveau_oclass
nv84_fifo_oclass = {
struct nouveau_oclass *
nv84_fifo_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(FIFO, 0x84),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv84_fifo_ctor,

4
drivers/gpu/drm/nouveau/core/engine/fifo/nvc0.c
View File

@ -720,8 +720,8 @@ nvc0_fifo_init(struct nouveau_object *object)
return 0;
}
struct nouveau_oclass
nvc0_fifo_oclass = {
struct nouveau_oclass *
nvc0_fifo_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(FIFO, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_fifo_ctor,

4
drivers/gpu/drm/nouveau/core/engine/fifo/nve0.c
View File

@ -675,8 +675,8 @@ nve0_fifo_init(struct nouveau_object *object)
return 0;
}
struct nouveau_oclass
nve0_fifo_oclass = {
struct nouveau_oclass *
nve0_fifo_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(FIFO, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nve0_fifo_ctor,

4
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc1.c
View File

@ -587,6 +587,7 @@ nvc1_grctx_init_unk58xx[] = {
{ 0x405870, 4, 0x04, 0x00000001 },
{ 0x405a00, 2, 0x04, 0x00000000 },
{ 0x405a18, 1, 0x04, 0x00000000 },
{}
};
static struct nvc0_graph_init
@ -598,6 +599,7 @@ nvc1_grctx_init_rop[] = {
{ 0x408904, 1, 0x04, 0x62000001 },
{ 0x408908, 1, 0x04, 0x00c80929 },
{ 0x408980, 1, 0x04, 0x0000011d },
{}
};
static struct nvc0_graph_init
@ -671,6 +673,7 @@ nvc1_grctx_init_gpc_0[] = {
{ 0x419000, 1, 0x04, 0x00000780 },
{ 0x419004, 2, 0x04, 0x00000000 },
{ 0x419014, 1, 0x04, 0x00000004 },
{}
};
static struct nvc0_graph_init
@ -717,6 +720,7 @@ nvc1_grctx_init_tpc[] = {
{ 0x419e98, 1, 0x04, 0x00000000 },
{ 0x419ee0, 1, 0x04, 0x00011110 },
{ 0x419f30, 11, 0x04, 0x00000000 },
{}
};
void

1
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd7.c
View File

@ -258,6 +258,7 @@ nvd7_grctx_init_hub[] = {
nvc0_grctx_init_unk78xx,
nvc0_grctx_init_unk80xx,
nvd9_grctx_init_rop,
NULL
};
struct nvc0_graph_init *

1
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvd9.c
View File

@ -466,6 +466,7 @@ nvd9_grctx_init_hub[] = {
nvc0_grctx_init_unk78xx,
nvc0_grctx_init_unk80xx,
nvd9_grctx_init_rop,
NULL
};
struct nvc0_graph_init *

14
drivers/gpu/drm/nouveau/core/engine/graph/nv10.c
View File

@ -945,7 +945,8 @@ nv10_graph_load_context(struct nv10_graph_chan *chan, int chid)
for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++)
nv_wr32(priv, nv10_graph_ctx_regs[i], chan->nv10[i]);
if (nv_device(priv)->chipset >= 0x17) {
if (nv_device(priv)->card_type >= NV_11 &&
nv_device(priv)->chipset >= 0x17) {
for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++)
nv_wr32(priv, nv17_graph_ctx_regs[i], chan->nv17[i]);
}
@ -970,7 +971,8 @@ nv10_graph_unload_context(struct nv10_graph_chan *chan)
for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++)
chan->nv10[i] = nv_rd32(priv, nv10_graph_ctx_regs[i]);
if (nv_device(priv)->chipset >= 0x17) {
if (nv_device(priv)->card_type >= NV_11 &&
nv_device(priv)->chipset >= 0x17) {
for (i = 0; i < ARRAY_SIZE(nv17_graph_ctx_regs); i++)
chan->nv17[i] = nv_rd32(priv, nv17_graph_ctx_regs[i]);
}
@ -1052,7 +1054,8 @@ nv10_graph_context_ctor(struct nouveau_object *parent,
NV_WRITE_CTX(0x00400e14, 0x00001000);
NV_WRITE_CTX(0x00400e30, 0x00080008);
NV_WRITE_CTX(0x00400e34, 0x00080008);
if (nv_device(priv)->chipset >= 0x17) {
if (nv_device(priv)->card_type >= NV_11 &&
nv_device(priv)->chipset >= 0x17) {
/* is it really needed ??? */
NV17_WRITE_CTX(NV10_PGRAPH_DEBUG_4,
nv_rd32(priv, NV10_PGRAPH_DEBUG_4));
@ -1231,7 +1234,7 @@ nv10_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
nv_engine(priv)->sclass = nv10_graph_sclass;
else
if (nv_device(priv)->chipset < 0x17 ||
nv_device(priv)->chipset == 0x1a)
nv_device(priv)->card_type < NV_11)
nv_engine(priv)->sclass = nv15_graph_sclass;
else
nv_engine(priv)->sclass = nv17_graph_sclass;
@ -1270,7 +1273,8 @@ nv10_graph_init(struct nouveau_object *object)
nv_wr32(priv, NV04_PGRAPH_DEBUG_2, 0x25f92ad9);
nv_wr32(priv, NV04_PGRAPH_DEBUG_3, 0x55DE0830 | (1 << 29) | (1 << 31));
if (nv_device(priv)->chipset >= 0x17) {
if (nv_device(priv)->card_type >= NV_11 &&
nv_device(priv)->chipset >= 0x17) {
nv_wr32(priv, NV10_PGRAPH_DEBUG_4, 0x1f000000);
nv_wr32(priv, 0x400a10, 0x03ff3fb6);
nv_wr32(priv, 0x400838, 0x002f8684);

2
drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c
View File

@ -1138,7 +1138,7 @@ nvc0_graph_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
if (ret)
return ret;
nv_subdev(priv)->unit = 0x18001000;
nv_subdev(priv)->unit = 0x08001000;
nv_subdev(priv)->intr = nvc0_graph_intr;
priv->base.units = nvc0_graph_units;

70
drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
View File

@ -34,16 +34,7 @@
#include <engine/fifo.h>
#include <engine/mpeg.h>
#include <engine/graph/nv40.h>
struct nv31_mpeg_priv {
struct nouveau_mpeg base;
atomic_t refcount;
};
struct nv31_mpeg_chan {
struct nouveau_object base;
};
#include <engine/mpeg/nv31.h>
/*******************************************************************************
* MPEG object classes
@ -89,18 +80,18 @@ nv31_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len)
if (mthd == 0x0190) {
/* DMA_CMD */
nv_mask(priv, 0x00b300, 0x00030000, (dma0 & 0x00030000));
nv_mask(priv, 0x00b300, 0x00010000, (dma0 & 0x00030000) ? 0x00010000 : 0);
nv_wr32(priv, 0x00b334, base);
nv_wr32(priv, 0x00b324, size);
} else
if (mthd == 0x01a0) {
/* DMA_DATA */
nv_mask(priv, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2);
nv_mask(priv, 0x00b300, 0x00020000, (dma0 & 0x00030000) ? 0x00020000 : 0);
nv_wr32(priv, 0x00b360, base);
nv_wr32(priv, 0x00b364, size);
} else {
/* DMA_IMAGE, VRAM only */
if (dma0 & 0x000c0000)
if (dma0 & 0x00030000)
return -EINVAL;
nv_wr32(priv, 0x00b370, base);
@ -110,7 +101,7 @@ nv31_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len)
return 0;
}
static struct nouveau_ofuncs
struct nouveau_ofuncs
nv31_mpeg_ofuncs = {
.ctor = nv31_mpeg_object_ctor,
.dtor = _nouveau_gpuobj_dtor,
@ -146,16 +137,23 @@ nv31_mpeg_context_ctor(struct nouveau_object *parent,
{
struct nv31_mpeg_priv *priv = (void *)engine;
struct nv31_mpeg_chan *chan;
unsigned long flags;
int ret;
if (!atomic_add_unless(&priv->refcount, 1, 1))
return -EBUSY;
ret = nouveau_object_create(parent, engine, oclass, 0, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
spin_lock_irqsave(&nv_engine(priv)->lock, flags);
if (priv->chan) {
spin_unlock_irqrestore(&nv_engine(priv)->lock, flags);
nouveau_object_destroy(&chan->base);
*pobject = NULL;
return -EBUSY;
}
priv->chan = chan;
spin_unlock_irqrestore(&nv_engine(priv)->lock, flags);
return 0;
}
@ -164,11 +162,15 @@ nv31_mpeg_context_dtor(struct nouveau_object *object)
{
struct nv31_mpeg_priv *priv = (void *)object->engine;
struct nv31_mpeg_chan *chan = (void *)object;
atomic_dec(&priv->refcount);
unsigned long flags;
spin_lock_irqsave(&nv_engine(priv)->lock, flags);
priv->chan = NULL;
spin_unlock_irqrestore(&nv_engine(priv)->lock, flags);
nouveau_object_destroy(&chan->base);
}
static struct nouveau_oclass
struct nouveau_oclass
nv31_mpeg_cclass = {
.handle = NV_ENGCTX(MPEG, 0x31),
.ofuncs = &(struct nouveau_ofuncs) {
@ -197,21 +199,19 @@ nv31_mpeg_tile_prog(struct nouveau_engine *engine, int i)
void
nv31_mpeg_intr(struct nouveau_subdev *subdev)
{
struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
struct nouveau_engine *engine = nv_engine(subdev);
struct nouveau_object *engctx;
struct nouveau_handle *handle;
struct nv31_mpeg_priv *priv = (void *)subdev;
u32 inst = nv_rd32(priv, 0x00b318) & 0x000fffff;
struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
struct nouveau_handle *handle;
struct nouveau_object *engctx;
u32 stat = nv_rd32(priv, 0x00b100);
u32 type = nv_rd32(priv, 0x00b230);
u32 mthd = nv_rd32(priv, 0x00b234);
u32 data = nv_rd32(priv, 0x00b238);
u32 show = stat;
int chid;
unsigned long flags;
engctx = nouveau_engctx_get(engine, inst);
chid = pfifo->chid(pfifo, engctx);
spin_lock_irqsave(&nv_engine(priv)->lock, flags);
engctx = nv_object(priv->chan);
if (stat & 0x01000000) {
/* happens on initial binding of the object */
@ -220,7 +220,7 @@ nv31_mpeg_intr(struct nouveau_subdev *subdev)
show &= ~0x01000000;
}
if (type == 0x00000010) {
if (type == 0x00000010 && engctx) {
handle = nouveau_handle_get_class(engctx, 0x3174);
if (handle && !nv_call(handle->object, mthd, data))
show &= ~0x01000000;
@ -232,13 +232,12 @@ nv31_mpeg_intr(struct nouveau_subdev *subdev)
nv_wr32(priv, 0x00b230, 0x00000001);
if (show) {
nv_error(priv,
"ch %d [0x%08x %s] 0x%08x 0x%08x 0x%08x 0x%08x\n",
chid, inst << 4, nouveau_client_name(engctx), stat,
type, mthd, data);
nv_error(priv, "ch %d [%s] 0x%08x 0x%08x 0x%08x 0x%08x\n",
pfifo->chid(pfifo, engctx),
nouveau_client_name(engctx), stat, type, mthd, data);
}
nouveau_engctx_put(engctx);
spin_unlock_irqrestore(&nv_engine(priv)->lock, flags);
}
static int
@ -284,10 +283,7 @@ nv31_mpeg_init(struct nouveau_object *object)
/* PMPEG init */
nv_wr32(priv, 0x00b32c, 0x00000000);
nv_wr32(priv, 0x00b314, 0x00000100);
if (nv_device(priv)->chipset >= 0x40 && nv44_graph_class(priv))
nv_wr32(priv, 0x00b220, 0x00000044);
else
nv_wr32(priv, 0x00b220, 0x00000031);
nv_wr32(priv, 0x00b220, 0x00000031);
nv_wr32(priv, 0x00b300, 0x02001ec1);
nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001);

15
drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.h Normal file
View File

@ -0,0 +1,15 @@
#ifndef __NV31_MPEG_H__
#define __NV31_MPEG_H__
#include <engine/mpeg.h>
struct nv31_mpeg_chan {
struct nouveau_object base;
};
struct nv31_mpeg_priv {
struct nouveau_mpeg base;
struct nv31_mpeg_chan *chan;
};
#endif

101
drivers/gpu/drm/nouveau/core/engine/mpeg/nv40.c
View File

@ -31,66 +31,63 @@
#include <subdev/instmem.h>
#include <engine/mpeg.h>
#include <engine/graph/nv40.h>
struct nv40_mpeg_priv {
struct nouveau_mpeg base;
};
struct nv40_mpeg_chan {
struct nouveau_mpeg_chan base;
};
#include <engine/mpeg/nv31.h>
/*******************************************************************************
* PMPEG context
* MPEG object classes
******************************************************************************/
static int
nv40_mpeg_context_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
nv40_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len)
{
struct nv40_mpeg_chan *chan;
int ret;
struct nouveau_instmem *imem = nouveau_instmem(object);
struct nv31_mpeg_priv *priv = (void *)object->engine;
u32 inst = *(u32 *)arg << 4;
u32 dma0 = nv_ro32(imem, inst + 0);
u32 dma1 = nv_ro32(imem, inst + 4);
u32 dma2 = nv_ro32(imem, inst + 8);
u32 base = (dma2 & 0xfffff000) | (dma0 >> 20);
u32 size = dma1 + 1;
ret = nouveau_mpeg_context_create(parent, engine, oclass, NULL,
264 * 4, 16,
NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
/* only allow linear DMA objects */
if (!(dma0 & 0x00002000))
return -EINVAL;
if (mthd == 0x0190) {
/* DMA_CMD */
nv_mask(priv, 0x00b300, 0x00030000, (dma0 & 0x00030000));
nv_wr32(priv, 0x00b334, base);
nv_wr32(priv, 0x00b324, size);
} else
if (mthd == 0x01a0) {
/* DMA_DATA */
nv_mask(priv, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2);
nv_wr32(priv, 0x00b360, base);
nv_wr32(priv, 0x00b364, size);
} else {
/* DMA_IMAGE, VRAM only */
if (dma0 & 0x00030000)
return -EINVAL;
nv_wr32(priv, 0x00b370, base);
nv_wr32(priv, 0x00b374, size);
}
nv_wo32(&chan->base.base, 0x78, 0x02001ec1);
return 0;
}
static int
nv40_mpeg_context_fini(struct nouveau_object *object, bool suspend)
{
static struct nouveau_omthds
nv40_mpeg_omthds[] = {
{ 0x0190, 0x0190, nv40_mpeg_mthd_dma },
{ 0x01a0, 0x01a0, nv40_mpeg_mthd_dma },
{ 0x01b0, 0x01b0, nv40_mpeg_mthd_dma },
{}
};
struct nv40_mpeg_priv *priv = (void *)object->engine;
struct nv40_mpeg_chan *chan = (void *)object;
u32 inst = 0x80000000 | nv_gpuobj(chan)->addr >> 4;
nv_mask(priv, 0x00b32c, 0x00000001, 0x00000000);
if (nv_rd32(priv, 0x00b318) == inst)
nv_mask(priv, 0x00b318, 0x80000000, 0x00000000);
nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001);
return 0;
}
static struct nouveau_oclass
nv40_mpeg_cclass = {
.handle = NV_ENGCTX(MPEG, 0x40),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv40_mpeg_context_ctor,
.dtor = _nouveau_mpeg_context_dtor,
.init = _nouveau_mpeg_context_init,
.fini = nv40_mpeg_context_fini,
.rd32 = _nouveau_mpeg_context_rd32,
.wr32 = _nouveau_mpeg_context_wr32,
},
struct nouveau_oclass
nv40_mpeg_sclass[] = {
{ 0x3174, &nv31_mpeg_ofuncs, nv40_mpeg_omthds },
{}
};
/*******************************************************************************
@ -100,7 +97,7 @@ nv40_mpeg_cclass = {
static void
nv40_mpeg_intr(struct nouveau_subdev *subdev)
{
struct nv40_mpeg_priv *priv = (void *)subdev;
struct nv31_mpeg_priv *priv = (void *)subdev;
u32 stat;
if ((stat = nv_rd32(priv, 0x00b100)))
@ -117,7 +114,7 @@ nv40_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv40_mpeg_priv *priv;
struct nv31_mpeg_priv *priv;
int ret;
ret = nouveau_mpeg_create(parent, engine, oclass, &priv);
@ -127,8 +124,8 @@ nv40_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
nv_subdev(priv)->unit = 0x00000002;
nv_subdev(priv)->intr = nv40_mpeg_intr;
nv_engine(priv)->cclass = &nv40_mpeg_cclass;
nv_engine(priv)->sclass = nv31_mpeg_sclass;
nv_engine(priv)->cclass = &nv31_mpeg_cclass;
nv_engine(priv)->sclass = nv40_mpeg_sclass;
nv_engine(priv)->tile_prog = nv31_mpeg_tile_prog;
return 0;
}

194
drivers/gpu/drm/nouveau/core/engine/mpeg/nv44.c Normal file
View File

@ -0,0 +1,194 @@
/*
* Copyright 2012 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <core/os.h>
#include <core/class.h>
#include <core/client.h>
#include <core/engctx.h>
#include <core/handle.h>
#include <subdev/fb.h>
#include <subdev/timer.h>
#include <subdev/instmem.h>
#include <engine/fifo.h>
#include <engine/mpeg.h>
struct nv44_mpeg_priv {
struct nouveau_mpeg base;
};
struct nv44_mpeg_chan {
struct nouveau_mpeg_chan base;
};
/*******************************************************************************
* PMPEG context
******************************************************************************/
static int
nv44_mpeg_context_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv44_mpeg_chan *chan;
int ret;
ret = nouveau_mpeg_context_create(parent, engine, oclass, NULL,
264 * 4, 16,
NVOBJ_FLAG_ZERO_ALLOC, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
nv_wo32(&chan->base.base, 0x78, 0x02001ec1);
return 0;
}
static int
nv44_mpeg_context_fini(struct nouveau_object *object, bool suspend)
{
struct nv44_mpeg_priv *priv = (void *)object->engine;
struct nv44_mpeg_chan *chan = (void *)object;
u32 inst = 0x80000000 | nv_gpuobj(chan)->addr >> 4;
nv_mask(priv, 0x00b32c, 0x00000001, 0x00000000);
if (nv_rd32(priv, 0x00b318) == inst)
nv_mask(priv, 0x00b318, 0x80000000, 0x00000000);
nv_mask(priv, 0x00b32c, 0x00000001, 0x00000001);
return 0;
}
static struct nouveau_oclass
nv44_mpeg_cclass = {
.handle = NV_ENGCTX(MPEG, 0x44),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv44_mpeg_context_ctor,
.dtor = _nouveau_mpeg_context_dtor,
.init = _nouveau_mpeg_context_init,
.fini = nv44_mpeg_context_fini,
.rd32 = _nouveau_mpeg_context_rd32,
.wr32 = _nouveau_mpeg_context_wr32,
},
};
/*******************************************************************************
* PMPEG engine/subdev functions
******************************************************************************/
static void
nv44_mpeg_intr(struct nouveau_subdev *subdev)
{
struct nouveau_fifo *pfifo = nouveau_fifo(subdev);
struct nouveau_engine *engine = nv_engine(subdev);
struct nouveau_object *engctx;
struct nouveau_handle *handle;
struct nv44_mpeg_priv *priv = (void *)subdev;
u32 inst = nv_rd32(priv, 0x00b318) & 0x000fffff;
u32 stat = nv_rd32(priv, 0x00b100);
u32 type = nv_rd32(priv, 0x00b230);
u32 mthd = nv_rd32(priv, 0x00b234);
u32 data = nv_rd32(priv, 0x00b238);
u32 show = stat;
int chid;
engctx = nouveau_engctx_get(engine, inst);
chid = pfifo->chid(pfifo, engctx);
if (stat & 0x01000000) {
/* happens on initial binding of the object */
if (type == 0x00000020 && mthd == 0x0000) {
nv_mask(priv, 0x00b308, 0x00000000, 0x00000000);
show &= ~0x01000000;
}
if (type == 0x00000010) {
handle = nouveau_handle_get_class(engctx, 0x3174);
if (handle && !nv_call(handle->object, mthd, data))
show &= ~0x01000000;
nouveau_handle_put(handle);
}
}
nv_wr32(priv, 0x00b100, stat);
nv_wr32(priv, 0x00b230, 0x00000001);
if (show) {
nv_error(priv,
"ch %d [0x%08x %s] 0x%08x 0x%08x 0x%08x 0x%08x\n",
chid, inst << 4, nouveau_client_name(engctx), stat,
type, mthd, data);
}
nouveau_engctx_put(engctx);
}
static void
nv44_mpeg_me_intr(struct nouveau_subdev *subdev)
{
struct nv44_mpeg_priv *priv = (void *)subdev;
u32 stat;
if ((stat = nv_rd32(priv, 0x00b100)))
nv44_mpeg_intr(subdev);
if ((stat = nv_rd32(priv, 0x00b800))) {
nv_error(priv, "PMSRCH 0x%08x\n", stat);
nv_wr32(priv, 0x00b800, stat);
}
}
static int
nv44_mpeg_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv44_mpeg_priv *priv;
int ret;
ret = nouveau_mpeg_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->unit = 0x00000002;
nv_subdev(priv)->intr = nv44_mpeg_me_intr;
nv_engine(priv)->cclass = &nv44_mpeg_cclass;
nv_engine(priv)->sclass = nv40_mpeg_sclass;
nv_engine(priv)->tile_prog = nv31_mpeg_tile_prog;
return 0;
}
struct nouveau_oclass
nv44_mpeg_oclass = {
.handle = NV_ENGINE(MPEG, 0x44),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv44_mpeg_ctor,
.dtor = _nouveau_mpeg_dtor,
.init = nv31_mpeg_init,
.fini = _nouveau_mpeg_fini,
},
};

449
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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <core/option.h>
#include <core/class.h>
#include <subdev/clock.h>
#include "priv.h"
#define QUAD_MASK 0x0f
#define QUAD_FREE 0x01
static struct nouveau_perfsig *
nouveau_perfsig_find_(struct nouveau_perfdom *dom, const char *name, u32 size)
{
char path[64];
int i;
if (name[0] != '/') {
for (i = 0; i < dom->signal_nr; i++) {
if ( dom->signal[i].name &&
!strncmp(name, dom->signal[i].name, size))
return &dom->signal[i];
}
} else {
for (i = 0; i < dom->signal_nr; i++) {
snprintf(path, sizeof(path), "/%s/%02x", dom->name, i);
if (!strncmp(name, path, size))
return &dom->signal[i];
}
}
return NULL;
}
struct nouveau_perfsig *
nouveau_perfsig_find(struct nouveau_perfmon *ppm, const char *name, u32 size,
struct nouveau_perfdom **pdom)
{
struct nouveau_perfdom *dom = *pdom;
struct nouveau_perfsig *sig;
if (dom == NULL) {
list_for_each_entry(dom, &ppm->domains, head) {
sig = nouveau_perfsig_find_(dom, name, size);
if (sig) {
*pdom = dom;
return sig;
}
}
return NULL;
}
return nouveau_perfsig_find_(dom, name, size);
}
struct nouveau_perfctr *
nouveau_perfsig_wrap(struct nouveau_perfmon *ppm, const char *name,
struct nouveau_perfdom **pdom)
{
struct nouveau_perfsig *sig;
struct nouveau_perfctr *ctr;
sig = nouveau_perfsig_find(ppm, name, strlen(name), pdom);
if (!sig)
return NULL;
ctr = kzalloc(sizeof(*ctr), GFP_KERNEL);
if (ctr) {
ctr->signal[0] = sig;
ctr->logic_op = 0xaaaa;
}
return ctr;
}
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
static int
nouveau_perfctr_query(struct nouveau_object *object, u32 mthd,
void *data, u32 size)
{
struct nouveau_device *device = nv_device(object);
struct nouveau_perfmon *ppm = (void *)object->engine;
struct nouveau_perfdom *dom = NULL, *chk;
struct nv_perfctr_query *args = data;
const bool all = nouveau_boolopt(device->cfgopt, "NvPmShowAll", false);
const bool raw = nouveau_boolopt(device->cfgopt, "NvPmUnnamed", all);
const char *name;
int tmp = 0, di, si;
char path[64];
if (size < sizeof(*args))
return -EINVAL;
di = (args->iter & 0xff000000) >> 24;
si = (args->iter & 0x00ffffff) - 1;
list_for_each_entry(chk, &ppm->domains, head) {
if (tmp++ == di) {
dom = chk;
break;
}
}
if (dom == NULL || si >= (int)dom->signal_nr)
return -EINVAL;
if (si >= 0) {
if (raw || !(name = dom->signal[si].name)) {
snprintf(path, sizeof(path), "/%s/%02x", dom->name, si);
name = path;
}
if (args->name)
strncpy(args->name, name, args->size);
args->size = strlen(name) + 1;
}
do {
while (++si < dom->signal_nr) {
if (all || dom->signal[si].name) {
args->iter = (di << 24) | ++si;
return 0;
}
}
si = -1;
di = di + 1;
dom = list_entry(dom->head.next, typeof(*dom), head);
} while (&dom->head != &ppm->domains);
args->iter = 0xffffffff;
return 0;
}
static int
nouveau_perfctr_sample(struct nouveau_object *object, u32 mthd,
void *data, u32 size)
{
struct nouveau_perfmon *ppm = (void *)object->engine;
struct nouveau_perfctr *ctr, *tmp;
struct nouveau_perfdom *dom;
struct nv_perfctr_sample *args = data;
if (size < sizeof(*args))
return -EINVAL;
ppm->sequence++;
list_for_each_entry(dom, &ppm->domains, head) {
/* sample previous batch of counters */
if (dom->quad != QUAD_MASK) {
dom->func->next(ppm, dom);
tmp = NULL;
while (!list_empty(&dom->list)) {
ctr = list_first_entry(&dom->list,
typeof(*ctr), head);
if (ctr->slot < 0) break;
if ( tmp && tmp == ctr) break;
if (!tmp) tmp = ctr;
dom->func->read(ppm, dom, ctr);
ctr->slot = -1;
list_move_tail(&ctr->head, &dom->list);
}
}
dom->quad = QUAD_MASK;
/* setup next batch of counters for sampling */
list_for_each_entry(ctr, &dom->list, head) {
ctr->slot = ffs(dom->quad) - 1;
if (ctr->slot < 0)
break;
dom->quad &= ~(QUAD_FREE << ctr->slot);
dom->func->init(ppm, dom, ctr);
}
if (dom->quad != QUAD_MASK)
dom->func->next(ppm, dom);
}
return 0;
}
static int
nouveau_perfctr_read(struct nouveau_object *object, u32 mthd,
void *data, u32 size)
{
struct nouveau_perfctr *ctr = (void *)object;
struct nv_perfctr_read *args = data;
if (size < sizeof(*args))
return -EINVAL;
if (!ctr->clk)
return -EAGAIN;
args->clk = ctr->clk;
args->ctr = ctr->ctr;
return 0;
}
static void
nouveau_perfctr_dtor(struct nouveau_object *object)
{
struct nouveau_perfctr *ctr = (void *)object;
if (ctr->head.next)
list_del(&ctr->head);
nouveau_object_destroy(&ctr->base);
}
static int
nouveau_perfctr_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nouveau_perfmon *ppm = (void *)engine;
struct nouveau_perfdom *dom = NULL;
struct nouveau_perfsig *sig[4] = {};
struct nouveau_perfctr *ctr;
struct nv_perfctr_class *args = data;
int ret, i;
if (size < sizeof(*args))
return -EINVAL;
for (i = 0; i < ARRAY_SIZE(args->signal) && args->signal[i].name; i++) {
sig[i] = nouveau_perfsig_find(ppm, args->signal[i].name,
args->signal[i].size, &dom);
if (!sig[i])
return -EINVAL;
}
ret = nouveau_object_create(parent, engine, oclass, 0, &ctr);
*pobject = nv_object(ctr);
if (ret)
return ret;
ctr->slot = -1;
ctr->logic_op = args->logic_op;
ctr->signal[0] = sig[0];
ctr->signal[1] = sig[1];
ctr->signal[2] = sig[2];
ctr->signal[3] = sig[3];
if (dom)
list_add_tail(&ctr->head, &dom->list);
return 0;
}
static struct nouveau_ofuncs
nouveau_perfctr_ofuncs = {
.ctor = nouveau_perfctr_ctor,
.dtor = nouveau_perfctr_dtor,
.init = nouveau_object_init,
.fini = nouveau_object_fini,
};
static struct nouveau_omthds
nouveau_perfctr_omthds[] = {
{ NV_PERFCTR_QUERY, NV_PERFCTR_QUERY, nouveau_perfctr_query },
{ NV_PERFCTR_SAMPLE, NV_PERFCTR_SAMPLE, nouveau_perfctr_sample },
{ NV_PERFCTR_READ, NV_PERFCTR_READ, nouveau_perfctr_read },
{}
};
struct nouveau_oclass
nouveau_perfmon_sclass[] = {
{ .handle = NV_PERFCTR_CLASS,
.ofuncs = &nouveau_perfctr_ofuncs,
.omthds = nouveau_perfctr_omthds,
},
{},
};
/*******************************************************************************
* PPM context
******************************************************************************/
static void
nouveau_perfctx_dtor(struct nouveau_object *object)
{
struct nouveau_perfmon *ppm = (void *)object->engine;
mutex_lock(&nv_subdev(ppm)->mutex);
ppm->context = NULL;
mutex_unlock(&nv_subdev(ppm)->mutex);
}
static int
nouveau_perfctx_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nouveau_perfmon *ppm = (void *)engine;
struct nouveau_perfctx *ctx;
int ret;
ret = nouveau_engctx_create(parent, engine, oclass, NULL,
0, 0, 0, &ctx);
*pobject = nv_object(ctx);
if (ret)
return ret;
mutex_lock(&nv_subdev(ppm)->mutex);
if (ppm->context == NULL)
ppm->context = ctx;
mutex_unlock(&nv_subdev(ppm)->mutex);
if (ctx != ppm->context)
return -EBUSY;
return 0;
}
struct nouveau_oclass
nouveau_perfmon_cclass = {
.handle = NV_ENGCTX(PERFMON, 0x00),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nouveau_perfctx_ctor,
.dtor = nouveau_perfctx_dtor,
.init = _nouveau_engctx_init,
.fini = _nouveau_engctx_fini,
},
};
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
int
nouveau_perfdom_new(struct nouveau_perfmon *ppm, const char *name, u32 mask,
u32 base, u32 size_unit, u32 size_domain,
const struct nouveau_specdom *spec)
{
const struct nouveau_specdom *sdom;
const struct nouveau_specsig *ssig;
struct nouveau_perfdom *dom;
int i;
for (i = 0; i == 0 || mask; i++) {
u32 addr = base + (i * size_unit);
if (i && !(mask & (1 << i)))
continue;
sdom = spec;
while (sdom->signal_nr) {
dom = kzalloc(sizeof(*dom) + sdom->signal_nr *
sizeof(*dom->signal), GFP_KERNEL);
if (!dom)
return -ENOMEM;
if (mask) {
snprintf(dom->name, sizeof(dom->name),
"%s/%02x/%02x", name, i,
(int)(sdom - spec));
} else {
snprintf(dom->name, sizeof(dom->name),
"%s/%02x", name, (int)(sdom - spec));
}
list_add_tail(&dom->head, &ppm->domains);
INIT_LIST_HEAD(&dom->list);
dom->func = sdom->func;
dom->addr = addr;
dom->quad = QUAD_MASK;
dom->signal_nr = sdom->signal_nr;
ssig = (sdom++)->signal;
while (ssig->name) {
dom->signal[ssig->signal].name = ssig->name;
ssig++;
}
addr += size_domain;
}
mask &= ~(1 << i);
}
return 0;
}
int
_nouveau_perfmon_fini(struct nouveau_object *object, bool suspend)
{
struct nouveau_perfmon *ppm = (void *)object;
return nouveau_engine_fini(&ppm->base, suspend);
}
int
_nouveau_perfmon_init(struct nouveau_object *object)
{
struct nouveau_perfmon *ppm = (void *)object;
return nouveau_engine_init(&ppm->base);
}
void
_nouveau_perfmon_dtor(struct nouveau_object *object)
{
struct nouveau_perfmon *ppm = (void *)object;
struct nouveau_perfdom *dom, *tmp;
list_for_each_entry_safe(dom, tmp, &ppm->domains, head) {
list_del(&dom->head);
kfree(dom);
}
nouveau_engine_destroy(&ppm->base);
}
int
nouveau_perfmon_create_(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass,
int length, void **pobject)
{
struct nouveau_perfmon *ppm;
int ret;
ret = nouveau_engine_create_(parent, engine, oclass, true, "PPM",
"perfmon", length, pobject);
ppm = *pobject;
if (ret)
return ret;
INIT_LIST_HEAD(&ppm->domains);
return 0;
}

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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "priv.h"
static void
pwr_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
u32 mask = 0x00000000;
u32 ctrl = 0x00000001;
int i;
for (i = 0; i < ARRAY_SIZE(ctr->signal) && ctr->signal[i]; i++)
mask |= 1 << (ctr->signal[i] - dom->signal);
nv_wr32(ppm, 0x10a504 + (ctr->slot * 0x10), mask);
nv_wr32(ppm, 0x10a50c + (ctr->slot * 0x10), ctrl);
nv_wr32(ppm, 0x10a50c + (ppm->last * 0x10), 0x00000003);
}
static void
pwr_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
ctr->ctr = ppm->pwr[ctr->slot];
ctr->clk = ppm->pwr[ppm->last];
}
static void
pwr_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom)
{
int i;
for (i = 0; i <= ppm->last; i++) {
ppm->pwr[i] = nv_rd32(ppm, 0x10a508 + (i * 0x10));
nv_wr32(ppm, 0x10a508 + (i * 0x10), 0x80000000);
}
}
static const struct nouveau_funcdom
pwr_perfctr_func = {
.init = pwr_perfctr_init,
.read = pwr_perfctr_read,
.next = pwr_perfctr_next,
};
const struct nouveau_specdom
nva3_perfmon_pwr[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x00, "pwr_gr_idle" },
{ 0x04, "pwr_bsp_idle" },
{ 0x05, "pwr_vp_idle" },
{ 0x06, "pwr_ppp_idle" },
{ 0x13, "pwr_ce0_idle" },
{}
}, &pwr_perfctr_func },
{}
};
const struct nouveau_specdom
nvc0_perfmon_pwr[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x00, "pwr_gr_idle" },
{ 0x04, "pwr_bsp_idle" },
{ 0x05, "pwr_vp_idle" },
{ 0x06, "pwr_ppp_idle" },
{ 0x13, "pwr_ce0_idle" },
{ 0x14, "pwr_ce1_idle" },
{}
}, &pwr_perfctr_func },
{}
};
const struct nouveau_specdom
nve0_perfmon_pwr[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{ 0x00, "pwr_gr_idle" },
{ 0x04, "pwr_bsp_idle" },
{ 0x05, "pwr_vp_idle" },
{ 0x06, "pwr_ppp_idle" },
{ 0x13, "pwr_ce0_idle" },
{ 0x14, "pwr_ce1_idle" },
{ 0x15, "pwr_ce2_idle" },
{}
}, &pwr_perfctr_func },
{}
};

143
drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.c Normal file
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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static void
nv40_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
struct nv40_perfmon_priv *priv = (void *)ppm;
struct nv40_perfmon_cntr *cntr = (void *)ctr;
u32 log = ctr->logic_op;
u32 src = 0x00000000;
int i;
for (i = 0; i < 4 && ctr->signal[i]; i++)
src |= (ctr->signal[i] - dom->signal) << (i * 8);
nv_wr32(priv, 0x00a7c0 + dom->addr, 0x00000001);
nv_wr32(priv, 0x00a400 + dom->addr + (cntr->base.slot * 0x40), src);
nv_wr32(priv, 0x00a420 + dom->addr + (cntr->base.slot * 0x40), log);
}
static void
nv40_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
struct nv40_perfmon_priv *priv = (void *)ppm;
struct nv40_perfmon_cntr *cntr = (void *)ctr;
switch (cntr->base.slot) {
case 0: cntr->base.ctr = nv_rd32(priv, 0x00a700 + dom->addr); break;
case 1: cntr->base.ctr = nv_rd32(priv, 0x00a6c0 + dom->addr); break;
case 2: cntr->base.ctr = nv_rd32(priv, 0x00a680 + dom->addr); break;
case 3: cntr->base.ctr = nv_rd32(priv, 0x00a740 + dom->addr); break;
}
cntr->base.clk = nv_rd32(priv, 0x00a600 + dom->addr);
}
static void
nv40_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom)
{
struct nv40_perfmon_priv *priv = (void *)ppm;
if (priv->sequence != ppm->sequence) {
nv_wr32(priv, 0x400084, 0x00000020);
priv->sequence = ppm->sequence;
}
}
const struct nouveau_funcdom
nv40_perfctr_func = {
.init = nv40_perfctr_init,
.read = nv40_perfctr_read,
.next = nv40_perfctr_next,
};
static const struct nouveau_specdom
nv40_perfmon[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
};
int
nv40_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv40_perfmon_oclass *mclass = (void *)oclass;
struct nv40_perfmon_priv *priv;
int ret;
ret = nouveau_perfmon_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
ret = nouveau_perfdom_new(&priv->base, "pm", 0, 0, 0, 4, mclass->doms);
if (ret)
return ret;
nv_engine(priv)->cclass = &nouveau_perfmon_cclass;
nv_engine(priv)->sclass = nouveau_perfmon_sclass;
return 0;
}
struct nouveau_oclass *
nv40_perfmon_oclass = &(struct nv40_perfmon_oclass) {
.base.handle = NV_ENGINE(PERFMON, 0x40),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv40_perfmon_ctor,
.dtor = _nouveau_perfmon_dtor,
.init = _nouveau_perfmon_init,
.fini = _nouveau_perfmon_fini,
},
.doms = nv40_perfmon,
}.base;

26
drivers/gpu/drm/nouveau/core/engine/perfmon/nv40.h Normal file
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#ifndef __NVKM_PM_NV40_H__
#define __NVKM_PM_NV40_H__
#include "priv.h"
struct nv40_perfmon_oclass {
struct nouveau_oclass base;
const struct nouveau_specdom *doms;
};
struct nv40_perfmon_priv {
struct nouveau_perfmon base;
u32 sequence;
};
int nv40_perfmon_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *data, u32 size,
struct nouveau_object **pobject);
struct nv40_perfmon_cntr {
struct nouveau_perfctr base;
};
extern const struct nouveau_funcdom nv40_perfctr_func;
#endif

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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static const struct nouveau_specdom
nv50_perfmon[] = {
{ 0x040, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x100, (const struct nouveau_specsig[]) {
{ 0xc8, "gr_idle" },
{}
}, &nv40_perfctr_func },
{ 0x100, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x020, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x040, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
};
struct nouveau_oclass *
nv50_perfmon_oclass = &(struct nv40_perfmon_oclass) {
.base.handle = NV_ENGINE(PERFMON, 0x50),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv40_perfmon_ctor,
.dtor = _nouveau_perfmon_dtor,
.init = _nouveau_perfmon_init,
.fini = _nouveau_perfmon_fini,
},
.doms = nv50_perfmon,
}.base;

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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static const struct nouveau_specdom
nv84_perfmon[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
};
struct nouveau_oclass *
nv84_perfmon_oclass = &(struct nv40_perfmon_oclass) {
.base.handle = NV_ENGINE(PERFMON, 0x84),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv40_perfmon_ctor,
.dtor = _nouveau_perfmon_dtor,
.init = _nouveau_perfmon_init,
.fini = _nouveau_perfmon_fini,
},
.doms = nv84_perfmon,
}.base;

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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nv40.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static const struct nouveau_specdom
nva3_perfmon[] = {
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{ 0x20, (const struct nouveau_specsig[]) {
{}
}, &nv40_perfctr_func },
{}
};
static int
nva3_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **object)
{
int ret = nv40_perfmon_ctor(parent, engine, oclass, data, size, object);
if (ret == 0) {
struct nv40_perfmon_priv *priv = (void *)*object;
ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
nva3_perfmon_pwr);
if (ret)
return ret;
priv->base.last = 3;
}
return ret;
}
struct nouveau_oclass *
nva3_perfmon_oclass = &(struct nv40_perfmon_oclass) {
.base.handle = NV_ENGINE(PERFMON, 0xa3),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nva3_perfmon_ctor,
.dtor = _nouveau_perfmon_dtor,
.init = _nouveau_perfmon_init,
.fini = _nouveau_perfmon_fini,
},
.doms = nva3_perfmon,
}.base;

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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nvc0.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static const struct nouveau_specdom
nvc0_perfmon_hub[] = {
{}
};
static const struct nouveau_specdom
nvc0_perfmon_gpc[] = {
{}
};
static const struct nouveau_specdom
nvc0_perfmon_part[] = {
{}
};
static void
nvc0_perfctr_init(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
struct nvc0_perfmon_priv *priv = (void *)ppm;
struct nvc0_perfmon_cntr *cntr = (void *)ctr;
u32 log = ctr->logic_op;
u32 src = 0x00000000;
int i;
for (i = 0; i < 4 && ctr->signal[i]; i++)
src |= (ctr->signal[i] - dom->signal) << (i * 8);
nv_wr32(priv, dom->addr + 0x09c, 0x00040002);
nv_wr32(priv, dom->addr + 0x100, 0x00000000);
nv_wr32(priv, dom->addr + 0x040 + (cntr->base.slot * 0x08), src);
nv_wr32(priv, dom->addr + 0x044 + (cntr->base.slot * 0x08), log);
}
static void
nvc0_perfctr_read(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom,
struct nouveau_perfctr *ctr)
{
struct nvc0_perfmon_priv *priv = (void *)ppm;
struct nvc0_perfmon_cntr *cntr = (void *)ctr;
switch (cntr->base.slot) {
case 0: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x08c); break;
case 1: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x088); break;
case 2: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x080); break;
case 3: cntr->base.ctr = nv_rd32(priv, dom->addr + 0x090); break;
}
cntr->base.clk = nv_rd32(priv, dom->addr + 0x070);
}
static void
nvc0_perfctr_next(struct nouveau_perfmon *ppm, struct nouveau_perfdom *dom)
{
struct nvc0_perfmon_priv *priv = (void *)ppm;
nv_wr32(priv, dom->addr + 0x06c, dom->signal_nr - 0x40 + 0x27);
nv_wr32(priv, dom->addr + 0x0ec, 0x00000011);
}
const struct nouveau_funcdom
nvc0_perfctr_func = {
.init = nvc0_perfctr_init,
.read = nvc0_perfctr_read,
.next = nvc0_perfctr_next,
};
int
nvc0_perfmon_fini(struct nouveau_object *object, bool suspend)
{
struct nvc0_perfmon_priv *priv = (void *)object;
nv_mask(priv, 0x000200, 0x10000000, 0x00000000);
nv_mask(priv, 0x000200, 0x10000000, 0x10000000);
return nouveau_perfmon_fini(&priv->base, suspend);
}
static int
nvc0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nvc0_perfmon_priv *priv;
u32 mask;
int ret;
ret = nouveau_perfmon_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
nvc0_perfmon_pwr);
if (ret)
return ret;
/* HUB */
ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
nvc0_perfmon_hub);
if (ret)
return ret;
/* GPC */
mask = (1 << nv_rd32(priv, 0x022430)) - 1;
mask &= ~nv_rd32(priv, 0x022504);
mask &= ~nv_rd32(priv, 0x022584);
ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000,
0x1000, 0x200, nvc0_perfmon_gpc);
if (ret)
return ret;
/* PART */
mask = (1 << nv_rd32(priv, 0x022438)) - 1;
mask &= ~nv_rd32(priv, 0x022548);
mask &= ~nv_rd32(priv, 0x0225c8);
ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000,
0x1000, 0x200, nvc0_perfmon_part);
if (ret)
return ret;
nv_engine(priv)->cclass = &nouveau_perfmon_cclass;
nv_engine(priv)->sclass = nouveau_perfmon_sclass;
priv->base.last = 7;
return 0;
}
struct nouveau_oclass
nvc0_perfmon_oclass = {
.handle = NV_ENGINE(PERFMON, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_perfmon_ctor,
.dtor = _nouveau_perfmon_dtor,
.init = _nouveau_perfmon_init,
.fini = nvc0_perfmon_fini,
},
};

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#ifndef __NVKM_PM_NVC0_H__
#define __NVKM_PM_NVC0_H__
#include "priv.h"
struct nvc0_perfmon_priv {
struct nouveau_perfmon base;
};
struct nvc0_perfmon_cntr {
struct nouveau_perfctr base;
};
extern const struct nouveau_funcdom nvc0_perfctr_func;
int nvc0_perfmon_fini(struct nouveau_object *, bool);
#endif

162
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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nvc0.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static const struct nouveau_specdom
nve0_perfmon_hub[] = {
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "hub00_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x40, (const struct nouveau_specsig[]) {
{ 0x27, "hub01_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "hub02_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "hub03_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x40, (const struct nouveau_specsig[]) {
{ 0x03, "host_mmio_rd" },
{ 0x27, "hub04_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "hub05_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0xc0, (const struct nouveau_specsig[]) {
{ 0x74, "host_fb_rd3x" },
{ 0x75, "host_fb_rd3x_2" },
{ 0xa7, "hub06_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "hub07_user_0" },
{}
}, &nvc0_perfctr_func },
{}
};
static const struct nouveau_specdom
nve0_perfmon_gpc[] = {
{ 0xe0, (const struct nouveau_specsig[]) {
{ 0xc7, "gpc00_user_0" },
{}
}, &nvc0_perfctr_func },
{}
};
static const struct nouveau_specdom
nve0_perfmon_part[] = {
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "part00_user_0" },
{}
}, &nvc0_perfctr_func },
{ 0x60, (const struct nouveau_specsig[]) {
{ 0x47, "part01_user_0" },
{}
}, &nvc0_perfctr_func },
{}
};
static int
nve0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nvc0_perfmon_priv *priv;
u32 mask;
int ret;
ret = nouveau_perfmon_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
/* PDAEMON */
ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
nve0_perfmon_pwr);
if (ret)
return ret;
/* HUB */
ret = nouveau_perfdom_new(&priv->base, "hub", 0, 0x1b0000, 0, 0x200,
nve0_perfmon_hub);
if (ret)
return ret;
/* GPC */
mask = (1 << nv_rd32(priv, 0x022430)) - 1;
mask &= ~nv_rd32(priv, 0x022504);
mask &= ~nv_rd32(priv, 0x022584);
ret = nouveau_perfdom_new(&priv->base, "gpc", mask, 0x180000,
0x1000, 0x200, nve0_perfmon_gpc);
if (ret)
return ret;
/* PART */
mask = (1 << nv_rd32(priv, 0x022438)) - 1;
mask &= ~nv_rd32(priv, 0x022548);
mask &= ~nv_rd32(priv, 0x0225c8);
ret = nouveau_perfdom_new(&priv->base, "part", mask, 0x1a0000,
0x1000, 0x200, nve0_perfmon_part);
if (ret)
return ret;
nv_engine(priv)->cclass = &nouveau_perfmon_cclass;
nv_engine(priv)->sclass = nouveau_perfmon_sclass;
priv->base.last = 7;
return 0;
}
struct nouveau_oclass
nve0_perfmon_oclass = {
.handle = NV_ENGINE(PERFMON, 0xe0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nve0_perfmon_ctor,
.dtor = _nouveau_perfmon_dtor,
.init = _nouveau_perfmon_init,
.fini = nvc0_perfmon_fini,
},
};

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/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include "nvc0.h"
/*******************************************************************************
* Perfmon object classes
******************************************************************************/
/*******************************************************************************
* PPM context
******************************************************************************/
/*******************************************************************************
* PPM engine/subdev functions
******************************************************************************/
static int
nvf0_perfmon_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nvc0_perfmon_priv *priv;
int ret;
ret = nouveau_perfmon_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
ret = nouveau_perfdom_new(&priv->base, "pwr", 0, 0, 0, 0,
nve0_perfmon_pwr);
if (ret)
return ret;
nv_engine(priv)->cclass = &nouveau_perfmon_cclass;
nv_engine(priv)->sclass = nouveau_perfmon_sclass;
return 0;
}
struct nouveau_oclass
nvf0_perfmon_oclass = {
.handle = NV_ENGINE(PERFMON, 0xf0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvf0_perfmon_ctor,
.dtor = _nouveau_perfmon_dtor,
.init = _nouveau_perfmon_init,
.fini = nvc0_perfmon_fini,
},
};

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#ifndef __NVKM_PERFMON_PRIV_H__
#define __NVKM_PERFMON_PRIV_H__
#include <engine/perfmon.h>
struct nouveau_perfctr {
struct nouveau_object base;
struct list_head head;
struct nouveau_perfsig *signal[4];
int slot;
u32 logic_op;
u32 clk;
u32 ctr;
};
extern struct nouveau_oclass nouveau_perfmon_sclass[];
struct nouveau_perfctx {
struct nouveau_engctx base;
};
extern struct nouveau_oclass nouveau_perfmon_cclass;
struct nouveau_specsig {
u8 signal;
const char *name;
};
struct nouveau_perfsig {
const char *name;
};
struct nouveau_perfdom;
struct nouveau_perfctr *
nouveau_perfsig_wrap(struct nouveau_perfmon *, const char *,
struct nouveau_perfdom **);
struct nouveau_specdom {
u16 signal_nr;
const struct nouveau_specsig *signal;
const struct nouveau_funcdom *func;
};
extern const struct nouveau_specdom nva3_perfmon_pwr[];
extern const struct nouveau_specdom nvc0_perfmon_pwr[];
extern const struct nouveau_specdom nve0_perfmon_pwr[];
struct nouveau_perfdom {
struct list_head head;
struct list_head list;
const struct nouveau_funcdom *func;
char name[32];
u32 addr;
u8 quad;
u32 signal_nr;
struct nouveau_perfsig signal[];
};
struct nouveau_funcdom {
void (*init)(struct nouveau_perfmon *, struct nouveau_perfdom *,
struct nouveau_perfctr *);
void (*read)(struct nouveau_perfmon *, struct nouveau_perfdom *,
struct nouveau_perfctr *);
void (*next)(struct nouveau_perfmon *, struct nouveau_perfdom *);
};
int nouveau_perfdom_new(struct nouveau_perfmon *, const char *, u32,
u32, u32, u32, const struct nouveau_specdom *);
#define nouveau_perfmon_create(p,e,o,d) \
nouveau_perfmon_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nouveau_perfmon_dtor(p) ({ \
struct nouveau_perfmon *c = (p); \
_nouveau_perfmon_dtor(nv_object(c)); \
})
#define nouveau_perfmon_init(p) ({ \
struct nouveau_perfmon *c = (p); \
_nouveau_perfmon_init(nv_object(c)); \
})
#define nouveau_perfmon_fini(p,s) ({ \
struct nouveau_perfmon *c = (p); \
_nouveau_perfmon_fini(nv_object(c), (s)); \
})
int nouveau_perfmon_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, int, void **);
void _nouveau_perfmon_dtor(struct nouveau_object *);
int _nouveau_perfmon_init(struct nouveau_object *);
int _nouveau_perfmon_fini(struct nouveau_object *, bool);
#endif

4
drivers/gpu/drm/nouveau/core/engine/software/nv04.c
View File

@ -135,8 +135,8 @@ nv04_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
struct nouveau_oclass
nv04_software_oclass = {
struct nouveau_oclass *
nv04_software_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(SW, 0x04),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_software_ctor,

4
drivers/gpu/drm/nouveau/core/engine/software/nv10.c
View File

@ -117,8 +117,8 @@ nv10_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
return 0;
}
struct nouveau_oclass
nv10_software_oclass = {
struct nouveau_oclass *
nv10_software_oclass = &(struct nouveau_oclass) {
.handle = NV_ENGINE(SW, 0x10),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv10_software_ctor,

96
drivers/gpu/drm/nouveau/core/engine/software/nv50.c
View File

@ -32,16 +32,9 @@
#include <subdev/bar.h>
#include <engine/software.h>
#include <engine/disp.h>
struct nv50_software_priv {
struct nouveau_software base;
};
struct nv50_software_chan {
struct nouveau_software_chan base;
};
#include "nv50.h"
/*******************************************************************************
* software object classes
@ -62,7 +55,7 @@ nv50_software_mthd_dma_vblsem(struct nouveau_object *object, u32 mthd,
if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) {
struct nouveau_gpuobj *gpuobj = nv_gpuobj(handle->object);
chan->base.vblank.ctxdma = gpuobj->node->offset >> 4;
chan->vblank.ctxdma = gpuobj->node->offset >> 4;
ret = 0;
}
nouveau_namedb_put(handle);
@ -74,34 +67,33 @@ nv50_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
chan->base.vblank.offset = *(u32 *)args;
chan->vblank.offset = *(u32 *)args;
return 0;
}
static int
int
nv50_software_mthd_vblsem_value(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
chan->base.vblank.value = *(u32 *)args;
chan->vblank.value = *(u32 *)args;
return 0;
}
static int
int
nv50_software_mthd_vblsem_release(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
struct nouveau_disp *disp = nouveau_disp(object);
u32 crtc = *(u32 *)args;
if (crtc > 1)
u32 head = *(u32 *)args;
if (head >= chan->vblank.nr_event)
return -EINVAL;
nouveau_event_get(disp->vblank, crtc, &chan->base.vblank.event);
nouveau_event_get(chan->vblank.event[head]);
return 0;
}
static int
int
nv50_software_mthd_flip(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
@ -132,10 +124,9 @@ nv50_software_sclass[] = {
******************************************************************************/
static int
nv50_software_vblsem_release(struct nouveau_eventh *event, int head)
nv50_software_vblsem_release(void *data, int head)
{
struct nouveau_software_chan *chan =
container_of(event, struct nouveau_software_chan, vblank.event);
struct nv50_software_chan *chan = data;
struct nv50_software_priv *priv = (void *)nv_object(chan)->engine;
struct nouveau_bar *bar = nouveau_bar(priv);
@ -154,45 +145,76 @@ nv50_software_vblsem_release(struct nouveau_eventh *event, int head)
return NVKM_EVENT_DROP;
}
static int
void
nv50_software_context_dtor(struct nouveau_object *object)
{
struct nv50_software_chan *chan = (void *)object;
int i;
if (chan->vblank.event) {
for (i = 0; i < chan->vblank.nr_event; i++)
nouveau_event_ref(NULL, &chan->vblank.event[i]);
kfree(chan->vblank.event);
}
nouveau_software_context_destroy(&chan->base);
}
int
nv50_software_context_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nouveau_disp *pdisp = nouveau_disp(parent);
struct nv50_software_cclass *pclass = (void *)oclass;
struct nv50_software_chan *chan;
int ret;
int ret, i;
ret = nouveau_software_context_create(parent, engine, oclass, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
chan->base.vblank.channel = nv_gpuobj(parent->parent)->addr >> 12;
chan->base.vblank.event.func = nv50_software_vblsem_release;
chan->vblank.nr_event = pdisp->vblank->index_nr;
chan->vblank.event = kzalloc(chan->vblank.nr_event *
sizeof(*chan->vblank.event), GFP_KERNEL);
if (!chan->vblank.event)
return -ENOMEM;
for (i = 0; i < chan->vblank.nr_event; i++) {
ret = nouveau_event_new(pdisp->vblank, i, pclass->vblank,
chan, &chan->vblank.event[i]);
if (ret)
return ret;
}
chan->vblank.channel = nv_gpuobj(parent->parent)->addr >> 12;
return 0;
}
static struct nouveau_oclass
static struct nv50_software_cclass
nv50_software_cclass = {
.handle = NV_ENGCTX(SW, 0x50),
.ofuncs = &(struct nouveau_ofuncs) {
.base.handle = NV_ENGCTX(SW, 0x50),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_software_context_ctor,
.dtor = _nouveau_software_context_dtor,
.init = _nouveau_software_context_init,
.fini = _nouveau_software_context_fini,
},
.vblank = nv50_software_vblsem_release,
};
/*******************************************************************************
* software engine/subdev functions
******************************************************************************/
static int
int
nv50_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv50_software_oclass *pclass = (void *)oclass;
struct nv50_software_priv *priv;
int ret;
@ -201,19 +223,21 @@ nv50_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
if (ret)
return ret;
nv_engine(priv)->cclass = &nv50_software_cclass;
nv_engine(priv)->sclass = nv50_software_sclass;
nv_engine(priv)->cclass = pclass->cclass;
nv_engine(priv)->sclass = pclass->sclass;
nv_subdev(priv)->intr = nv04_software_intr;
return 0;
}
struct nouveau_oclass
nv50_software_oclass = {
.handle = NV_ENGINE(SW, 0x50),
.ofuncs = &(struct nouveau_ofuncs) {
struct nouveau_oclass *
nv50_software_oclass = &(struct nv50_software_oclass) {
.base.handle = NV_ENGINE(SW, 0x50),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_software_ctor,
.dtor = _nouveau_software_dtor,
.init = _nouveau_software_init,
.fini = _nouveau_software_fini,
},
};
.cclass = &nv50_software_cclass.base,
.sclass = nv50_software_sclass,
}.base;

47
drivers/gpu/drm/nouveau/core/engine/software/nv50.h Normal file
View File

@ -0,0 +1,47 @@
#ifndef __NVKM_SW_NV50_H__
#define __NVKM_SW_NV50_H__
#include <engine/software.h>
struct nv50_software_oclass {
struct nouveau_oclass base;
struct nouveau_oclass *cclass;
struct nouveau_oclass *sclass;
};
struct nv50_software_priv {
struct nouveau_software base;
};
int nv50_software_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
struct nv50_software_cclass {
struct nouveau_oclass base;
int (*vblank)(void *, int);
};
struct nv50_software_chan {
struct nouveau_software_chan base;
struct {
struct nouveau_eventh **event;
int nr_event;
u32 channel;
u32 ctxdma;
u64 offset;
u32 value;
} vblank;
};
int nv50_software_context_ctor(struct nouveau_object *,
struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
void nv50_software_context_dtor(struct nouveau_object *);
int nv50_software_mthd_vblsem_value(struct nouveau_object *, u32, void *, u32);
int nv50_software_mthd_vblsem_release(struct nouveau_object *, u32, void *, u32);
int nv50_software_mthd_flip(struct nouveau_object *, u32, void *, u32);
#endif

130
drivers/gpu/drm/nouveau/core/engine/software/nvc0.c
View File

@ -32,13 +32,7 @@
#include <engine/software.h>
#include <engine/disp.h>
struct nvc0_software_priv {
struct nouveau_software base;
};
struct nvc0_software_chan {
struct nouveau_software_chan base;
};
#include "nv50.h"
/*******************************************************************************
* software object classes
@ -48,58 +42,24 @@ static int
nvc0_software_mthd_vblsem_offset(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
struct nvc0_software_chan *chan = (void *)nv_engctx(object->parent);
struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
u64 data = *(u32 *)args;
if (mthd == 0x0400) {
chan->base.vblank.offset &= 0x00ffffffffULL;
chan->base.vblank.offset |= data << 32;
chan->vblank.offset &= 0x00ffffffffULL;
chan->vblank.offset |= data << 32;
} else {
chan->base.vblank.offset &= 0xff00000000ULL;
chan->base.vblank.offset |= data;
chan->vblank.offset &= 0xff00000000ULL;
chan->vblank.offset |= data;
}
return 0;
}
static int
nvc0_software_mthd_vblsem_value(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
struct nvc0_software_chan *chan = (void *)nv_engctx(object->parent);
chan->base.vblank.value = *(u32 *)args;
return 0;
}
static int
nvc0_software_mthd_vblsem_release(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
struct nvc0_software_chan *chan = (void *)nv_engctx(object->parent);
struct nouveau_disp *disp = nouveau_disp(object);
u32 crtc = *(u32 *)args;
if ((nv_device(object)->card_type < NV_E0 && crtc > 1) || crtc > 3)
return -EINVAL;
nouveau_event_get(disp->vblank, crtc, &chan->base.vblank.event);
return 0;
}
static int
nvc0_software_mthd_flip(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
struct nvc0_software_chan *chan = (void *)nv_engctx(object->parent);
if (chan->base.flip)
return chan->base.flip(chan->base.flip_data);
return -EINVAL;
}
static int
nvc0_software_mthd_mp_control(struct nouveau_object *object, u32 mthd,
void *args, u32 size)
{
struct nvc0_software_chan *chan = (void *)nv_engctx(object->parent);
struct nvc0_software_priv *priv = (void *)nv_object(chan)->engine;
struct nv50_software_chan *chan = (void *)nv_engctx(object->parent);
struct nv50_software_priv *priv = (void *)nv_object(chan)->engine;
u32 data = *(u32 *)args;
switch (mthd) {
@ -124,9 +84,9 @@ static struct nouveau_omthds
nvc0_software_omthds[] = {
{ 0x0400, 0x0400, nvc0_software_mthd_vblsem_offset },
{ 0x0404, 0x0404, nvc0_software_mthd_vblsem_offset },
{ 0x0408, 0x0408, nvc0_software_mthd_vblsem_value },
{ 0x040c, 0x040c, nvc0_software_mthd_vblsem_release },
{ 0x0500, 0x0500, nvc0_software_mthd_flip },
{ 0x0408, 0x0408, nv50_software_mthd_vblsem_value },
{ 0x040c, 0x040c, nv50_software_mthd_vblsem_release },
{ 0x0500, 0x0500, nv50_software_mthd_flip },
{ 0x0600, 0x0600, nvc0_software_mthd_mp_control },
{ 0x0644, 0x0644, nvc0_software_mthd_mp_control },
{ 0x06ac, 0x06ac, nvc0_software_mthd_mp_control },
@ -144,11 +104,10 @@ nvc0_software_sclass[] = {
******************************************************************************/
static int
nvc0_software_vblsem_release(struct nouveau_eventh *event, int head)
nvc0_software_vblsem_release(void *data, int head)
{
struct nouveau_software_chan *chan =
container_of(event, struct nouveau_software_chan, vblank.event);
struct nvc0_software_priv *priv = (void *)nv_object(chan)->engine;
struct nv50_software_chan *chan = data;
struct nv50_software_priv *priv = (void *)nv_object(chan)->engine;
struct nouveau_bar *bar = nouveau_bar(priv);
nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
@ -160,66 +119,31 @@ nvc0_software_vblsem_release(struct nouveau_eventh *event, int head)
return NVKM_EVENT_DROP;
}
static int
nvc0_software_context_ctor(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nvc0_software_chan *chan;
int ret;
ret = nouveau_software_context_create(parent, engine, oclass, &chan);
*pobject = nv_object(chan);
if (ret)
return ret;
chan->base.vblank.channel = nv_gpuobj(parent->parent)->addr >> 12;
chan->base.vblank.event.func = nvc0_software_vblsem_release;
return 0;
}
static struct nouveau_oclass
static struct nv50_software_cclass
nvc0_software_cclass = {
.handle = NV_ENGCTX(SW, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_software_context_ctor,
.base.handle = NV_ENGCTX(SW, 0xc0),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_software_context_ctor,
.dtor = _nouveau_software_context_dtor,
.init = _nouveau_software_context_init,
.fini = _nouveau_software_context_fini,
},
.vblank = nvc0_software_vblsem_release,
};
/*******************************************************************************
* software engine/subdev functions
******************************************************************************/
static int
nvc0_software_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nvc0_software_priv *priv;
int ret;
ret = nouveau_software_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_engine(priv)->cclass = &nvc0_software_cclass;
nv_engine(priv)->sclass = nvc0_software_sclass;
nv_subdev(priv)->intr = nv04_software_intr;
return 0;
}
struct nouveau_oclass
nvc0_software_oclass = {
.handle = NV_ENGINE(SW, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_software_ctor,
struct nouveau_oclass *
nvc0_software_oclass = &(struct nv50_software_oclass) {
.base.handle = NV_ENGINE(SW, 0xc0),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_software_ctor,
.dtor = _nouveau_software_dtor,
.init = _nouveau_software_init,
.fini = _nouveau_software_fini,
},
};
.cclass = &nvc0_software_cclass.base,
.sclass = nvc0_software_sclass,
}.base;

73
drivers/gpu/drm/nouveau/core/include/core/class.h
View File

@ -22,7 +22,7 @@
#define NV_DEVICE_DISABLE_PPP 0x0000004000000000ULL
#define NV_DEVICE_DISABLE_COPY0 0x0000008000000000ULL
#define NV_DEVICE_DISABLE_COPY1 0x0000010000000000ULL
#define NV_DEVICE_DISABLE_UNK1C1 0x0000020000000000ULL
#define NV_DEVICE_DISABLE_VIC 0x0000020000000000ULL
#define NV_DEVICE_DISABLE_VENC 0x0000040000000000ULL
struct nv_device_class {
@ -98,6 +98,77 @@ struct nv_dma_class {
u32 conf0;
};
/* Perfmon counter class
*
* XXXX: NV_PERFCTR
*/
#define NV_PERFCTR_CLASS 0x0000ffff
#define NV_PERFCTR_QUERY 0x00000000
#define NV_PERFCTR_SAMPLE 0x00000001
#define NV_PERFCTR_READ 0x00000002
struct nv_perfctr_class {
u16 logic_op;
struct {
char __user *name; /*XXX: use cfu when exposed to userspace */
u32 size;
} signal[4];
};
struct nv_perfctr_query {
u32 iter;
u32 size;
char __user *name; /*XXX: use ctu when exposed to userspace */
};
struct nv_perfctr_sample {
};
struct nv_perfctr_read {
u32 ctr;
u32 clk;
};
/* Device control class
*
* XXXX: NV_CONTROL
*/
#define NV_CONTROL_CLASS 0x0000fffe
#define NV_CONTROL_PSTATE_INFO 0x00000000
#define NV_CONTROL_PSTATE_INFO_USTATE_DISABLE (-1)
#define NV_CONTROL_PSTATE_INFO_USTATE_PERFMON (-2)
#define NV_CONTROL_PSTATE_INFO_PSTATE_UNKNOWN (-1)
#define NV_CONTROL_PSTATE_INFO_PSTATE_PERFMON (-2)
#define NV_CONTROL_PSTATE_ATTR 0x00000001
#define NV_CONTROL_PSTATE_ATTR_STATE_CURRENT (-1)
#define NV_CONTROL_PSTATE_USER 0x00000002
#define NV_CONTROL_PSTATE_USER_STATE_UNKNOWN (-1)
#define NV_CONTROL_PSTATE_USER_STATE_PERFMON (-2)
struct nv_control_pstate_info {
u32 count; /* out: number of power states */
s32 ustate; /* out: current target pstate index */
u32 pstate; /* out: current pstate index */
};
struct nv_control_pstate_attr {
s32 state; /* in: index of pstate to query
* out: pstate identifier
*/
u32 index; /* in: index of attribute to query
* out: index of next attribute, or 0 if no more
*/
char name[32];
char unit[16];
u32 min;
u32 max;
};
struct nv_control_pstate_user {
s32 state; /* in: pstate identifier */
};
/* DMA FIFO channel classes
*
* 006b: NV03_CHANNEL_DMA

9
drivers/gpu/drm/nouveau/core/include/core/debug.h
View File

@ -1,13 +1,20 @@
#ifndef __NOUVEAU_DEBUG_H__
#define __NOUVEAU_DEBUG_H__
extern int nv_info_debug_level;
#define NV_DBG_FATAL 0
#define NV_DBG_ERROR 1
#define NV_DBG_WARN 2
#define NV_DBG_INFO 3
#define NV_DBG_INFO nv_info_debug_level
#define NV_DBG_DEBUG 4
#define NV_DBG_TRACE 5
#define NV_DBG_PARANOIA 6
#define NV_DBG_SPAM 7
#define NV_DBG_INFO_NORMAL 3
#define NV_DBG_INFO_SILENT NV_DBG_DEBUG
#define nv_debug_level(a) nv_info_debug_level = NV_DBG_INFO_##a
#endif

7
drivers/gpu/drm/nouveau/core/include/core/device.h
View File

@ -33,9 +33,10 @@ enum nv_subdev_type {
NVDEV_SUBDEV_INSTMEM,
NVDEV_SUBDEV_VM,
NVDEV_SUBDEV_BAR,
NVDEV_SUBDEV_PWR,
NVDEV_SUBDEV_VOLT,
NVDEV_SUBDEV_CLOCK,
NVDEV_SUBDEV_THERM,
NVDEV_SUBDEV_CLOCK,
NVDEV_ENGINE_DMAOBJ,
NVDEV_ENGINE_FIFO,
@ -50,9 +51,10 @@ enum nv_subdev_type {
NVDEV_ENGINE_COPY0,
NVDEV_ENGINE_COPY1,
NVDEV_ENGINE_COPY2,
NVDEV_ENGINE_UNK1C1,
NVDEV_ENGINE_VIC,
NVDEV_ENGINE_VENC,
NVDEV_ENGINE_DISP,
NVDEV_ENGINE_PERFMON,
NVDEV_SUBDEV_NR,
};
@ -72,6 +74,7 @@ struct nouveau_device {
enum {
NV_04 = 0x04,
NV_10 = 0x10,
NV_11 = 0x11,
NV_20 = 0x20,
NV_30 = 0x30,
NV_40 = 0x40,

22
drivers/gpu/drm/nouveau/core/include/core/event.h
View File

@ -5,13 +5,21 @@
#define NVKM_EVENT_DROP 0
#define NVKM_EVENT_KEEP 1
/* nouveau_eventh.flags bit #s */
#define NVKM_EVENT_ENABLE 0
struct nouveau_eventh {
struct nouveau_event *event;
struct list_head head;
int (*func)(struct nouveau_eventh *, int index);
unsigned long flags;
int index;
int (*func)(void *, int);
void *priv;
};
struct nouveau_event {
spinlock_t lock;
spinlock_t list_lock;
spinlock_t refs_lock;
void *priv;
void (*enable)(struct nouveau_event *, int index);
@ -28,9 +36,11 @@ int nouveau_event_create(int index_nr, struct nouveau_event **);
void nouveau_event_destroy(struct nouveau_event **);
void nouveau_event_trigger(struct nouveau_event *, int index);
void nouveau_event_get(struct nouveau_event *, int index,
struct nouveau_eventh *);
void nouveau_event_put(struct nouveau_event *, int index,
struct nouveau_eventh *);
int nouveau_event_new(struct nouveau_event *, int index,
int (*func)(void *, int), void *,
struct nouveau_eventh **);
void nouveau_event_ref(struct nouveau_eventh *, struct nouveau_eventh **);
void nouveau_event_get(struct nouveau_eventh *);
void nouveau_event_put(struct nouveau_eventh *);
#endif

9
drivers/gpu/drm/nouveau/core/include/core/option.h
View File

@ -8,4 +8,13 @@ bool nouveau_boolopt(const char *optstr, const char *opt, bool value);
int nouveau_dbgopt(const char *optstr, const char *sub);
/* compares unterminated string 'str' with zero-terminated string 'cmp' */
static inline int
strncasecmpz(const char *str, const char *cmp, size_t len)
{
if (strlen(cmp) != len)
return len;
return strncasecmp(str, cmp, len);
}
#endif

30
drivers/gpu/drm/nouveau/core/include/core/printk.h
View File

@ -6,27 +6,12 @@
struct nouveau_object;
#define NV_PRINTK_FATAL KERN_CRIT
#define NV_PRINTK_ERROR KERN_ERR
#define NV_PRINTK_WARN KERN_WARNING
#define NV_PRINTK_INFO KERN_INFO
#define NV_PRINTK_DEBUG KERN_DEBUG
#define NV_PRINTK_PARANOIA KERN_DEBUG
#define NV_PRINTK_TRACE KERN_DEBUG
#define NV_PRINTK_SPAM KERN_DEBUG
extern int nv_printk_suspend_level;
#define NV_DBG_SUSPEND (nv_printk_suspend_level)
#define NV_PRINTK_SUSPEND (nv_printk_level_to_pfx(nv_printk_suspend_level))
const char *nv_printk_level_to_pfx(int level);
void __printf(4, 5)
nv_printk_(struct nouveau_object *, const char *, int, const char *, ...);
void __printf(3, 4)
nv_printk_(struct nouveau_object *, int, const char *, ...);
#define nv_printk(o,l,f,a...) do { \
if (NV_DBG_##l <= CONFIG_NOUVEAU_DEBUG) \
nv_printk_(nv_object(o), NV_PRINTK_##l, NV_DBG_##l, f, ##a); \
nv_printk_(nv_object(o), NV_DBG_##l, f, ##a); \
} while(0)
#define nv_fatal(o,f,a...) nv_printk((o), FATAL, f, ##a)
@ -37,16 +22,9 @@ nv_printk_(struct nouveau_object *, const char *, int, const char *, ...);
#define nv_trace(o,f,a...) nv_printk((o), TRACE, f, ##a)
#define nv_spam(o,f,a...) nv_printk((o), SPAM, f, ##a)
#define nv_suspend(o,f,a...) nv_printk((o), SUSPEND, f, ##a)
static inline void nv_suspend_set_printk_level(int level)
{
nv_printk_suspend_level = level;
}
#define nv_assert(f,a...) do { \
if (NV_DBG_FATAL <= CONFIG_NOUVEAU_DEBUG) \
nv_printk_(NULL, NV_PRINTK_FATAL, NV_DBG_FATAL, f "\n", ##a); \
nv_printk_(NULL, NV_DBG_FATAL, f "\n", ##a); \
BUG_ON(1); \
} while(0)

16
drivers/gpu/drm/nouveau/core/include/engine/fifo.h
View File

@ -101,14 +101,14 @@ nouveau_client_name_for_fifo_chid(struct nouveau_fifo *fifo, u32 chid);
#define _nouveau_fifo_init _nouveau_engine_init
#define _nouveau_fifo_fini _nouveau_engine_fini
extern struct nouveau_oclass nv04_fifo_oclass;
extern struct nouveau_oclass nv10_fifo_oclass;
extern struct nouveau_oclass nv17_fifo_oclass;
extern struct nouveau_oclass nv40_fifo_oclass;
extern struct nouveau_oclass nv50_fifo_oclass;
extern struct nouveau_oclass nv84_fifo_oclass;
extern struct nouveau_oclass nvc0_fifo_oclass;
extern struct nouveau_oclass nve0_fifo_oclass;
extern struct nouveau_oclass *nv04_fifo_oclass;
extern struct nouveau_oclass *nv10_fifo_oclass;
extern struct nouveau_oclass *nv17_fifo_oclass;
extern struct nouveau_oclass *nv40_fifo_oclass;
extern struct nouveau_oclass *nv50_fifo_oclass;
extern struct nouveau_oclass *nv84_fifo_oclass;
extern struct nouveau_oclass *nvc0_fifo_oclass;
extern struct nouveau_oclass *nve0_fifo_oclass;
void nv04_fifo_intr(struct nouveau_subdev *);
int nv04_fifo_context_attach(struct nouveau_object *, struct nouveau_object *);

5
drivers/gpu/drm/nouveau/core/include/engine/mpeg.h
View File

@ -42,10 +42,13 @@ struct nouveau_mpeg {
extern struct nouveau_oclass nv31_mpeg_oclass;
extern struct nouveau_oclass nv40_mpeg_oclass;
extern struct nouveau_oclass nv44_mpeg_oclass;
extern struct nouveau_oclass nv50_mpeg_oclass;
extern struct nouveau_oclass nv84_mpeg_oclass;
extern struct nouveau_ofuncs nv31_mpeg_ofuncs;
extern struct nouveau_oclass nv31_mpeg_cclass;
extern struct nouveau_oclass nv31_mpeg_sclass[];
extern struct nouveau_oclass nv40_mpeg_sclass[];
void nv31_mpeg_intr(struct nouveau_subdev *);
void nv31_mpeg_tile_prog(struct nouveau_engine *, int);
int nv31_mpeg_init(struct nouveau_object *);

39
drivers/gpu/drm/nouveau/core/include/engine/perfmon.h Normal file
View File

@ -0,0 +1,39 @@
#ifndef __NVKM_PERFMON_H__
#define __NVKM_PERFMON_H__
#include <core/device.h>
#include <core/engine.h>
#include <core/engctx.h>
#include <core/class.h>
struct nouveau_perfdom;
struct nouveau_perfctr;
struct nouveau_perfmon {
struct nouveau_engine base;
struct nouveau_perfctx *context;
void *profile_data;
struct list_head domains;
u32 sequence;
/*XXX: temp for daemon backend */
u32 pwr[8];
u32 last;
};
static inline struct nouveau_perfmon *
nouveau_perfmon(void *obj)
{
return (void *)nv_device(obj)->subdev[NVDEV_ENGINE_PERFMON];
}
extern struct nouveau_oclass *nv40_perfmon_oclass;
extern struct nouveau_oclass *nv50_perfmon_oclass;
extern struct nouveau_oclass *nv84_perfmon_oclass;
extern struct nouveau_oclass *nva3_perfmon_oclass;
extern struct nouveau_oclass nvc0_perfmon_oclass;
extern struct nouveau_oclass nve0_perfmon_oclass;
extern struct nouveau_oclass nvf0_perfmon_oclass;
#endif

17
drivers/gpu/drm/nouveau/core/include/engine/software.h
View File

@ -3,19 +3,10 @@
#include <core/engine.h>
#include <core/engctx.h>
#include <core/event.h>
struct nouveau_software_chan {
struct nouveau_engctx base;
struct {
struct nouveau_eventh event;
u32 channel;
u32 ctxdma;
u64 offset;
u32 value;
} vblank;
int (*flip)(void *);
void *flip_data;
};
@ -50,10 +41,10 @@ struct nouveau_software {
#define _nouveau_software_init _nouveau_engine_init
#define _nouveau_software_fini _nouveau_engine_fini
extern struct nouveau_oclass nv04_software_oclass;
extern struct nouveau_oclass nv10_software_oclass;
extern struct nouveau_oclass nv50_software_oclass;
extern struct nouveau_oclass nvc0_software_oclass;
extern struct nouveau_oclass *nv04_software_oclass;
extern struct nouveau_oclass *nv10_software_oclass;
extern struct nouveau_oclass *nv50_software_oclass;
extern struct nouveau_oclass *nvc0_software_oclass;
void nv04_software_intr(struct nouveau_subdev *);

29
drivers/gpu/drm/nouveau/core/include/subdev/bios/boost.h Normal file
View File

@ -0,0 +1,29 @@
#ifndef __NVBIOS_BOOST_H__
#define __NVBIOS_BOOST_H__
u16 nvbios_boostTe(struct nouveau_bios *, u8 *, u8 *, u8 *, u8 *, u8 *, u8 *);
struct nvbios_boostE {
u8 pstate;
u32 min;
u32 max;
};
u16 nvbios_boostEe(struct nouveau_bios *, int idx, u8 *, u8 *, u8 *, u8 *);
u16 nvbios_boostEp(struct nouveau_bios *, int idx, u8 *, u8 *, u8 *, u8 *,
struct nvbios_boostE *);
u16 nvbios_boostEm(struct nouveau_bios *, u8, u8 *, u8 *, u8 *, u8 *,
struct nvbios_boostE *);
struct nvbios_boostS {
u8 domain;
u8 percent;
u32 min;
u32 max;
};
u16 nvbios_boostSe(struct nouveau_bios *, int, u16, u8 *, u8 *, u8, u8);
u16 nvbios_boostSp(struct nouveau_bios *, int, u16, u8 *, u8 *, u8, u8,
struct nvbios_boostS *);
#endif

28
drivers/gpu/drm/nouveau/core/include/subdev/bios/cstep.h Normal file
View File

@ -0,0 +1,28 @@
#ifndef __NVBIOS_CSTEP_H__
#define __NVBIOS_CSTEP_H__
u16 nvbios_cstepTe(struct nouveau_bios *,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz);
struct nvbios_cstepE {
u8 pstate;
u8 index;
};
u16 nvbios_cstepEe(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr);
u16 nvbios_cstepEp(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr,
struct nvbios_cstepE *);
u16 nvbios_cstepEm(struct nouveau_bios *, u8 pstate, u8 *ver, u8 *hdr,
struct nvbios_cstepE *);
struct nvbios_cstepX {
u32 freq;
u8 unkn[2];
u8 voltage;
};
u16 nvbios_cstepXe(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr);
u16 nvbios_cstepXp(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr,
struct nvbios_cstepX *);
#endif

10
drivers/gpu/drm/nouveau/core/include/subdev/bios/gpio.h
View File

@ -7,7 +7,15 @@ enum dcb_gpio_func_name {
DCB_GPIO_TVDAC1 = 0x2d,
DCB_GPIO_FAN = 0x09,
DCB_GPIO_FAN_SENSE = 0x3d,
DCB_GPIO_UNUSED = 0xff
DCB_GPIO_UNUSED = 0xff,
DCB_GPIO_VID0 = 0x04,
DCB_GPIO_VID1 = 0x05,
DCB_GPIO_VID2 = 0x06,
DCB_GPIO_VID3 = 0x1a,
DCB_GPIO_VID4 = 0x73,
DCB_GPIO_VID5 = 0x74,
DCB_GPIO_VID6 = 0x75,
DCB_GPIO_VID7 = 0x76,
};
#define DCB_GPIO_LOG_DIR 0x02

33
drivers/gpu/drm/nouveau/core/include/subdev/bios/perf.h
View File

@ -3,6 +3,39 @@
struct nouveau_bios;
u16 nvbios_perf_table(struct nouveau_bios *, u8 *ver, u8 *hdr,
u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
struct nvbios_perfE {
u8 pstate;
u8 fanspeed;
u8 voltage;
u32 core;
u32 shader;
u32 memory;
u32 vdec;
u32 disp;
u32 script;
};
u16 nvbios_perf_entry(struct nouveau_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u16 nvbios_perfEp(struct nouveau_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_perfE *);
struct nvbios_perfS {
union {
struct {
u32 freq;
} v40;
};
};
u32 nvbios_perfSe(struct nouveau_bios *, u32 data, int idx,
u8 *ver, u8 *hdr, u8 cnt, u8 len);
u32 nvbios_perfSp(struct nouveau_bios *, u32 data, int idx,
u8 *ver, u8 *hdr, u8 cnt, u8 len, struct nvbios_perfS *);
struct nvbios_perf_fan {
u32 pwm_divisor;
};

11
drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h Normal file
View File

@ -0,0 +1,11 @@
#ifndef __NVBIOS_RAMMAP_H__
#define __NVBIOS_RAMMAP_H__
u16 nvbios_rammap_table(struct nouveau_bios *, u8 *ver, u8 *hdr,
u8 *cnt, u8 *len, u8 *snr, u8 *ssz);
u16 nvbios_rammap_entry(struct nouveau_bios *, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u16 nvbios_rammap_match(struct nouveau_bios *, u16 khz,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
#endif

8
drivers/gpu/drm/nouveau/core/include/subdev/bios/timing.h Normal file
View File

@ -0,0 +1,8 @@
#ifndef __NVBIOS_TIMING_H__
#define __NVBIOS_TIMING_H__
u16 nvbios_timing_table(struct nouveau_bios *,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u16 nvbios_timing_entry(struct nouveau_bios *, int idx, u8 *ver, u8 *hdr);
#endif

25
drivers/gpu/drm/nouveau/core/include/subdev/bios/vmap.h Normal file
View File

@ -0,0 +1,25 @@
#ifndef __NVBIOS_VMAP_H__
#define __NVBIOS_VMAP_H__
struct nouveau_bios;
struct nvbios_vmap {
};
u16 nvbios_vmap_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u16 nvbios_vmap_parse(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_vmap *);
struct nvbios_vmap_entry {
u8 unk0;
u8 link;
u32 min;
u32 max;
s32 arg[6];
};
u16 nvbios_vmap_entry(struct nouveau_bios *, int idx, u8 *ver, u8 *len);
u16 nvbios_vmap_entry_parse(struct nouveau_bios *, int idx, u8 *ver, u8 *len,
struct nvbios_vmap_entry *);
#endif

27
drivers/gpu/drm/nouveau/core/include/subdev/bios/volt.h Normal file
View File

@ -0,0 +1,27 @@
#ifndef __NVBIOS_VOLT_H__
#define __NVBIOS_VOLT_H__
struct nouveau_bios;
struct nvbios_volt {
u8 vidmask;
u32 min;
u32 max;
u32 base;
s16 step;
};
u16 nvbios_volt_table(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len);
u16 nvbios_volt_parse(struct nouveau_bios *, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_volt *);
struct nvbios_volt_entry {
u32 voltage;
u8 vid;
};
u16 nvbios_volt_entry(struct nouveau_bios *, int idx, u8 *ver, u8 *len);
u16 nvbios_volt_entry_parse(struct nouveau_bios *, int idx, u8 *ver, u8 *len,
struct nvbios_volt_entry *);
#endif

20
drivers/gpu/drm/nouveau/core/include/subdev/bus.h
View File

@ -11,6 +11,8 @@ struct nouveau_bus_intr {
struct nouveau_bus {
struct nouveau_subdev base;
int (*hwsq_exec)(struct nouveau_bus *, u32 *, u32);
u32 hwsq_size;
};
static inline struct nouveau_bus *
@ -33,9 +35,19 @@ nouveau_bus(void *obj)
#define _nouveau_bus_init _nouveau_subdev_init
#define _nouveau_bus_fini _nouveau_subdev_fini
extern struct nouveau_oclass nv04_bus_oclass;
extern struct nouveau_oclass nv31_bus_oclass;
extern struct nouveau_oclass nv50_bus_oclass;
extern struct nouveau_oclass nvc0_bus_oclass;
extern struct nouveau_oclass *nv04_bus_oclass;
extern struct nouveau_oclass *nv31_bus_oclass;
extern struct nouveau_oclass *nv50_bus_oclass;
extern struct nouveau_oclass *nv94_bus_oclass;
extern struct nouveau_oclass *nvc0_bus_oclass;
/* interface to sequencer */
struct nouveau_hwsq;
int nouveau_hwsq_init(struct nouveau_bus *, struct nouveau_hwsq **);
int nouveau_hwsq_fini(struct nouveau_hwsq **, bool exec);
void nouveau_hwsq_wr32(struct nouveau_hwsq *, u32 addr, u32 data);
void nouveau_hwsq_setf(struct nouveau_hwsq *, u8 flag, int data);
void nouveau_hwsq_wait(struct nouveau_hwsq *, u8 flag, u8 data);
void nouveau_hwsq_nsec(struct nouveau_hwsq *, u32 nsec);
#endif

111
drivers/gpu/drm/nouveau/core/include/subdev/clock.h
View File

@ -7,9 +7,78 @@
struct nouveau_pll_vals;
struct nvbios_pll;
enum nv_clk_src {
nv_clk_src_crystal,
nv_clk_src_href,
nv_clk_src_hclk,
nv_clk_src_hclkm3,
nv_clk_src_hclkm3d2,
nv_clk_src_host,
nv_clk_src_sppll0,
nv_clk_src_sppll1,
nv_clk_src_mpllsrcref,
nv_clk_src_mpllsrc,
nv_clk_src_mpll,
nv_clk_src_mdiv,
nv_clk_src_core,
nv_clk_src_shader,
nv_clk_src_mem,
nv_clk_src_gpc,
nv_clk_src_rop,
nv_clk_src_hubk01,
nv_clk_src_hubk06,
nv_clk_src_hubk07,
nv_clk_src_copy,
nv_clk_src_daemon,
nv_clk_src_disp,
nv_clk_src_vdec,
nv_clk_src_dom6,
nv_clk_src_max,
};
struct nouveau_cstate {
struct list_head head;
u8 voltage;
u32 domain[nv_clk_src_max];
};
struct nouveau_pstate {
struct list_head head;
struct list_head list; /* c-states */
struct nouveau_cstate base;
u8 pstate;
u8 fanspeed;
};
struct nouveau_clock {
struct nouveau_subdev base;
struct nouveau_clocks *domains;
struct nouveau_pstate bstate;
struct list_head states;
int state_nr;
int pstate; /* current */
int ustate; /* user-requested (-1 disabled, -2 perfmon) */
int astate; /* perfmon adjustment (base) */
int tstate; /* thermal adjustment (max-) */
int dstate; /* display adjustment (min+) */
int (*read)(struct nouveau_clock *, enum nv_clk_src);
int (*calc)(struct nouveau_clock *, struct nouveau_cstate *);
int (*prog)(struct nouveau_clock *);
void (*tidy)(struct nouveau_clock *);
/*XXX: die, these are here *only* to support the completely
* bat-shit insane what-was-nouveau_hw.c code
*/
@ -25,27 +94,42 @@ nouveau_clock(void *obj)
return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_CLOCK];
}
#define nouveau_clock_create(p,e,o,d) \
nouveau_subdev_create((p), (e), (o), 0, "CLOCK", "clock", d)
#define nouveau_clock_destroy(p) \
nouveau_subdev_destroy(&(p)->base)
#define nouveau_clock_init(p) \
nouveau_subdev_init(&(p)->base)
struct nouveau_clocks {
enum nv_clk_src name;
u8 bios; /* 0xff for none */
#define NVKM_CLK_DOM_FLAG_CORE 0x01
u8 flags;
const char *mname;
int mdiv;
};
#define nouveau_clock_create(p,e,o,i,d) \
nouveau_clock_create_((p), (e), (o), (i), sizeof(**d), (void **)d)
#define nouveau_clock_destroy(p) ({ \
struct nouveau_clock *clk = (p); \
_nouveau_clock_dtor(nv_object(clk)); \
})
#define nouveau_clock_init(p) ({ \
struct nouveau_clock *clk = (p); \
_nouveau_clock_init(nv_object(clk)); \
})
#define nouveau_clock_fini(p,s) \
nouveau_subdev_fini(&(p)->base, (s))
int nouveau_clock_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32, int, void **);
#define _nouveau_clock_dtor _nouveau_subdev_dtor
#define _nouveau_clock_init _nouveau_subdev_init
struct nouveau_oclass *,
struct nouveau_clocks *, int, void **);
void _nouveau_clock_dtor(struct nouveau_object *);
int _nouveau_clock_init(struct nouveau_object *);
#define _nouveau_clock_fini _nouveau_subdev_fini
extern struct nouveau_oclass nv04_clock_oclass;
extern struct nouveau_oclass nv40_clock_oclass;
extern struct nouveau_oclass nv50_clock_oclass;
extern struct nouveau_oclass *nv50_clock_oclass;
extern struct nouveau_oclass *nv84_clock_oclass;
extern struct nouveau_oclass nva3_clock_oclass;
extern struct nouveau_oclass nvc0_clock_oclass;
extern struct nouveau_oclass nve0_clock_oclass;
int nv04_clock_pll_set(struct nouveau_clock *, u32 type, u32 freq);
int nv04_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
@ -55,4 +139,9 @@ int nv04_clock_pll_prog(struct nouveau_clock *, u32 reg1,
int nva3_clock_pll_calc(struct nouveau_clock *, struct nvbios_pll *,
int clk, struct nouveau_pll_vals *);
int nouveau_clock_ustate(struct nouveau_clock *, int req);
int nouveau_clock_astate(struct nouveau_clock *, int req, int rel);
int nouveau_clock_dstate(struct nouveau_clock *, int req, int rel);
int nouveau_clock_tstate(struct nouveau_clock *, int req, int rel);
#endif

50
drivers/gpu/drm/nouveau/core/include/subdev/fb.h
View File

@ -78,23 +78,28 @@ nouveau_fb(void *obj)
return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_FB];
}
extern struct nouveau_oclass nv04_fb_oclass;
extern struct nouveau_oclass nv10_fb_oclass;
extern struct nouveau_oclass nv1a_fb_oclass;
extern struct nouveau_oclass nv20_fb_oclass;
extern struct nouveau_oclass nv25_fb_oclass;
extern struct nouveau_oclass nv30_fb_oclass;
extern struct nouveau_oclass nv35_fb_oclass;
extern struct nouveau_oclass nv36_fb_oclass;
extern struct nouveau_oclass nv40_fb_oclass;
extern struct nouveau_oclass nv41_fb_oclass;
extern struct nouveau_oclass nv44_fb_oclass;
extern struct nouveau_oclass nv46_fb_oclass;
extern struct nouveau_oclass nv47_fb_oclass;
extern struct nouveau_oclass nv49_fb_oclass;
extern struct nouveau_oclass nv4e_fb_oclass;
extern struct nouveau_oclass nv50_fb_oclass;
extern struct nouveau_oclass nvc0_fb_oclass;
extern struct nouveau_oclass *nv04_fb_oclass;
extern struct nouveau_oclass *nv10_fb_oclass;
extern struct nouveau_oclass *nv1a_fb_oclass;
extern struct nouveau_oclass *nv20_fb_oclass;
extern struct nouveau_oclass *nv25_fb_oclass;
extern struct nouveau_oclass *nv30_fb_oclass;
extern struct nouveau_oclass *nv35_fb_oclass;
extern struct nouveau_oclass *nv36_fb_oclass;
extern struct nouveau_oclass *nv40_fb_oclass;
extern struct nouveau_oclass *nv41_fb_oclass;
extern struct nouveau_oclass *nv44_fb_oclass;
extern struct nouveau_oclass *nv46_fb_oclass;
extern struct nouveau_oclass *nv47_fb_oclass;
extern struct nouveau_oclass *nv49_fb_oclass;
extern struct nouveau_oclass *nv4e_fb_oclass;
extern struct nouveau_oclass *nv50_fb_oclass;
extern struct nouveau_oclass *nv84_fb_oclass;
extern struct nouveau_oclass *nva3_fb_oclass;
extern struct nouveau_oclass *nvaa_fb_oclass;
extern struct nouveau_oclass *nvaf_fb_oclass;
extern struct nouveau_oclass *nvc0_fb_oclass;
extern struct nouveau_oclass *nve0_fb_oclass;
struct nouveau_ram {
struct nouveau_object base;
@ -121,6 +126,17 @@ struct nouveau_ram {
int (*get)(struct nouveau_fb *, u64 size, u32 align,
u32 size_nc, u32 type, struct nouveau_mem **);
void (*put)(struct nouveau_fb *, struct nouveau_mem **);
int (*calc)(struct nouveau_fb *, u32 freq);
int (*prog)(struct nouveau_fb *);
void (*tidy)(struct nouveau_fb *);
struct {
u8 version;
u32 data;
u8 size;
} rammap, ramcfg, timing;
u32 freq;
u32 mr[16];
};
#endif

7
drivers/gpu/drm/nouveau/core/include/subdev/i2c.h
View File

@ -60,13 +60,18 @@ void _nouveau_i2c_port_dtor(struct nouveau_object *);
#define _nouveau_i2c_port_init nouveau_object_init
#define _nouveau_i2c_port_fini nouveau_object_fini
struct nouveau_i2c_board_info {
struct i2c_board_info dev;
u8 udelay; /* set to 0 to use the standard delay */
};
struct nouveau_i2c {
struct nouveau_subdev base;
struct nouveau_i2c_port *(*find)(struct nouveau_i2c *, u8 index);
struct nouveau_i2c_port *(*find_type)(struct nouveau_i2c *, u16 type);
int (*identify)(struct nouveau_i2c *, int index,
const char *what, struct i2c_board_info *,
const char *what, struct nouveau_i2c_board_info *,
bool (*match)(struct nouveau_i2c_port *,
struct i2c_board_info *));
struct list_head ports;

29
drivers/gpu/drm/nouveau/core/include/subdev/mc.h
View File

@ -11,7 +11,6 @@ struct nouveau_mc_intr {
struct nouveau_mc {
struct nouveau_subdev base;
const struct nouveau_mc_intr *intr_map;
bool use_msi;
};
@ -21,8 +20,8 @@ nouveau_mc(void *obj)
return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_MC];
}
#define nouveau_mc_create(p,e,o,m,d) \
nouveau_mc_create_((p), (e), (o), (m), sizeof(**d), (void **)d)
#define nouveau_mc_create(p,e,o,d) \
nouveau_mc_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nouveau_mc_destroy(p) ({ \
struct nouveau_mc *pmc = (p); _nouveau_mc_dtor(nv_object(pmc)); \
})
@ -34,20 +33,24 @@ nouveau_mc(void *obj)
})
int nouveau_mc_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, const struct nouveau_mc_intr *,
int, void **);
struct nouveau_oclass *, int, void **);
void _nouveau_mc_dtor(struct nouveau_object *);
int _nouveau_mc_init(struct nouveau_object *);
int _nouveau_mc_fini(struct nouveau_object *, bool);
extern struct nouveau_oclass nv04_mc_oclass;
extern struct nouveau_oclass nv44_mc_oclass;
extern struct nouveau_oclass nv50_mc_oclass;
extern struct nouveau_oclass nv98_mc_oclass;
extern struct nouveau_oclass nvc0_mc_oclass;
struct nouveau_mc_oclass {
struct nouveau_oclass base;
const struct nouveau_mc_intr *intr;
void (*msi_rearm)(struct nouveau_mc *);
};
extern const struct nouveau_mc_intr nv04_mc_intr[];
int nv04_mc_init(struct nouveau_object *);
int nv50_mc_init(struct nouveau_object *);
extern struct nouveau_oclass *nv04_mc_oclass;
extern struct nouveau_oclass *nv40_mc_oclass;
extern struct nouveau_oclass *nv44_mc_oclass;
extern struct nouveau_oclass *nv50_mc_oclass;
extern struct nouveau_oclass *nv94_mc_oclass;
extern struct nouveau_oclass *nv98_mc_oclass;
extern struct nouveau_oclass *nvc0_mc_oclass;
extern struct nouveau_oclass *nvc3_mc_oclass;
#endif

80
drivers/gpu/drm/nouveau/core/include/subdev/pwr.h Normal file
View File

@ -0,0 +1,80 @@
#ifndef __NOUVEAU_PWR_H__
#define __NOUVEAU_PWR_H__
#include <core/subdev.h>
#include <core/device.h>
struct nouveau_pwr {
struct nouveau_subdev base;
struct {
u32 limit;
u32 *data;
u32 size;
} code;
struct {
u32 limit;
u32 *data;
u32 size;
} data;
struct {
u32 base;
u32 size;
} send;
struct {
u32 base;
u32 size;
struct work_struct work;
wait_queue_head_t wait;
u32 process;
u32 message;
u32 data[2];
} recv;
int (*message)(struct nouveau_pwr *, u32[2], u32, u32, u32, u32);
};
static inline struct nouveau_pwr *
nouveau_pwr(void *obj)
{
return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_PWR];
}
#define nouveau_pwr_create(p, e, o, d) \
nouveau_pwr_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nouveau_pwr_destroy(p) \
nouveau_subdev_destroy(&(p)->base)
#define nouveau_pwr_init(p) ({ \
struct nouveau_pwr *ppwr = (p); \
_nouveau_pwr_init(nv_object(ppwr)); \
})
#define nouveau_pwr_fini(p,s) ({ \
struct nouveau_pwr *ppwr = (p); \
_nouveau_pwr_fini(nv_object(ppwr), (s)); \
})
int nouveau_pwr_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, int, void **);
#define _nouveau_pwr_dtor _nouveau_subdev_dtor
int _nouveau_pwr_init(struct nouveau_object *);
int _nouveau_pwr_fini(struct nouveau_object *, bool);
extern struct nouveau_oclass nva3_pwr_oclass;
extern struct nouveau_oclass nvc0_pwr_oclass;
extern struct nouveau_oclass nvd0_pwr_oclass;
extern struct nouveau_oclass nv108_pwr_oclass;
/* interface to MEMX process running on PPWR */
struct nouveau_memx;
int nouveau_memx_init(struct nouveau_pwr *, struct nouveau_memx **);
int nouveau_memx_fini(struct nouveau_memx **, bool exec);
void nouveau_memx_wr32(struct nouveau_memx *, u32 addr, u32 data);
void nouveau_memx_wait(struct nouveau_memx *,
u32 addr, u32 mask, u32 data, u32 nsec);
void nouveau_memx_nsec(struct nouveau_memx *, u32 nsec);
#endif

2
drivers/gpu/drm/nouveau/core/include/subdev/therm.h
View File

@ -71,6 +71,8 @@ void _nouveau_therm_dtor(struct nouveau_object *);
int _nouveau_therm_init(struct nouveau_object *);
int _nouveau_therm_fini(struct nouveau_object *, bool);
int nouveau_therm_cstate(struct nouveau_therm *, int, int);
extern struct nouveau_oclass nv40_therm_oclass;
extern struct nouveau_oclass nv50_therm_oclass;
extern struct nouveau_oclass nv84_therm_oclass;

60
drivers/gpu/drm/nouveau/core/include/subdev/volt.h Normal file
View File

@ -0,0 +1,60 @@
#ifndef __NOUVEAU_VOLT_H__
#define __NOUVEAU_VOLT_H__
#include <core/subdev.h>
#include <core/device.h>
struct nouveau_voltage {
u32 uv;
u8 id;
};
struct nouveau_volt {
struct nouveau_subdev base;
int (*vid_get)(struct nouveau_volt *);
int (*get)(struct nouveau_volt *);
int (*vid_set)(struct nouveau_volt *, u8 vid);
int (*set)(struct nouveau_volt *, u32 uv);
int (*set_id)(struct nouveau_volt *, u8 id, int condition);
u8 vid_mask;
u8 vid_nr;
struct {
u32 uv;
u8 vid;
} vid[256];
};
static inline struct nouveau_volt *
nouveau_volt(void *obj)
{
return (void *)nv_device(obj)->subdev[NVDEV_SUBDEV_VOLT];
}
#define nouveau_volt_create(p, e, o, d) \
nouveau_volt_create_((p), (e), (o), sizeof(**d), (void **)d)
#define nouveau_volt_destroy(p) ({ \
struct nouveau_volt *v = (p); \
_nouveau_volt_dtor(nv_object(v)); \
})
#define nouveau_volt_init(p) ({ \
struct nouveau_volt *v = (p); \
_nouveau_volt_init(nv_object(v)); \
})
#define nouveau_volt_fini(p,s) \
nouveau_subdev_fini((p), (s))
int nouveau_volt_create_(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, int, void **);
void _nouveau_volt_dtor(struct nouveau_object *);
int _nouveau_volt_init(struct nouveau_object *);
#define _nouveau_volt_fini _nouveau_subdev_fini
extern struct nouveau_oclass nv40_volt_oclass;
int nouveau_voltgpio_init(struct nouveau_volt *);
int nouveau_voltgpio_get(struct nouveau_volt *);
int nouveau_voltgpio_set(struct nouveau_volt *, u8);
#endif

127
drivers/gpu/drm/nouveau/core/subdev/bios/boost.c Normal file
View File

@ -0,0 +1,127 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/boost.h>
u16
nvbios_boostTe(struct nouveau_bios *bios,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
{
struct bit_entry bit_P;
u16 boost = 0x0000;
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 2)
boost = nv_ro16(bios, bit_P.offset + 0x30);
if (boost) {
*ver = nv_ro08(bios, boost + 0);
switch (*ver) {
case 0x11:
*hdr = nv_ro08(bios, boost + 1);
*cnt = nv_ro08(bios, boost + 5);
*len = nv_ro08(bios, boost + 2);
*snr = nv_ro08(bios, boost + 4);
*ssz = nv_ro08(bios, boost + 3);
return boost;
default:
break;
}
}
}
return 0x0000;
}
u16
nvbios_boostEe(struct nouveau_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u8 snr, ssz;
u16 data = nvbios_boostTe(bios, ver, hdr, cnt, len, &snr, &ssz);
if (data && idx < *cnt) {
data = data + *hdr + (idx * (*len + (snr * ssz)));
*hdr = *len;
*cnt = snr;
*len = ssz;
return data;
}
return 0x0000;
}
u16
nvbios_boostEp(struct nouveau_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_boostE *info)
{
u16 data = nvbios_boostEe(bios, idx, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
if (data) {
info->pstate = (nv_ro16(bios, data + 0x00) & 0x01e0) >> 5;
info->min = nv_ro16(bios, data + 0x02) * 1000;
info->max = nv_ro16(bios, data + 0x04) * 1000;
}
return data;
}
u16
nvbios_boostEm(struct nouveau_bios *bios, u8 pstate,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_boostE *info)
{
u32 data, idx = 0;
while ((data = nvbios_boostEp(bios, idx++, ver, hdr, cnt, len, info))) {
if (info->pstate == pstate)
break;
}
return data;
}
u16
nvbios_boostSe(struct nouveau_bios *bios, int idx,
u16 data, u8 *ver, u8 *hdr, u8 cnt, u8 len)
{
if (data && idx < cnt) {
data = data + *hdr + (idx * len);
*hdr = len;
return data;
}
return 0x0000;
}
u16
nvbios_boostSp(struct nouveau_bios *bios, int idx,
u16 data, u8 *ver, u8 *hdr, u8 cnt, u8 len,
struct nvbios_boostS *info)
{
data = nvbios_boostSe(bios, idx, data, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
if (data) {
info->domain = nv_ro08(bios, data + 0x00);
info->percent = nv_ro08(bios, data + 0x01);
info->min = nv_ro16(bios, data + 0x02) * 1000;
info->max = nv_ro16(bios, data + 0x04) * 1000;
}
return data;
}

123
drivers/gpu/drm/nouveau/core/subdev/bios/cstep.c Normal file
View File

@ -0,0 +1,123 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/cstep.h>
u16
nvbios_cstepTe(struct nouveau_bios *bios,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len, u8 *xnr, u8 *xsz)
{
struct bit_entry bit_P;
u16 cstep = 0x0000;
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 2)
cstep = nv_ro16(bios, bit_P.offset + 0x34);
if (cstep) {
*ver = nv_ro08(bios, cstep + 0);
switch (*ver) {
case 0x10:
*hdr = nv_ro08(bios, cstep + 1);
*cnt = nv_ro08(bios, cstep + 3);
*len = nv_ro08(bios, cstep + 2);
*xnr = nv_ro08(bios, cstep + 5);
*xsz = nv_ro08(bios, cstep + 4);
return cstep;
default:
break;
}
}
}
return 0x0000;
}
u16
nvbios_cstepEe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr)
{
u8 cnt, len, xnr, xsz;
u16 data = nvbios_cstepTe(bios, ver, hdr, &cnt, &len, &xnr, &xsz);
if (data && idx < cnt) {
data = data + *hdr + (idx * len);
*hdr = len;
return data;
}
return 0x0000;
}
u16
nvbios_cstepEp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
struct nvbios_cstepE *info)
{
u16 data = nvbios_cstepEe(bios, idx, ver, hdr);
memset(info, 0x00, sizeof(*info));
if (data) {
info->pstate = (nv_ro16(bios, data + 0x00) & 0x01e0) >> 5;
info->index = nv_ro08(bios, data + 0x03);
}
return data;
}
u16
nvbios_cstepEm(struct nouveau_bios *bios, u8 pstate, u8 *ver, u8 *hdr,
struct nvbios_cstepE *info)
{
u32 data, idx = 0;
while ((data = nvbios_cstepEp(bios, idx++, ver, hdr, info))) {
if (info->pstate == pstate)
break;
}
return data;
}
u16
nvbios_cstepXe(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr)
{
u8 cnt, len, xnr, xsz;
u16 data = nvbios_cstepTe(bios, ver, hdr, &cnt, &len, &xnr, &xsz);
if (data && idx < xnr) {
data = data + *hdr + (cnt * len) + (idx * xsz);
*hdr = xsz;
return data;
}
return 0x0000;
}
u16
nvbios_cstepXp(struct nouveau_bios *bios, int idx, u8 *ver, u8 *hdr,
struct nvbios_cstepX *info)
{
u16 data = nvbios_cstepXe(bios, idx, ver, hdr);
memset(info, 0x00, sizeof(*info));
if (data) {
info->freq = nv_ro16(bios, data + 0x00) * 1000;
info->unkn[0] = nv_ro08(bios, data + 0x02);
info->unkn[1] = nv_ro08(bios, data + 0x03);
info->voltage = nv_ro08(bios, data + 0x04);
}
return data;
}

10
drivers/gpu/drm/nouveau/core/subdev/bios/dp.c
View File

@ -89,6 +89,7 @@ nvbios_dpout_parse(struct nouveau_bios *bios, u8 idx,
struct nvbios_dpout *info)
{
u16 data = nvbios_dpout_entry(bios, idx, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
if (data && *ver) {
info->type = nv_ro16(bios, data + 0x00);
info->mask = nv_ro16(bios, data + 0x02);
@ -99,9 +100,12 @@ nvbios_dpout_parse(struct nouveau_bios *bios, u8 idx,
info->script[0] = nv_ro16(bios, data + 0x06);
info->script[1] = nv_ro16(bios, data + 0x08);
info->lnkcmp = nv_ro16(bios, data + 0x0a);
info->script[2] = nv_ro16(bios, data + 0x0c);
info->script[3] = nv_ro16(bios, data + 0x0e);
info->script[4] = nv_ro16(bios, data + 0x10);
if (*len >= 0x0f) {
info->script[2] = nv_ro16(bios, data + 0x0c);
info->script[3] = nv_ro16(bios, data + 0x0e);
}
if (*len >= 0x11)
info->script[4] = nv_ro16(bios, data + 0x10);
break;
case 0x40:
info->flags = nv_ro08(bios, data + 0x04);

4
drivers/gpu/drm/nouveau/core/subdev/bios/init.c
View File

@ -2180,7 +2180,7 @@ nvbios_init(struct nouveau_subdev *subdev, bool execute)
u16 data;
if (execute)
nv_suspend(bios, "running init tables\n");
nv_info(bios, "running init tables\n");
while (!ret && (data = (init_script(bios, ++i)))) {
struct nvbios_init init = {
.subdev = subdev,
@ -2210,5 +2210,5 @@ nvbios_init(struct nouveau_subdev *subdev, bool execute)
ret = nvbios_exec(&init);
}
return 0;
return ret;
}

140
drivers/gpu/drm/nouveau/core/subdev/bios/perf.c
View File

@ -26,8 +26,9 @@
#include <subdev/bios/bit.h>
#include <subdev/bios/perf.h>
static u16
perf_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
u16
nvbios_perf_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr,
u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
{
struct bit_entry bit_P;
u16 perf = 0x0000;
@ -38,10 +39,22 @@ perf_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
if (perf) {
*ver = nv_ro08(bios, perf + 0);
*hdr = nv_ro08(bios, perf + 1);
if (*ver >= 0x40 && *ver < 0x41) {
*cnt = nv_ro08(bios, perf + 5);
*len = nv_ro08(bios, perf + 2);
*snr = nv_ro08(bios, perf + 4);
*ssz = nv_ro08(bios, perf + 3);
return perf;
} else
if (*ver >= 0x20 && *ver < 0x40) {
*cnt = nv_ro08(bios, perf + 2);
*len = nv_ro08(bios, perf + 3);
*snr = nv_ro08(bios, perf + 4);
*ssz = nv_ro08(bios, perf + 5);
return perf;
}
}
} else
nv_error(bios, "unknown offset for perf in BIT P %d\n",
bit_P.version);
}
}
if (bios->bmp_offset) {
@ -50,19 +63,132 @@ perf_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
if (perf) {
*hdr = nv_ro08(bios, perf + 0);
*ver = nv_ro08(bios, perf + 1);
*cnt = nv_ro08(bios, perf + 2);
*len = nv_ro08(bios, perf + 3);
*snr = 0;
*ssz = 0;
return perf;
}
}
}
return 0x0000;
}
u16
nvbios_perf_entry(struct nouveau_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u8 snr, ssz;
u16 perf = nvbios_perf_table(bios, ver, hdr, cnt, len, &snr, &ssz);
if (perf && idx < *cnt) {
perf = perf + *hdr + (idx * (*len + (snr * ssz)));
*hdr = *len;
*cnt = snr;
*len = ssz;
return perf;
}
return 0x0000;
}
u16
nvbios_perfEp(struct nouveau_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_perfE *info)
{
u16 perf = nvbios_perf_entry(bios, idx, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
info->pstate = nv_ro08(bios, perf + 0x00);
switch (!!perf * *ver) {
case 0x12:
case 0x13:
case 0x14:
info->core = nv_ro32(bios, perf + 0x01) * 10;
info->memory = nv_ro32(bios, perf + 0x05) * 20;
info->fanspeed = nv_ro08(bios, perf + 0x37);
if (*hdr > 0x38)
info->voltage = nv_ro08(bios, perf + 0x38);
break;
case 0x21:
case 0x23:
case 0x24:
info->fanspeed = nv_ro08(bios, perf + 0x04);
info->voltage = nv_ro08(bios, perf + 0x05);
info->shader = nv_ro16(bios, perf + 0x06) * 1000;
info->core = info->shader + (signed char)
nv_ro08(bios, perf + 0x08) * 1000;
switch (nv_device(bios)->chipset) {
case 0x49:
case 0x4b:
info->memory = nv_ro16(bios, perf + 0x0b) * 1000;
break;
default:
info->memory = nv_ro16(bios, perf + 0x0b) * 2000;
break;
}
break;
case 0x25:
info->fanspeed = nv_ro08(bios, perf + 0x04);
info->voltage = nv_ro08(bios, perf + 0x05);
info->core = nv_ro16(bios, perf + 0x06) * 1000;
info->shader = nv_ro16(bios, perf + 0x0a) * 1000;
info->memory = nv_ro16(bios, perf + 0x0c) * 1000;
break;
case 0x30:
info->script = nv_ro16(bios, perf + 0x02);
case 0x35:
info->fanspeed = nv_ro08(bios, perf + 0x06);
info->voltage = nv_ro08(bios, perf + 0x07);
info->core = nv_ro16(bios, perf + 0x08) * 1000;
info->shader = nv_ro16(bios, perf + 0x0a) * 1000;
info->memory = nv_ro16(bios, perf + 0x0c) * 1000;
info->vdec = nv_ro16(bios, perf + 0x10) * 1000;
info->disp = nv_ro16(bios, perf + 0x14) * 1000;
break;
case 0x40:
info->voltage = nv_ro08(bios, perf + 0x02);
break;
default:
return 0x0000;
}
return perf;
}
u32
nvbios_perfSe(struct nouveau_bios *bios, u32 perfE, int idx,
u8 *ver, u8 *hdr, u8 cnt, u8 len)
{
u32 data = 0x00000000;
if (idx < cnt) {
data = perfE + *hdr + (idx * len);
*hdr = len;
}
return data;
}
u32
nvbios_perfSp(struct nouveau_bios *bios, u32 perfE, int idx,
u8 *ver, u8 *hdr, u8 cnt, u8 len,
struct nvbios_perfS *info)
{
u32 data = nvbios_perfSe(bios, perfE, idx, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
switch (!!data * *ver) {
case 0x40:
info->v40.freq = (nv_ro16(bios, data + 0x00) & 0x3fff) * 1000;
break;
default:
break;
}
return data;
}
int
nvbios_perf_fan_parse(struct nouveau_bios *bios,
struct nvbios_perf_fan *fan)
{
u8 ver = 0, hdr = 0, cnt = 0, len = 0;
u16 perf = perf_table(bios, &ver, &hdr, &cnt, &len);
u8 ver, hdr, cnt, len, snr, ssz;
u16 perf = nvbios_perf_table(bios, &ver, &hdr, &cnt, &len, &snr, &ssz);
if (!perf)
return -ENODEV;

1
drivers/gpu/drm/nouveau/core/subdev/bios/pll.c
View File

@ -114,6 +114,7 @@ pll_map(struct nouveau_bios *bios)
switch (nv_device(bios)->card_type) {
case NV_04:
case NV_10:
case NV_11:
case NV_20:
case NV_30:
return nv04_pll_mapping;

88
drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c Normal file
View File

@ -0,0 +1,88 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/rammap.h>
u16
nvbios_rammap_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr,
u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
{
struct bit_entry bit_P;
u16 rammap = 0x0000;
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 2)
rammap = nv_ro16(bios, bit_P.offset + 4);
if (rammap) {
*ver = nv_ro08(bios, rammap + 0);
switch (*ver) {
case 0x10:
case 0x11:
*hdr = nv_ro08(bios, rammap + 1);
*cnt = nv_ro08(bios, rammap + 5);
*len = nv_ro08(bios, rammap + 2);
*snr = nv_ro08(bios, rammap + 4);
*ssz = nv_ro08(bios, rammap + 3);
return rammap;
default:
break;
}
}
}
return 0x0000;
}
u16
nvbios_rammap_entry(struct nouveau_bios *bios, int idx,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
u8 snr, ssz;
u16 rammap = nvbios_rammap_table(bios, ver, hdr, cnt, len, &snr, &ssz);
if (rammap && idx < *cnt) {
rammap = rammap + *hdr + (idx * (*len + (snr * ssz)));
*hdr = *len;
*cnt = snr;
*len = ssz;
return rammap;
}
return 0x0000;
}
u16
nvbios_rammap_match(struct nouveau_bios *bios, u16 khz,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
int idx = 0;
u32 data;
while ((data = nvbios_rammap_entry(bios, idx++, ver, hdr, cnt, len))) {
if (khz >= nv_ro16(bios, data + 0x00) &&
khz <= nv_ro16(bios, data + 0x02))
break;
}
return data;
}

73
drivers/gpu/drm/nouveau/core/subdev/bios/timing.c Normal file
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@ -0,0 +1,73 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/timing.h>
u16
nvbios_timing_table(struct nouveau_bios *bios,
u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
struct bit_entry bit_P;
u16 timing = 0x0000;
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 1)
timing = nv_ro16(bios, bit_P.offset + 4);
else
if (bit_P.version == 2)
timing = nv_ro16(bios, bit_P.offset + 8);
if (timing) {
*ver = nv_ro08(bios, timing + 0);
switch (*ver) {
case 0x10:
*hdr = nv_ro08(bios, timing + 1);
*cnt = nv_ro08(bios, timing + 2);
*len = nv_ro08(bios, timing + 3);
return timing;
case 0x20:
*hdr = nv_ro08(bios, timing + 1);
*cnt = nv_ro08(bios, timing + 3);
*len = nv_ro08(bios, timing + 2);
return timing;
default:
break;
}
}
}
return 0x0000;
}
u16
nvbios_timing_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
{
u8 hdr, cnt;
u16 timing = nvbios_timing_table(bios, ver, &hdr, &cnt, len);
if (timing && idx < cnt)
return timing + hdr + (idx * *len);
return 0x0000;
}

112
drivers/gpu/drm/nouveau/core/subdev/bios/vmap.c Normal file
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@ -0,0 +1,112 @@
/*
* Copyright 2012 Nouveau Community
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Martin Peres
*/
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/vmap.h>
u16
nvbios_vmap_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
struct bit_entry bit_P;
u16 vmap = 0x0000;
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 2) {
vmap = nv_ro16(bios, bit_P.offset + 0x20);
if (vmap) {
*ver = nv_ro08(bios, vmap + 0);
switch (*ver) {
case 0x10:
case 0x20:
*hdr = nv_ro08(bios, vmap + 1);
*cnt = nv_ro08(bios, vmap + 3);
*len = nv_ro08(bios, vmap + 2);
return vmap;
default:
break;
}
}
}
}
return 0x0000;
}
u16
nvbios_vmap_parse(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_vmap *info)
{
u16 vmap = nvbios_vmap_table(bios, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
switch (!!vmap * *ver) {
case 0x10:
case 0x20:
break;
}
return vmap;
}
u16
nvbios_vmap_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
{
u8 hdr, cnt;
u16 vmap = nvbios_vmap_table(bios, ver, &hdr, &cnt, len);
if (vmap && idx < cnt) {
vmap = vmap + hdr + (idx * *len);
return vmap;
}
return 0x0000;
}
u16
nvbios_vmap_entry_parse(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len,
struct nvbios_vmap_entry *info)
{
u16 vmap = nvbios_vmap_entry(bios, idx, ver, len);
memset(info, 0x00, sizeof(*info));
switch (!!vmap * *ver) {
case 0x10:
info->link = 0xff;
info->min = nv_ro32(bios, vmap + 0x00);
info->max = nv_ro32(bios, vmap + 0x04);
info->arg[0] = nv_ro32(bios, vmap + 0x08);
info->arg[1] = nv_ro32(bios, vmap + 0x0c);
info->arg[2] = nv_ro32(bios, vmap + 0x10);
break;
case 0x20:
info->unk0 = nv_ro08(bios, vmap + 0x00);
info->link = nv_ro08(bios, vmap + 0x01);
info->min = nv_ro32(bios, vmap + 0x02);
info->max = nv_ro32(bios, vmap + 0x06);
info->arg[0] = nv_ro32(bios, vmap + 0x0a);
info->arg[1] = nv_ro32(bios, vmap + 0x0e);
info->arg[2] = nv_ro32(bios, vmap + 0x12);
info->arg[3] = nv_ro32(bios, vmap + 0x16);
info->arg[4] = nv_ro32(bios, vmap + 0x1a);
info->arg[5] = nv_ro32(bios, vmap + 0x1e);
break;
}
return vmap;
}

137
drivers/gpu/drm/nouveau/core/subdev/bios/volt.c Normal file
View File

@ -0,0 +1,137 @@
/*
* Copyright 2012 Nouveau Community
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Martin Peres
*/
#include <subdev/bios.h>
#include <subdev/bios/bit.h>
#include <subdev/bios/volt.h>
u16
nvbios_volt_table(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
struct bit_entry bit_P;
u16 volt = 0x0000;
if (!bit_entry(bios, 'P', &bit_P)) {
if (bit_P.version == 2)
volt = nv_ro16(bios, bit_P.offset + 0x0c);
else
if (bit_P.version == 1)
volt = nv_ro16(bios, bit_P.offset + 0x10);
if (volt) {
*ver = nv_ro08(bios, volt + 0);
switch (*ver) {
case 0x12:
*hdr = 5;
*cnt = nv_ro08(bios, volt + 2);
*len = nv_ro08(bios, volt + 1);
return volt;
case 0x20:
*hdr = nv_ro08(bios, volt + 1);
*cnt = nv_ro08(bios, volt + 2);
*len = nv_ro08(bios, volt + 3);
return volt;
case 0x30:
case 0x40:
case 0x50:
*hdr = nv_ro08(bios, volt + 1);
*cnt = nv_ro08(bios, volt + 3);
*len = nv_ro08(bios, volt + 2);
return volt;
}
}
}
return 0x0000;
}
u16
nvbios_volt_parse(struct nouveau_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
struct nvbios_volt *info)
{
u16 volt = nvbios_volt_table(bios, ver, hdr, cnt, len);
memset(info, 0x00, sizeof(*info));
switch (!!volt * *ver) {
case 0x12:
info->vidmask = nv_ro08(bios, volt + 0x04);
break;
case 0x20:
info->vidmask = nv_ro08(bios, volt + 0x05);
break;
case 0x30:
info->vidmask = nv_ro08(bios, volt + 0x04);
break;
case 0x40:
info->base = nv_ro32(bios, volt + 0x04);
info->step = nv_ro16(bios, volt + 0x08);
info->vidmask = nv_ro08(bios, volt + 0x0b);
/*XXX*/
info->min = 0;
info->max = info->base;
break;
case 0x50:
info->vidmask = nv_ro08(bios, volt + 0x06);
info->min = nv_ro32(bios, volt + 0x0a);
info->max = nv_ro32(bios, volt + 0x0e);
info->base = nv_ro32(bios, volt + 0x12) & 0x00ffffff;
info->step = nv_ro16(bios, volt + 0x16);
break;
}
return volt;
}
u16
nvbios_volt_entry(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len)
{
u8 hdr, cnt;
u16 volt = nvbios_volt_table(bios, ver, &hdr, &cnt, len);
if (volt && idx < cnt) {
volt = volt + hdr + (idx * *len);
return volt;
}
return 0x0000;
}
u16
nvbios_volt_entry_parse(struct nouveau_bios *bios, int idx, u8 *ver, u8 *len,
struct nvbios_volt_entry *info)
{
u16 volt = nvbios_volt_entry(bios, idx, ver, len);
memset(info, 0x00, sizeof(*info));
switch (!!volt * *ver) {
case 0x12:
case 0x20:
info->voltage = nv_ro08(bios, volt + 0x00) * 10000;
info->vid = nv_ro08(bios, volt + 0x01);
break;
case 0x30:
info->voltage = nv_ro08(bios, volt + 0x00) * 10000;
info->vid = nv_ro08(bios, volt + 0x01) >> 2;
break;
case 0x40:
case 0x50:
break;
}
return volt;
}

145
drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.c Normal file
View File

@ -0,0 +1,145 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
#include <subdev/timer.h>
#include <subdev/bus.h>
struct nouveau_hwsq {
struct nouveau_bus *pbus;
u32 addr;
u32 data;
struct {
u8 data[512];
u8 size;
} c;
};
static void
hwsq_cmd(struct nouveau_hwsq *hwsq, int size, u8 data[])
{
memcpy(&hwsq->c.data[hwsq->c.size], data, size * sizeof(data[0]));
hwsq->c.size += size;
}
int
nouveau_hwsq_init(struct nouveau_bus *pbus, struct nouveau_hwsq **phwsq)
{
struct nouveau_hwsq *hwsq;
hwsq = *phwsq = kmalloc(sizeof(*hwsq), GFP_KERNEL);
if (hwsq) {
hwsq->pbus = pbus;
hwsq->addr = ~0;
hwsq->data = ~0;
memset(hwsq->c.data, 0x7f, sizeof(hwsq->c.data));
hwsq->c.size = 0;
}
return hwsq ? 0 : -ENOMEM;
}
int
nouveau_hwsq_fini(struct nouveau_hwsq **phwsq, bool exec)
{
struct nouveau_hwsq *hwsq = *phwsq;
int ret = 0, i;
if (hwsq) {
struct nouveau_bus *pbus = hwsq->pbus;
hwsq->c.size = (hwsq->c.size + 4) / 4;
if (hwsq->c.size <= pbus->hwsq_size) {
if (exec)
ret = pbus->hwsq_exec(pbus, (u32 *)hwsq->c.data,
hwsq->c.size);
if (ret)
nv_error(pbus, "hwsq exec failed: %d\n", ret);
} else {
nv_error(pbus, "hwsq ucode too large\n");
ret = -ENOSPC;
}
for (i = 0; ret && i < hwsq->c.size; i++)
nv_error(pbus, "\t0x%08x\n", ((u32 *)hwsq->c.data)[i]);
*phwsq = NULL;
kfree(hwsq);
}
return ret;
}
void
nouveau_hwsq_wr32(struct nouveau_hwsq *hwsq, u32 addr, u32 data)
{
nv_debug(hwsq->pbus, "R[%06x] = 0x%08x\n", addr, data);
if (hwsq->data != data) {
if ((data & 0xffff0000) != (hwsq->data & 0xffff0000)) {
hwsq_cmd(hwsq, 5, (u8[]){ 0xe2, data, data >> 8,
data >> 16, data >> 24 });
} else {
hwsq_cmd(hwsq, 3, (u8[]){ 0x42, data, data >> 8 });
}
}
if ((addr & 0xffff0000) != (hwsq->addr & 0xffff0000)) {
hwsq_cmd(hwsq, 5, (u8[]){ 0xe0, addr, addr >> 8,
addr >> 16, addr >> 24 });
} else {
hwsq_cmd(hwsq, 3, (u8[]){ 0x40, addr, addr >> 8 });
}
hwsq->addr = addr;
hwsq->data = data;
}
void
nouveau_hwsq_setf(struct nouveau_hwsq *hwsq, u8 flag, int data)
{
nv_debug(hwsq->pbus, " FLAG[%02x] = %d\n", flag, data);
flag += 0x80;
if (data >= 0)
flag += 0x20;
if (data >= 1)
flag += 0x20;
hwsq_cmd(hwsq, 1, (u8[]){ flag });
}
void
nouveau_hwsq_wait(struct nouveau_hwsq *hwsq, u8 flag, u8 data)
{
nv_debug(hwsq->pbus, " WAIT[%02x] = %d\n", flag, data);
hwsq_cmd(hwsq, 3, (u8[]){ 0x5f, flag, data });
}
void
nouveau_hwsq_nsec(struct nouveau_hwsq *hwsq, u32 nsec)
{
u8 shift = 0, usec = nsec / 1000;
while (usec & ~3) {
usec >>= 2;
shift++;
}
nv_debug(hwsq->pbus, " DELAY = %d ns\n", nsec);
hwsq_cmd(hwsq, 1, (u8[]){ 0x00 | (shift << 2) | usec });
}

113
drivers/gpu/drm/nouveau/core/subdev/bus/hwsq.h Normal file
View File

@ -0,0 +1,113 @@
#ifndef __NVKM_BUS_HWSQ_H__
#define __NVKM_BUS_HWSQ_H__
#include <subdev/bus.h>
struct hwsq {
struct nouveau_subdev *subdev;
struct nouveau_hwsq *hwsq;
int sequence;
};
struct hwsq_reg {
int sequence;
bool force;
u32 addr[2];
u32 data;
};
static inline struct hwsq_reg
hwsq_reg2(u32 addr1, u32 addr2)
{
return (struct hwsq_reg) {
.sequence = 0,
.force = 0,
.addr = { addr1, addr2 },
.data = 0xdeadbeef,
};
}
static inline struct hwsq_reg
hwsq_reg(u32 addr)
{
return hwsq_reg2(addr, addr);
}
static inline int
hwsq_init(struct hwsq *ram, struct nouveau_subdev *subdev)
{
struct nouveau_bus *pbus = nouveau_bus(subdev);
int ret;
ret = nouveau_hwsq_init(pbus, &ram->hwsq);
if (ret)
return ret;
ram->sequence++;
ram->subdev = subdev;
return 0;
}
static inline int
hwsq_exec(struct hwsq *ram, bool exec)
{
int ret = 0;
if (ram->subdev) {
ret = nouveau_hwsq_fini(&ram->hwsq, exec);
ram->subdev = NULL;
}
return ret;
}
static inline u32
hwsq_rd32(struct hwsq *ram, struct hwsq_reg *reg)
{
if (reg->sequence != ram->sequence)
reg->data = nv_rd32(ram->subdev, reg->addr[0]);
return reg->data;
}
static inline void
hwsq_wr32(struct hwsq *ram, struct hwsq_reg *reg, u32 data)
{
reg->sequence = ram->sequence;
reg->data = data;
if (reg->addr[0] != reg->addr[1])
nouveau_hwsq_wr32(ram->hwsq, reg->addr[1], reg->data);
nouveau_hwsq_wr32(ram->hwsq, reg->addr[0], reg->data);
}
static inline void
hwsq_nuke(struct hwsq *ram, struct hwsq_reg *reg)
{
reg->force = true;
}
static inline u32
hwsq_mask(struct hwsq *ram, struct hwsq_reg *reg, u32 mask, u32 data)
{
u32 temp = hwsq_rd32(ram, reg);
if (temp != ((temp & ~mask) | data) || reg->force)
hwsq_wr32(ram, reg, (temp & ~mask) | data);
return temp;
}
static inline void
hwsq_setf(struct hwsq *ram, u8 flag, int data)
{
nouveau_hwsq_setf(ram->hwsq, flag, data);
}
static inline void
hwsq_wait(struct hwsq *ram, u8 flag, u8 data)
{
nouveau_hwsq_wait(ram->hwsq, flag, data);
}
static inline void
hwsq_nsec(struct hwsq *ram, u32 nsec)
{
nouveau_hwsq_nsec(ram->hwsq, nsec);
}
#endif

54
drivers/gpu/drm/nouveau/core/subdev/bus/nv04.c
View File

@ -23,11 +23,7 @@
* Ben Skeggs
*/
#include <subdev/bus.h>
struct nv04_bus_priv {
struct nouveau_bus base;
};
#include "nv04.h"
static void
nv04_bus_intr(struct nouveau_subdev *subdev)
@ -55,23 +51,6 @@ nv04_bus_intr(struct nouveau_subdev *subdev)
}
}
static int
nv04_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv04_bus_priv *priv;
int ret;
ret = nouveau_bus_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->intr = nv04_bus_intr;
return 0;
}
static int
nv04_bus_init(struct nouveau_object *object)
{
@ -83,13 +62,34 @@ nv04_bus_init(struct nouveau_object *object)
return nouveau_bus_init(&priv->base);
}
struct nouveau_oclass
nv04_bus_oclass = {
.handle = NV_SUBDEV(BUS, 0x04),
.ofuncs = &(struct nouveau_ofuncs) {
int
nv04_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv04_bus_impl *impl = (void *)oclass;
struct nv04_bus_priv *priv;
int ret;
ret = nouveau_bus_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->intr = impl->intr;
priv->base.hwsq_exec = impl->hwsq_exec;
priv->base.hwsq_size = impl->hwsq_size;
return 0;
}
struct nouveau_oclass *
nv04_bus_oclass = &(struct nv04_bus_impl) {
.base.handle = NV_SUBDEV(BUS, 0x04),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_bus_ctor,
.dtor = _nouveau_bus_dtor,
.init = nv04_bus_init,
.fini = _nouveau_bus_fini,
},
};
.intr = nv04_bus_intr,
}.base;

23
drivers/gpu/drm/nouveau/core/subdev/bus/nv04.h Normal file
View File

@ -0,0 +1,23 @@
#ifndef __NVKM_BUS_NV04_H__
#define __NVKM_BUS_NV04_H__
#include <subdev/bus.h>
struct nv04_bus_priv {
struct nouveau_bus base;
};
int nv04_bus_ctor(struct nouveau_object *, struct nouveau_object *,
struct nouveau_oclass *, void *, u32,
struct nouveau_object **);
int nv50_bus_init(struct nouveau_object *);
void nv50_bus_intr(struct nouveau_subdev *);
struct nv04_bus_impl {
struct nouveau_oclass base;
void (*intr)(struct nouveau_subdev *);
int (*hwsq_exec)(struct nouveau_bus *, u32 *, u32);
u32 hwsq_size;
};
#endif

38
drivers/gpu/drm/nouveau/core/subdev/bus/nv31.c
View File

@ -23,11 +23,7 @@
* Ben Skeggs
*/
#include <subdev/bus.h>
struct nv31_bus_priv {
struct nouveau_bus base;
};
#include "nv04.h"
static void
nv31_bus_intr(struct nouveau_subdev *subdev)
@ -71,7 +67,7 @@ nv31_bus_intr(struct nouveau_subdev *subdev)
static int
nv31_bus_init(struct nouveau_object *object)
{
struct nv31_bus_priv *priv = (void *)object;
struct nv04_bus_priv *priv = (void *)object;
int ret;
ret = nouveau_bus_init(&priv->base);
@ -83,30 +79,14 @@ nv31_bus_init(struct nouveau_object *object)
return 0;
}
static int
nv31_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv31_bus_priv *priv;
int ret;
ret = nouveau_bus_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->intr = nv31_bus_intr;
return 0;
}
struct nouveau_oclass
nv31_bus_oclass = {
.handle = NV_SUBDEV(BUS, 0x31),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv31_bus_ctor,
struct nouveau_oclass *
nv31_bus_oclass = &(struct nv04_bus_impl) {
.base.handle = NV_SUBDEV(BUS, 0x31),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_bus_ctor,
.dtor = _nouveau_bus_dtor,
.init = nv31_bus_init,
.fini = _nouveau_bus_fini,
},
};
.intr = nv31_bus_intr,
}.base;

60
drivers/gpu/drm/nouveau/core/subdev/bus/nv50.c
View File

@ -23,13 +23,27 @@
* Ben Skeggs
*/
#include <subdev/bus.h>
#include <subdev/timer.h>
struct nv50_bus_priv {
struct nouveau_bus base;
};
#include "nv04.h"
static void
static int
nv50_bus_hwsq_exec(struct nouveau_bus *pbus, u32 *data, u32 size)
{
struct nv50_bus_priv *priv = (void *)pbus;
int i;
nv_mask(pbus, 0x001098, 0x00000008, 0x00000000);
nv_wr32(pbus, 0x001304, 0x00000000);
for (i = 0; i < size; i++)
nv_wr32(priv, 0x001400 + (i * 4), data[i]);
nv_mask(pbus, 0x001098, 0x00000018, 0x00000018);
nv_wr32(pbus, 0x00130c, 0x00000003);
return nv_wait(pbus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT;
}
void
nv50_bus_intr(struct nouveau_subdev *subdev)
{
struct nouveau_bus *pbus = nouveau_bus(subdev);
@ -61,10 +75,10 @@ nv50_bus_intr(struct nouveau_subdev *subdev)
}
}
static int
int
nv50_bus_init(struct nouveau_object *object)
{
struct nv50_bus_priv *priv = (void *)object;
struct nv04_bus_priv *priv = (void *)object;
int ret;
ret = nouveau_bus_init(&priv->base);
@ -76,30 +90,16 @@ nv50_bus_init(struct nouveau_object *object)
return 0;
}
static int
nv50_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nv50_bus_priv *priv;
int ret;
ret = nouveau_bus_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->intr = nv50_bus_intr;
return 0;
}
struct nouveau_oclass
nv50_bus_oclass = {
.handle = NV_SUBDEV(BUS, 0x50),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv50_bus_ctor,
struct nouveau_oclass *
nv50_bus_oclass = &(struct nv04_bus_impl) {
.base.handle = NV_SUBDEV(BUS, 0x50),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_bus_ctor,
.dtor = _nouveau_bus_dtor,
.init = nv50_bus_init,
.fini = _nouveau_bus_fini,
},
};
.intr = nv50_bus_intr,
.hwsq_exec = nv50_bus_hwsq_exec,
.hwsq_size = 64,
}.base;

59
drivers/gpu/drm/nouveau/core/subdev/bus/nv94.c Normal file
View File

@ -0,0 +1,59 @@
/*
* Copyright 2012 Nouveau Community
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Martin Peres <martin.peres@labri.fr>
* Ben Skeggs
*/
#include <subdev/timer.h>
#include "nv04.h"
static int
nv94_bus_hwsq_exec(struct nouveau_bus *pbus, u32 *data, u32 size)
{
struct nv50_bus_priv *priv = (void *)pbus;
int i;
nv_mask(pbus, 0x001098, 0x00000008, 0x00000000);
nv_wr32(pbus, 0x001304, 0x00000000);
nv_wr32(pbus, 0x001318, 0x00000000);
for (i = 0; i < size; i++)
nv_wr32(priv, 0x080000 + (i * 4), data[i]);
nv_mask(pbus, 0x001098, 0x00000018, 0x00000018);
nv_wr32(pbus, 0x00130c, 0x00000001);
return nv_wait(pbus, 0x001308, 0x00000100, 0x00000000) ? 0 : -ETIMEDOUT;
}
struct nouveau_oclass *
nv94_bus_oclass = &(struct nv04_bus_impl) {
.base.handle = NV_SUBDEV(BUS, 0x94),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_bus_ctor,
.dtor = _nouveau_bus_dtor,
.init = nv50_bus_init,
.fini = _nouveau_bus_fini,
},
.intr = nv50_bus_intr,
.hwsq_exec = nv94_bus_hwsq_exec,
.hwsq_size = 128,
}.base;

38
drivers/gpu/drm/nouveau/core/subdev/bus/nvc0.c
View File

@ -23,11 +23,7 @@
* Ben Skeggs
*/
#include <subdev/bus.h>
struct nvc0_bus_priv {
struct nouveau_bus base;
};
#include "nv04.h"
static void
nvc0_bus_intr(struct nouveau_subdev *subdev)
@ -60,7 +56,7 @@ nvc0_bus_intr(struct nouveau_subdev *subdev)
static int
nvc0_bus_init(struct nouveau_object *object)
{
struct nvc0_bus_priv *priv = (void *)object;
struct nv04_bus_priv *priv = (void *)object;
int ret;
ret = nouveau_bus_init(&priv->base);
@ -72,30 +68,14 @@ nvc0_bus_init(struct nouveau_object *object)
return 0;
}
static int
nvc0_bus_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nouveau_oclass *oclass, void *data, u32 size,
struct nouveau_object **pobject)
{
struct nvc0_bus_priv *priv;
int ret;
ret = nouveau_bus_create(parent, engine, oclass, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;
nv_subdev(priv)->intr = nvc0_bus_intr;
return 0;
}
struct nouveau_oclass
nvc0_bus_oclass = {
.handle = NV_SUBDEV(BUS, 0xc0),
.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nvc0_bus_ctor,
struct nouveau_oclass *
nvc0_bus_oclass = &(struct nv04_bus_impl) {
.base.handle = NV_SUBDEV(BUS, 0xc0),
.base.ofuncs = &(struct nouveau_ofuncs) {
.ctor = nv04_bus_ctor,
.dtor = _nouveau_bus_dtor,
.init = nvc0_bus_init,
.fini = _nouveau_bus_fini,
},
};
.intr = nvc0_bus_intr,
}.base;

494
drivers/gpu/drm/nouveau/core/subdev/clock/base.c Normal file
View File

@ -0,0 +1,494 @@
/*
* Copyright 2013 Red Hat Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: Ben Skeggs
*/
#include <core/option.h>
#include <subdev/clock.h>
#include <subdev/therm.h>
#include <subdev/volt.h>
#include <subdev/fb.h>
#include <subdev/bios.h>
#include <subdev/bios/boost.h>
#include <subdev/bios/cstep.h>
#include <subdev/bios/perf.h>
/******************************************************************************
* misc
*****************************************************************************/
static u32
nouveau_clock_adjust(struct nouveau_clock *clk, bool adjust,
u8 pstate, u8 domain, u32 input)
{
struct nouveau_bios *bios = nouveau_bios(clk);
struct nvbios_boostE boostE;
u8 ver, hdr, cnt, len;
u16 data;
data = nvbios_boostEm(bios, pstate, &ver, &hdr, &cnt, &len, &boostE);
if (data) {
struct nvbios_boostS boostS;
u8 idx = 0, sver, shdr;
u16 subd;
input = max(boostE.min, input);
input = min(boostE.max, input);
do {
sver = ver;
shdr = hdr;
subd = nvbios_boostSp(bios, idx++, data, &sver, &shdr,
cnt, len, &boostS);
if (subd && boostS.domain == domain) {
if (adjust)
input = input * boostS.percent / 100;
input = max(boostS.min, input);
input = min(boostS.max, input);
break;
}
} while (subd);
}
return input;
}
/******************************************************************************
* C-States
*****************************************************************************/
static int
nouveau_cstate_prog(struct nouveau_clock *clk,
struct nouveau_pstate *pstate, int cstatei)
{
struct nouveau_therm *ptherm = nouveau_therm(clk);
struct nouveau_volt *volt = nouveau_volt(clk);
struct nouveau_cstate *cstate;
int ret;
if (!list_empty(&pstate->list)) {
cstate = list_entry(pstate->list.prev, typeof(*cstate), head);
} else {
cstate = &pstate->base;
}
ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, +1);
if (ret && ret != -ENODEV) {
nv_error(clk, "failed to raise fan speed: %d\n", ret);
return ret;
}
ret = volt->set_id(volt, cstate->voltage, +1);
if (ret && ret != -ENODEV) {
nv_error(clk, "failed to raise voltage: %d\n", ret);
return ret;
}
ret = clk->calc(clk, cstate);
if (ret == 0) {
ret = clk->prog(clk);
clk->tidy(clk);
}
ret = volt->set_id(volt, cstate->voltage, -1);
if (ret && ret != -ENODEV)
nv_error(clk, "failed to lower voltage: %d\n", ret);
ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, -1);
if (ret && ret != -ENODEV)
nv_error(clk, "failed to lower fan speed: %d\n", ret);
return 0;
}
static void
nouveau_cstate_del(struct nouveau_cstate *cstate)
{
list_del(&cstate->head);
kfree(cstate);
}
static int
nouveau_cstate_new(struct nouveau_clock *clk, int idx,
struct nouveau_pstate *pstate)
{
struct nouveau_bios *bios = nouveau_bios(clk);
struct nouveau_clocks *domain = clk->domains;
struct nouveau_cstate *cstate = NULL;
struct nvbios_cstepX cstepX;
u8 ver, hdr;
u16 data;
data = nvbios_cstepXp(bios, idx, &ver, &hdr, &cstepX);
if (!data)
return -ENOENT;
cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
if (!cstate)
return -ENOMEM;
*cstate = pstate->base;
cstate->voltage = cstepX.voltage;
while (domain && domain->name != nv_clk_src_max) {
if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
u32 freq = nouveau_clock_adjust(clk, true,
pstate->pstate,
domain->bios,
cstepX.freq);
cstate->domain[domain->name] = freq;
}
domain++;
}
list_add(&cstate->head, &pstate->list);
return 0;
}
/******************************************************************************
* P-States
*****************************************************************************/
static int
nouveau_pstate_prog(struct nouveau_clock *clk, int pstatei)
{
struct nouveau_fb *pfb = nouveau_fb(clk);
struct nouveau_pstate *pstate;
int ret, idx = 0;
list_for_each_entry(pstate, &clk->states, head) {
if (idx++ == pstatei)
break;
}
nv_debug(clk, "setting performance state %d\n", pstatei);
clk->pstate = pstatei;
if (pfb->ram->calc) {
ret = pfb->ram->calc(pfb, pstate->base.domain[nv_clk_src_mem]);
if (ret == 0)
ret = pfb->ram->prog(pfb);
pfb->ram->tidy(pfb);
}
return nouveau_cstate_prog(clk, pstate, 0);
}
static int
nouveau_pstate_calc(struct nouveau_clock *clk)
{
int pstate, ret = 0;
nv_trace(clk, "P %d U %d A %d T %d D %d\n", clk->pstate,
clk->ustate, clk->astate, clk->tstate, clk->dstate);
if (clk->state_nr && clk->ustate != -1) {
pstate = (clk->ustate < 0) ? clk->astate : clk->ustate;
pstate = min(pstate, clk->state_nr - 1 - clk->tstate);
pstate = max(pstate, clk->dstate);
} else {
pstate = clk->pstate = -1;
}
nv_trace(clk, "-> %d\n", pstate);
if (pstate != clk->pstate)
ret = nouveau_pstate_prog(clk, pstate);
return ret;
}
static void
nouveau_pstate_info(struct nouveau_clock *clk, struct nouveau_pstate *pstate)
{
struct nouveau_clocks *clock = clk->domains - 1;
struct nouveau_cstate *cstate;
char info[3][32] = { "", "", "" };
char name[4] = "--";
int i = -1;
if (pstate->pstate != 0xff)
snprintf(name, sizeof(name), "%02x", pstate->pstate);
while ((++clock)->name != nv_clk_src_max) {
u32 lo = pstate->base.domain[clock->name];
u32 hi = lo;
if (hi == 0)
continue;
nv_debug(clk, "%02x: %10d KHz\n", clock->name, lo);
list_for_each_entry(cstate, &pstate->list, head) {
u32 freq = cstate->domain[clock->name];
lo = min(lo, freq);
hi = max(hi, freq);
nv_debug(clk, "%10d KHz\n", freq);
}
if (clock->mname && ++i < ARRAY_SIZE(info)) {
lo /= clock->mdiv;
hi /= clock->mdiv;
if (lo == hi) {
snprintf(info[i], sizeof(info[i]), "%s %d MHz",
clock->mname, lo);
} else {
snprintf(info[i], sizeof(info[i]),
"%s %d-%d MHz", clock->mname, lo, hi);
}
}
}
nv_info(clk, "%s: %s %s %s\n", name, info[0], info[1], info[2]);
}
static void
nouveau_pstate_del(struct nouveau_pstate *pstate)
{
struct nouveau_cstate *cstate, *temp;
list_for_each_entry_safe(cstate, temp, &pstate->list, head) {
nouveau_cstate_del(cstate);
}
list_del(&pstate->head);
kfree(pstate);
}
static int
nouveau_pstate_new(struct nouveau_clock *clk, int idx)
{
struct nouveau_bios *bios = nouveau_bios(clk);
struct nouveau_clocks *domain = clk->domains - 1;
struct nouveau_pstate *pstate;
struct nouveau_cstate *cstate;
struct nvbios_cstepE cstepE;
struct nvbios_perfE perfE;
u8 ver, hdr, cnt, len;
u16 data;
data = nvbios_perfEp(bios, idx, &ver, &hdr, &cnt, &len, &perfE);
if (!data)
return -EINVAL;
if (perfE.pstate == 0xff)
return 0;
pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
cstate = &pstate->base;
if (!pstate)
return -ENOMEM;
INIT_LIST_HEAD(&pstate->list);
pstate->pstate = perfE.pstate;
pstate->fanspeed = perfE.fanspeed;
cstate->voltage = perfE.voltage;
cstate->domain[nv_clk_src_core] = perfE.core;
cstate->domain[nv_clk_src_shader] = perfE.shader;
cstate->domain[nv_clk_src_mem] = perfE.memory;
cstate->domain[nv_clk_src_vdec] = perfE.vdec;
cstate->domain[nv_clk_src_dom6] = perfE.disp;
while (ver >= 0x40 && (++domain)->name != nv_clk_src_max) {
struct nvbios_perfS perfS;
u8 sver = ver, shdr = hdr;
u32 perfSe = nvbios_perfSp(bios, data, domain->bios,
&sver, &shdr, cnt, len, &perfS);
if (perfSe == 0 || sver != 0x40)
continue;
if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
perfS.v40.freq = nouveau_clock_adjust(clk, false,
pstate->pstate,
domain->bios,
perfS.v40.freq);
}
cstate->domain[domain->name] = perfS.v40.freq;
}
data = nvbios_cstepEm(bios, pstate->pstate, &ver, &hdr, &cstepE);
if (data) {
int idx = cstepE.index;
do {
nouveau_cstate_new(clk, idx, pstate);
} while(idx--);
}
nouveau_pstate_info(clk, pstate);
list_add_tail(&pstate->head, &clk->states);
clk->state_nr++;
return 0;
}
/******************************************************************************
* Adjustment triggers
*****************************************************************************/
static int
nouveau_clock_ustate_update(struct nouveau_clock *clk, int req)
{
struct nouveau_pstate *pstate;
int i = 0;
/* YKW repellant */
return -ENOSYS;
if (req != -1 && req != -2) {
list_for_each_entry(pstate, &clk->states, head) {
if (pstate->pstate == req)
break;
i++;
}
if (pstate->pstate != req)
return -EINVAL;
req = i;
}
clk->ustate = req;
return 0;
}
int
nouveau_clock_ustate(struct nouveau_clock *clk, int req)
{
int ret = nouveau_clock_ustate_update(clk, req);
if (ret)
return ret;
return nouveau_pstate_calc(clk);
}
int
nouveau_clock_astate(struct nouveau_clock *clk, int req, int rel)
{
if (!rel) clk->astate = req;
if ( rel) clk->astate += rel;
clk->astate = min(clk->astate, clk->state_nr - 1);
clk->astate = max(clk->astate, 0);
return nouveau_pstate_calc(clk);
}
int
nouveau_clock_tstate(struct nouveau_clock *clk, int req, int rel)
{
if (!rel) clk->tstate = req;
if ( rel) clk->tstate += rel;
clk->tstate = min(clk->tstate, 0);
clk->tstate = max(clk->tstate, -(clk->state_nr - 1));
return nouveau_pstate_calc(clk);
}
int
nouveau_clock_dstate(struct nouveau_clock *clk, int req, int rel)
{
if (!rel) clk->dstate = req;
if ( rel) clk->dstate += rel;
clk->dstate = min(clk->dstate, clk->state_nr - 1);
clk->dstate = max(clk->dstate, 0);
return nouveau_pstate_calc(clk);
}
/******************************************************************************
* subdev base class implementation
*****************************************************************************/
int
_nouveau_clock_init(struct nouveau_object *object)
{
struct nouveau_clock *clk = (void *)object;
struct nouveau_clocks *clock = clk->domains;
int ret;
memset(&clk->bstate, 0x00, sizeof(clk->bstate));
INIT_LIST_HEAD(&clk->bstate.list);
clk->bstate.pstate = 0xff;
while (clock->name != nv_clk_src_max) {
ret = clk->read(clk, clock->name);
if (ret < 0) {
nv_error(clk, "%02x freq unknown\n", clock->name);
return ret;
}
clk->bstate.base.domain[clock->name] = ret;
clock++;
}
nouveau_pstate_info(clk, &clk->bstate);
clk->astate = clk->state_nr - 1;
clk->tstate = 0;
clk->dstate = 0;
clk->pstate = -1;
nouveau_pstate_calc(clk);
return 0;
}
void
_nouveau_clock_dtor(struct nouveau_object *object)
{
struct nouveau_clock *clk = (void *)object;
struct nouveau_pstate *pstate, *temp;
list_for_each_entry_safe(pstate, temp, &clk->states, head) {
nouveau_pstate_del(pstate);
}
nouveau_subdev_destroy(&clk->base);
}
int
nouveau_clock_create_(struct nouveau_object *parent,
struct nouveau_object *engine,
struct nouveau_oclass *oclass,
struct nouveau_clocks *clocks,
int length, void **object)
{
struct nouveau_device *device = nv_device(parent);
struct nouveau_clock *clk;
int ret, idx, arglen;
const char *mode;
ret = nouveau_subdev_create_(parent, engine, oclass, 0, "CLK",
"clock", length, object);
clk = *object;
if (ret)
return ret;
INIT_LIST_HEAD(&clk->states);
clk->domains = clocks;
clk->ustate = -1;
idx = 0;
do {
ret = nouveau_pstate_new(clk, idx++);
} while (ret == 0);
mode = nouveau_stropt(device->cfgopt, "NvClkMode", &arglen);
if (mode) {
if (!strncasecmpz(mode, "disabled", arglen)) {
clk->ustate = -1;
} else {
char save = mode[arglen];
long v;
((char *)mode)[arglen] = '\0';
if (!kstrtol(mode, 0, &v))
nouveau_clock_ustate_update(clk, v);
((char *)mode)[arglen] = save;
}
}
return 0;
}

2
drivers/gpu/drm/nouveau/core/subdev/clock/nv04.c
View File

@ -77,7 +77,7 @@ nv04_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
struct nv04_clock_priv *priv;
int ret;
ret = nouveau_clock_create(parent, engine, oclass, &priv);
ret = nouveau_clock_create(parent, engine, oclass, NULL, &priv);
*pobject = nv_object(priv);
if (ret)
return ret;

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