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MIPS: uasm: add jalr instruction

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This patch allows use of the jalr instruction from uasm. It will be used
by a subsequent patch.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
This commit is contained in:
Paul Burton 2014-03-16 12:58:05 +00:00
parent 8dee5901b2
commit 49e9529b9d
3 changed files with 10 additions and 4 deletions
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4
arch/mips/include/asm/uasm.h
View File

@ -74,6 +74,9 @@ void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b, unsigned int c, \
#define Ip_u1u2(op) \ #define Ip_u1u2(op) \
void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b) void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b)
#define Ip_u2u1(op) \
void ISAOPC(op)(u32 **buf, unsigned int a, unsigned int b)
#define Ip_u1s2(op) \ #define Ip_u1s2(op) \
void ISAOPC(op)(u32 **buf, unsigned int a, signed int b) void ISAOPC(op)(u32 **buf, unsigned int a, signed int b)
@ -114,6 +117,7 @@ Ip_u2u1msbu3(_ext);
Ip_u2u1msbu3(_ins); Ip_u2u1msbu3(_ins);
Ip_u1(_j); Ip_u1(_j);
Ip_u1(_jal); Ip_u1(_jal);
Ip_u2u1(_jalr);
Ip_u1(_jr); Ip_u1(_jr);
Ip_u2s3u1(_ld); Ip_u2s3u1(_ld);
Ip_u3u1u2(_ldx); Ip_u3u1u2(_ldx);

1
arch/mips/mm/uasm-mips.c
View File

@ -82,6 +82,7 @@ static struct insn insn_table[] = {
{ insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE }, { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE },
{ insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
{ insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM }, { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM },
{ insn_jalr, M(spec_op, 0, 0, 0, 0, jalr_op), RS | RD },
{ insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM }, { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
{ insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS }, { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS },
{ insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },

9
arch/mips/mm/uasm.c
View File

@ -49,10 +49,10 @@ enum opcode {
insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm, insn_bne, insn_cache, insn_daddiu, insn_daddu, insn_dins, insn_dinsm,
insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll, insn_dmfc0, insn_dmtc0, insn_drotr, insn_drotr32, insn_dsll,
insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret, insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
insn_ext, insn_ins, insn_j, insn_jal, insn_jr, insn_ld, insn_ldx, insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_ld,
insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0, insn_mtc0, insn_ldx, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0,
insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc, insn_scd, insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc,
insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw, insn_scd, insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw,
insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_syscall, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor,
insn_xori, insn_xori,
}; };
@ -250,6 +250,7 @@ I_u2u1msbdu3(_ext)
I_u2u1msbu3(_ins) I_u2u1msbu3(_ins)
I_u1(_j) I_u1(_j)
I_u1(_jal) I_u1(_jal)
I_u2u1(_jalr)
I_u1(_jr) I_u1(_jr)
I_u2s3u1(_ld) I_u2s3u1(_ld)
I_u2s3u1(_ll) I_u2s3u1(_ll)