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MIPS: pass non-NULL dev_id on shared request_irq()
Recently all usages of setup_irq() was replaced by request_irq().
request_irq() does a few sanity checks that were not done in
setup_irq(), if they fail irq registration will fail. One of the check
is to ensure that non-NULL dev_id is passed in the case of shared irq.
This caused malta on qemu to hang.
Fix it by passing handler as dev_id to all request_irq()'s that are
shared. For sni, instead of passing non-NULL dev_id, remove shared irq
flags.
Fixes: ac8fd122e0
("MIPS: Replace setup_irq() by request_irq()")
Reported-by: Nathan Chancellor <natechancellor@gmail.com>
Suggested-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: afzal mohammed <afzal.mohd.ma@gmail.com>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Tested-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
parent
ac8fd122e0
commit
49e6e07e3c
@ -758,7 +758,7 @@ void __init arch_init_irq(void)
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/* Register the bus error interrupt. */
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if (dec_interrupt[DEC_IRQ_BUS] >= 0 && busirq_handler) {
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if (request_irq(dec_interrupt[DEC_IRQ_BUS], busirq_handler,
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busirq_flags, "bus error", NULL))
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busirq_flags, "bus error", busirq_handler))
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pr_err("Failed to register bus error interrupt\n");
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}
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/* Register the HALT interrupt. */
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@ -292,7 +292,8 @@ int r4k_clockevent_init(void)
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cp0_timer_irq_installed = 1;
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if (request_irq(irq, c0_compare_interrupt, flags, "timer", NULL))
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if (request_irq(irq, c0_compare_interrupt, flags, "timer",
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c0_compare_interrupt))
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pr_err("Failed to request irq %d (timer)\n", irq);
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return 0;
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@ -109,7 +109,7 @@ void __init mach_init_irq(void)
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/* setup north bridge irq (bonito) */
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if (request_irq(LOONGSON_NORTH_BRIDGE_IRQ, ip6_action,
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IRQF_SHARED | IRQF_NO_THREAD, "cascade", NULL))
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IRQF_SHARED | IRQF_NO_THREAD, "cascade", ip6_action))
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pr_err("Failed to register north bridge cascade interrupt\n");
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/* setup source bridge irq (i8259) */
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if (request_irq(LOONGSON_SOUTH_BRIDGE_IRQ, no_action,
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@ -81,7 +81,7 @@ unsigned int get_c0_compare_int(void)
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/* MIPS_MT modes may want timer for second VPE */
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if ((get_current_vpe()) && !tim_installed) {
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if (request_irq(MSP_INT_VPE1_TIMER, c0_compare_interrupt, flags,
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"timer", NULL))
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"timer", c0_compare_interrupt))
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pr_err("Failed to register timer interrupt\n");
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tim_installed++;
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}
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@ -222,8 +222,8 @@ void __init sni_a20r_irq_init(void)
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irq_set_chip_and_handler(i, &a20r_irq_type, handle_level_irq);
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sni_hwint = a20r_hwint;
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change_c0_status(ST0_IM, IE_IRQ0);
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if (request_irq(SNI_A20R_IRQ_BASE + 3, sni_isa_irq_handler,
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IRQF_SHARED, "ISA", NULL))
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if (request_irq(SNI_A20R_IRQ_BASE + 3, sni_isa_irq_handler, 0, "ISA",
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NULL))
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pr_err("Failed to register ISA interrupt\n");
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}
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@ -244,8 +244,8 @@ void __init sni_pcit_irq_init(void)
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*(volatile u32 *)SNI_PCIT_INT_REG = 0;
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sni_hwint = sni_pcit_hwint;
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change_c0_status(ST0_IM, IE_IRQ1);
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if (request_irq(SNI_PCIT_INT_START + 6, sni_isa_irq_handler,
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IRQF_SHARED, "ISA", NULL))
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if (request_irq(SNI_PCIT_INT_START + 6, sni_isa_irq_handler, 0, "ISA",
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NULL))
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pr_err("Failed to register ISA interrupt\n");
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}
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@ -259,8 +259,8 @@ void __init sni_pcit_cplus_irq_init(void)
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*(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
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sni_hwint = sni_pcit_hwint_cplus;
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change_c0_status(ST0_IM, IE_IRQ0);
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if (request_irq(MIPS_CPU_IRQ_BASE + 3, sni_isa_irq_handler,
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IRQF_SHARED, "ISA", NULL))
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if (request_irq(MIPS_CPU_IRQ_BASE + 3, sni_isa_irq_handler, 0, "ISA",
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NULL))
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pr_err("Failed to register ISA interrupt\n");
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}
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@ -473,10 +473,10 @@ void __init sni_rm200_irq_init(void)
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sni_hwint = sni_rm200_hwint;
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change_c0_status(ST0_IM, IE_IRQ0);
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if (request_irq(SNI_RM200_INT_START + 0, sni_rm200_i8259A_irq_handler,
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IRQF_SHARED, "onboard ISA", NULL))
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0, "onboard ISA", NULL))
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pr_err("Failed to register onboard ISA interrupt\n");
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if (request_irq(SNI_RM200_INT_START + 1, sni_isa_irq_handler,
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IRQF_SHARED, "ISA", NULL))
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if (request_irq(SNI_RM200_INT_START + 1, sni_isa_irq_handler, 0, "ISA",
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NULL))
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pr_err("Failed to register ISA interrupt\n");
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}
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