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drm/i915: Add initial selftests for hang detection and resets
Check that we can reset the GPU and continue executing from the next request. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170213171558.20942-47-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
parent
7db4dceafa
commit
496b575e3c
@ -3377,8 +3377,8 @@ int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
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int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
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void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
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void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
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int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
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unsigned int flags);
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int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
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unsigned int flags);
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int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
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void i915_gem_resume(struct drm_i915_private *dev_priv);
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int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
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@ -480,3 +480,7 @@ void intel_hangcheck_init(struct drm_i915_private *i915)
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INIT_DELAYED_WORK(&i915->gpu_error.hangcheck_work,
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i915_hangcheck_elapsed);
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}
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#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
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#include "selftests/intel_hangcheck.c"
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#endif
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@ -16,3 +16,4 @@ selftest(dmabuf, i915_gem_dmabuf_live_selftests)
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selftest(coherency, i915_gem_coherency_live_selftests)
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selftest(gtt, i915_gem_gtt_live_selftests)
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selftest(contexts, i915_gem_context_live_selftests)
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selftest(hangcheck, intel_hangcheck_live_selftests)
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537
drivers/gpu/drm/i915/selftests/intel_hangcheck.c
Normal file
537
drivers/gpu/drm/i915/selftests/intel_hangcheck.c
Normal file
@ -0,0 +1,537 @@
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/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "../i915_selftest.h"
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struct hang {
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struct drm_i915_private *i915;
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struct drm_i915_gem_object *hws;
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struct drm_i915_gem_object *obj;
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u32 *seqno;
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u32 *batch;
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};
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static int hang_init(struct hang *h, struct drm_i915_private *i915)
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{
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void *vaddr;
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int err;
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memset(h, 0, sizeof(*h));
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h->i915 = i915;
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h->hws = i915_gem_object_create_internal(i915, PAGE_SIZE);
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if (IS_ERR(h->hws))
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return PTR_ERR(h->hws);
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h->obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
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if (IS_ERR(h->obj)) {
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err = PTR_ERR(h->obj);
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goto err_hws;
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}
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i915_gem_object_set_cache_level(h->hws, I915_CACHE_LLC);
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vaddr = i915_gem_object_pin_map(h->hws, I915_MAP_WB);
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if (IS_ERR(vaddr)) {
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err = PTR_ERR(vaddr);
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goto err_obj;
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}
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h->seqno = memset(vaddr, 0xff, PAGE_SIZE);
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vaddr = i915_gem_object_pin_map(h->obj,
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HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC);
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if (IS_ERR(vaddr)) {
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err = PTR_ERR(vaddr);
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goto err_unpin_hws;
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}
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h->batch = vaddr;
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return 0;
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err_unpin_hws:
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i915_gem_object_unpin_map(h->hws);
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err_obj:
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i915_gem_object_put(h->obj);
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err_hws:
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i915_gem_object_put(h->hws);
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return err;
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}
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static u64 hws_address(const struct i915_vma *hws,
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const struct drm_i915_gem_request *rq)
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{
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return hws->node.start + offset_in_page(sizeof(u32)*rq->fence.context);
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}
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static int emit_recurse_batch(struct hang *h,
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struct drm_i915_gem_request *rq)
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{
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struct drm_i915_private *i915 = h->i915;
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struct i915_address_space *vm = rq->ctx->ppgtt ? &rq->ctx->ppgtt->base : &i915->ggtt.base;
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struct i915_vma *hws, *vma;
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unsigned int flags;
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u32 *batch;
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int err;
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vma = i915_vma_instance(h->obj, vm, NULL);
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if (IS_ERR(vma))
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return PTR_ERR(vma);
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hws = i915_vma_instance(h->hws, vm, NULL);
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if (IS_ERR(hws))
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return PTR_ERR(hws);
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err = i915_vma_pin(vma, 0, 0, PIN_USER);
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if (err)
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return err;
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err = i915_vma_pin(hws, 0, 0, PIN_USER);
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if (err)
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goto unpin_vma;
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err = rq->engine->emit_flush(rq, EMIT_INVALIDATE);
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if (err)
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goto unpin_hws;
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err = i915_switch_context(rq);
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if (err)
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goto unpin_hws;
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i915_vma_move_to_active(vma, rq, 0);
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if (!i915_gem_object_has_active_reference(vma->obj)) {
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i915_gem_object_get(vma->obj);
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i915_gem_object_set_active_reference(vma->obj);
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}
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i915_vma_move_to_active(hws, rq, 0);
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if (!i915_gem_object_has_active_reference(hws->obj)) {
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i915_gem_object_get(hws->obj);
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i915_gem_object_set_active_reference(hws->obj);
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}
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batch = h->batch;
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if (INTEL_GEN(i915) >= 8) {
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*batch++ = MI_STORE_DWORD_IMM_GEN4;
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*batch++ = lower_32_bits(hws_address(hws, rq));
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*batch++ = upper_32_bits(hws_address(hws, rq));
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*batch++ = rq->fence.seqno;
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*batch++ = MI_BATCH_BUFFER_START | 1 << 8 | 1;
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*batch++ = lower_32_bits(vma->node.start);
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*batch++ = upper_32_bits(vma->node.start);
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} else if (INTEL_GEN(i915) >= 6) {
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*batch++ = MI_STORE_DWORD_IMM_GEN4;
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*batch++ = 0;
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*batch++ = lower_32_bits(hws_address(hws, rq));
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*batch++ = rq->fence.seqno;
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*batch++ = MI_BATCH_BUFFER_START | 1 << 8;
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*batch++ = lower_32_bits(vma->node.start);
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} else if (INTEL_GEN(i915) >= 4) {
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*batch++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
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*batch++ = 0;
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*batch++ = lower_32_bits(hws_address(hws, rq));
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*batch++ = rq->fence.seqno;
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*batch++ = MI_BATCH_BUFFER_START | 2 << 6;
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*batch++ = lower_32_bits(vma->node.start);
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} else {
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*batch++ = MI_STORE_DWORD_IMM;
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*batch++ = lower_32_bits(hws_address(hws, rq));
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*batch++ = rq->fence.seqno;
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*batch++ = MI_BATCH_BUFFER_START | 2 << 6 | 1;
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*batch++ = lower_32_bits(vma->node.start);
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}
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*batch++ = MI_BATCH_BUFFER_END; /* not reached */
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flags = 0;
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if (INTEL_GEN(vm->i915) <= 5)
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flags |= I915_DISPATCH_SECURE;
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err = rq->engine->emit_bb_start(rq, vma->node.start, PAGE_SIZE, flags);
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unpin_hws:
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i915_vma_unpin(hws);
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unpin_vma:
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i915_vma_unpin(vma);
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return err;
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}
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static struct drm_i915_gem_request *
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hang_create_request(struct hang *h,
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struct intel_engine_cs *engine,
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struct i915_gem_context *ctx)
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{
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struct drm_i915_gem_request *rq;
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int err;
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if (i915_gem_object_is_active(h->obj)) {
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struct drm_i915_gem_object *obj;
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void *vaddr;
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obj = i915_gem_object_create_internal(h->i915, PAGE_SIZE);
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if (IS_ERR(obj))
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return ERR_CAST(obj);
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vaddr = i915_gem_object_pin_map(obj,
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HAS_LLC(h->i915) ? I915_MAP_WB : I915_MAP_WC);
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if (IS_ERR(vaddr)) {
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i915_gem_object_put(obj);
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return ERR_CAST(vaddr);
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}
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i915_gem_object_unpin_map(h->obj);
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i915_gem_object_put(h->obj);
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h->obj = obj;
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h->batch = vaddr;
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}
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rq = i915_gem_request_alloc(engine, ctx);
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if (IS_ERR(rq))
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return rq;
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err = emit_recurse_batch(h, rq);
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if (err) {
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__i915_add_request(rq, false);
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return ERR_PTR(err);
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}
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return rq;
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}
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static u32 hws_seqno(const struct hang *h,
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const struct drm_i915_gem_request *rq)
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{
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return READ_ONCE(h->seqno[rq->fence.context % (PAGE_SIZE/sizeof(u32))]);
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}
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static void hang_fini(struct hang *h)
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{
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*h->batch = MI_BATCH_BUFFER_END;
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wmb();
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i915_gem_object_unpin_map(h->obj);
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i915_gem_object_put(h->obj);
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i915_gem_object_unpin_map(h->hws);
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i915_gem_object_put(h->hws);
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i915_gem_wait_for_idle(h->i915, I915_WAIT_LOCKED);
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i915_gem_retire_requests(h->i915);
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}
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static int igt_hang_sanitycheck(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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struct drm_i915_gem_request *rq;
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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struct hang h;
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int err;
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/* Basic check that we can execute our hanging batch */
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if (!igt_can_mi_store_dword_imm(i915))
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return 0;
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mutex_lock(&i915->drm.struct_mutex);
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err = hang_init(&h, i915);
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if (err)
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goto unlock;
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for_each_engine(engine, i915, id) {
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long timeout;
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rq = hang_create_request(&h, engine, i915->kernel_context);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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pr_err("Failed to create request for %s, err=%d\n",
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engine->name, err);
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goto fini;
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}
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i915_gem_request_get(rq);
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*h.batch = MI_BATCH_BUFFER_END;
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__i915_add_request(rq, true);
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timeout = i915_wait_request(rq,
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I915_WAIT_LOCKED,
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MAX_SCHEDULE_TIMEOUT);
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i915_gem_request_put(rq);
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if (timeout < 0) {
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err = timeout;
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pr_err("Wait for request failed on %s, err=%d\n",
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engine->name, err);
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goto fini;
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}
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}
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fini:
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hang_fini(&h);
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unlock:
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mutex_unlock(&i915->drm.struct_mutex);
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return err;
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}
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static int igt_global_reset(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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unsigned int reset_count;
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int err = 0;
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/* Check that we can issue a global GPU reset */
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set_bit(I915_RESET_IN_PROGRESS, &i915->gpu_error.flags);
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mutex_lock(&i915->drm.struct_mutex);
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reset_count = i915_reset_count(&i915->gpu_error);
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i915_reset(i915);
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if (i915_reset_count(&i915->gpu_error) == reset_count) {
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pr_err("No GPU reset recorded!\n");
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err = -EINVAL;
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}
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mutex_unlock(&i915->drm.struct_mutex);
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GEM_BUG_ON(test_bit(I915_RESET_IN_PROGRESS, &i915->gpu_error.flags));
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if (i915_terminally_wedged(&i915->gpu_error))
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err = -EIO;
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return err;
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}
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static u32 fake_hangcheck(struct drm_i915_gem_request *rq)
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{
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u32 reset_count;
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rq->engine->hangcheck.stalled = true;
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rq->engine->hangcheck.seqno = intel_engine_get_seqno(rq->engine);
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reset_count = i915_reset_count(&rq->i915->gpu_error);
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set_bit(I915_RESET_IN_PROGRESS, &rq->i915->gpu_error.flags);
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wake_up_all(&rq->i915->gpu_error.wait_queue);
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return reset_count;
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}
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static bool wait_for_hang(struct hang *h, struct drm_i915_gem_request *rq)
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{
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return !(wait_for_us(i915_seqno_passed(hws_seqno(h, rq),
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rq->fence.seqno),
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10) &&
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wait_for(i915_seqno_passed(hws_seqno(h, rq),
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rq->fence.seqno),
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1000));
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}
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static int igt_wait_reset(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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struct drm_i915_gem_request *rq;
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unsigned int reset_count;
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struct hang h;
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long timeout;
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int err;
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/* Check that we detect a stuck waiter and issue a reset */
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set_bit(I915_RESET_IN_PROGRESS, &i915->gpu_error.flags);
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mutex_lock(&i915->drm.struct_mutex);
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err = hang_init(&h, i915);
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if (err)
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goto unlock;
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rq = hang_create_request(&h, i915->engine[RCS], i915->kernel_context);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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goto fini;
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}
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i915_gem_request_get(rq);
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__i915_add_request(rq, true);
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if (!wait_for_hang(&h, rq)) {
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pr_err("Failed to start request %x\n", rq->fence.seqno);
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err = -EIO;
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goto out_rq;
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}
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reset_count = fake_hangcheck(rq);
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timeout = i915_wait_request(rq, I915_WAIT_LOCKED, 10);
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if (timeout < 0) {
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pr_err("i915_wait_request failed on a stuck request: err=%ld\n",
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timeout);
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err = timeout;
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goto out_rq;
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}
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GEM_BUG_ON(test_bit(I915_RESET_IN_PROGRESS, &i915->gpu_error.flags));
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if (i915_reset_count(&i915->gpu_error) == reset_count) {
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pr_err("No GPU reset recorded!\n");
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err = -EINVAL;
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goto out_rq;
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}
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out_rq:
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i915_gem_request_put(rq);
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fini:
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hang_fini(&h);
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unlock:
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mutex_unlock(&i915->drm.struct_mutex);
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if (i915_terminally_wedged(&i915->gpu_error))
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return -EIO;
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return err;
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}
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static int igt_reset_queue(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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struct hang h;
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int err;
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/* Check that we replay pending requests following a hang */
|
||||
|
||||
if (!igt_can_mi_store_dword_imm(i915))
|
||||
return 0;
|
||||
|
||||
mutex_lock(&i915->drm.struct_mutex);
|
||||
err = hang_init(&h, i915);
|
||||
if (err)
|
||||
goto unlock;
|
||||
|
||||
for_each_engine(engine, i915, id) {
|
||||
struct drm_i915_gem_request *prev;
|
||||
IGT_TIMEOUT(end_time);
|
||||
unsigned int count;
|
||||
|
||||
prev = hang_create_request(&h, engine, i915->kernel_context);
|
||||
if (IS_ERR(prev)) {
|
||||
err = PTR_ERR(prev);
|
||||
goto fini;
|
||||
}
|
||||
|
||||
i915_gem_request_get(prev);
|
||||
__i915_add_request(prev, true);
|
||||
|
||||
count = 0;
|
||||
do {
|
||||
struct drm_i915_gem_request *rq;
|
||||
unsigned int reset_count;
|
||||
|
||||
rq = hang_create_request(&h,
|
||||
engine,
|
||||
i915->kernel_context);
|
||||
if (IS_ERR(rq)) {
|
||||
err = PTR_ERR(rq);
|
||||
goto fini;
|
||||
}
|
||||
|
||||
i915_gem_request_get(rq);
|
||||
__i915_add_request(rq, true);
|
||||
|
||||
if (!wait_for_hang(&h, prev)) {
|
||||
pr_err("Failed to start request %x\n",
|
||||
prev->fence.seqno);
|
||||
i915_gem_request_put(rq);
|
||||
i915_gem_request_put(prev);
|
||||
err = -EIO;
|
||||
goto fini;
|
||||
}
|
||||
|
||||
reset_count = fake_hangcheck(prev);
|
||||
|
||||
i915_reset(i915);
|
||||
|
||||
GEM_BUG_ON(test_bit(I915_RESET_IN_PROGRESS,
|
||||
&i915->gpu_error.flags));
|
||||
if (prev->fence.error != -EIO) {
|
||||
pr_err("GPU reset not recorded on hanging request [fence.error=%d]!\n",
|
||||
prev->fence.error);
|
||||
i915_gem_request_put(rq);
|
||||
i915_gem_request_put(prev);
|
||||
err = -EINVAL;
|
||||
goto fini;
|
||||
}
|
||||
|
||||
if (rq->fence.error) {
|
||||
pr_err("Fence error status not zero [%d] after unrelated reset\n",
|
||||
rq->fence.error);
|
||||
i915_gem_request_put(rq);
|
||||
i915_gem_request_put(prev);
|
||||
err = -EINVAL;
|
||||
goto fini;
|
||||
}
|
||||
|
||||
if (i915_reset_count(&i915->gpu_error) == reset_count) {
|
||||
pr_err("No GPU reset recorded!\n");
|
||||
i915_gem_request_put(rq);
|
||||
i915_gem_request_put(prev);
|
||||
err = -EINVAL;
|
||||
goto fini;
|
||||
}
|
||||
|
||||
i915_gem_request_put(prev);
|
||||
prev = rq;
|
||||
count++;
|
||||
} while (time_before(jiffies, end_time));
|
||||
pr_info("%s: Completed %d resets\n", engine->name, count);
|
||||
|
||||
*h.batch = MI_BATCH_BUFFER_END;
|
||||
wmb();
|
||||
|
||||
i915_gem_request_put(prev);
|
||||
}
|
||||
|
||||
fini:
|
||||
hang_fini(&h);
|
||||
unlock:
|
||||
mutex_unlock(&i915->drm.struct_mutex);
|
||||
|
||||
if (i915_terminally_wedged(&i915->gpu_error))
|
||||
return -EIO;
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
int intel_hangcheck_live_selftests(struct drm_i915_private *i915)
|
||||
{
|
||||
static const struct i915_subtest tests[] = {
|
||||
SUBTEST(igt_hang_sanitycheck),
|
||||
SUBTEST(igt_global_reset),
|
||||
SUBTEST(igt_wait_reset),
|
||||
SUBTEST(igt_reset_queue),
|
||||
};
|
||||
|
||||
if (!intel_has_gpu_reset(i915))
|
||||
return 0;
|
||||
|
||||
return i915_subtests(tests, i915);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user