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arm64: dts: qcom: sc8180x: Add display and gpu nodes

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This patch adds gpu, gmu, gpucc, dispcc and finally the mdss node with
dsi0/1, dp0/1 and edp subnodes as found in this SoC

Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230530162454.51708-13-vkoul@kernel.org
This commit is contained in:
Vinod Koul 2023-05-30 21:54:51 +05:30 committed by Bjorn Andersson
parent b080f53a8f
commit 494dec9b6f
1 changed files with 658 additions and 0 deletions
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658
arch/arm64/boot/dts/qcom/sc8180x.dtsi
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@ -4,7 +4,9 @@
* Copyright (c) 2020-2023, Linaro Limited
*/
#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
#include <dt-bindings/clock/qcom,gcc-sc8180x.h>
#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc8180x.h>
@ -2190,6 +2192,123 @@
#hwlock-cells = <1>;
};
gpu: gpu@2c00000 {
compatible = "qcom,adreno-680.1", "qcom,adreno";
#stream-id-cells = <16>;
reg = <0 0x02c00000 0 0x40000>;
reg-names = "kgsl_3d0_reg_memory";
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&adreno_smmu 0 0xc01>;
operating-points-v2 = <&gpu_opp_table>;
interconnects = <&gem_noc MASTER_GRAPHICS_3D 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "gfx-mem";
qcom,gmu = <&gmu>;
status = "disabled";
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-514000000 {
opp-hz = /bits/ 64 <514000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
};
opp-461000000 {
opp-hz = /bits/ 64 <461000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
};
opp-405000000 {
opp-hz = /bits/ 64 <405000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
};
opp-315000000 {
opp-hz = /bits/ 64 <315000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
};
opp-256000000 {
opp-hz = /bits/ 64 <256000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
};
opp-177000000 {
opp-hz = /bits/ 64 <177000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
};
};
};
gmu: gmu@2c6a000 {
compatible="qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
reg = <0 0x02c6a000 0 0x30000>,
<0 0x0b290000 0 0x10000>,
<0 0x0b490000 0 0x10000>;
reg-names = "gmu",
"gmu_pdc",
"gmu_pdc_seq";
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hfi", "gmu";
clocks = <&gpucc GPU_CC_AHB_CLK>,
<&gpucc GPU_CC_CX_GMU_CLK>,
<&gpucc GPU_CC_CXO_CLK>,
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
power-domains = <&gpucc GPU_CX_GDSC>,
<&gpucc GPU_GX_GDSC>;
power-domain-names = "cx", "gx";
iommus = <&adreno_smmu 5 0xc00>;
operating-points-v2 = <&gmu_opp_table>;
gmu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
};
};
};
gpucc: clock-controller@2c90000 {
compatible = "qcom,sc8180x-gpucc";
reg = <0 0x02c90000 0 0x9000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
clock-names = "bi_tcxo",
"gcc_gpu_gpll0_clk_src",
"gcc_gpu_gpll0_div_clk_src";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
adreno_smmu: iommu@2ca0000 {
compatible = "qcom,sc8180x-smmu-500", "arm,mmu-500";
reg = <0 0x02ca0000 0 0x10000>;
@ -2539,6 +2658,545 @@
};
};
mdss: mdss@ae00000 {
compatible = "qcom,sc8180x-mdss";
reg = <0 0x0ae00000 0 0x1000>;
reg-names = "mdss";
power-domains = <&dispcc MDSS_GDSC>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&gcc GCC_DISP_SF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface",
"bus",
"nrt_bus",
"core";
resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>;
interconnect-names = "mdp0-mem", "mdp1-mem";
iommus = <&apps_smmu 0x800 0x420>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
mdss_mdp: mdp@ae01000 {
compatible = "qcom,sc8180x-dpu";
reg = <0 0x0ae01000 0 0x8f000>,
<0 0x0aeb0000 0 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "iface",
"bus",
"core",
"vsync";
assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
assigned-clock-rates = <460000000>,
<19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SC8180X_MMCX>;
interrupt-parent = <&mdss>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf0_out: endpoint {
remote-endpoint = <&dp0_in>;
};
};
port@1 {
reg = <1>;
dpu_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@2 {
reg = <2>;
dpu_intf2_out: endpoint {
remote-endpoint = <&dsi1_in>;
};
};
port@4 {
reg = <4>;
dpu_intf4_out: endpoint {
remote-endpoint = <&dp1_in>;
};
};
port@5 {
reg = <5>;
dpu_intf5_out: endpoint {
remote-endpoint = <&edp_in>;
};
};
};
mdp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-345000000 {
opp-hz = /bits/ 64 <345000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-460000000 {
opp-hz = /bits/ 64 <460000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
dsi0: dsi@ae94000 {
compatible = "qcom,mdss-dsi-ctrl";
reg = <0 0x0ae94000 0 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SC8180X_MMCX>;
phys = <&dsi0_phy>;
phy-names = "dsi";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
};
};
};
dsi_opp_table: opp-table {
compatible = "operating-points-v2";
opp-187500000 {
opp-hz = /bits/ 64 <187500000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-358000000 {
opp-hz = /bits/ 64 <358000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
};
dsi0_phy: dsi-phy@ae94400 {
compatible = "qcom,dsi-phy-7nm";
reg = <0 0x0ae94400 0 0x200>,
<0 0x0ae94600 0 0x280>,
<0 0x0ae94900 0 0x260>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "ref";
status = "disabled";
};
dsi1: dsi@ae96000 {
compatible = "qcom,mdss-dsi-ctrl";
reg = <0 0x0ae96000 0 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
<&dispcc DISP_CC_MDSS_ESC1_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SC8180X_MMCX>;
phys = <&dsi1_phy>;
phy-names = "dsi";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi1_in: endpoint {
remote-endpoint = <&dpu_intf2_out>;
};
};
port@1 {
reg = <1>;
dsi1_out: endpoint {
};
};
};
};
dsi1_phy: dsi-phy@ae96400 {
compatible = "qcom,dsi-phy-7nm";
reg = <0 0x0ae96400 0 0x200>,
<0 0x0ae96600 0 0x280>,
<0 0x0ae96900 0 0x260>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "ref";
status = "disabled";
};
mdss_dp0: displayport-controller@ae90000 {
compatible = "qcom,sc8180x-dp";
reg = <0 0xae90000 0 0x200>,
<0 0xae90200 0 0x200>,
<0 0xae90400 0 0x600>,
<0 0xae90a00 0 0x400>;
interrupt-parent = <&mdss>;
interrupts = <12>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
assigned-clock-parents = <&usb_prim_dpphy 0>, <&usb_prim_dpphy 1>;
phys = <&usb_prim_dpphy>;
phy-names = "dp";
#sound-dai-cells = <0>;
operating-points-v2 = <&dp0_opp_table>;
power-domains = <&rpmhpd SC8180X_CX>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dp0_in: endpoint {
remote-endpoint = <&dpu_intf0_out>;
};
};
port@1 {
reg = <1>;
};
};
dp0_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-270000000 {
opp-hz = /bits/ 64 <270000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-540000000 {
opp-hz = /bits/ 64 <540000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-810000000 {
opp-hz = /bits/ 64 <810000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
mdss_dp1: displayport-controller@ae98000 {
compatible = "qcom,sc8180x-dp";
reg = <0 0xae98000 0 0x200>,
<0 0xae98200 0 0x200>,
<0 0xae98400 0 0x600>,
<0 0xae98a00 0 0x400>;
interrupt-parent = <&mdss>;
interrupts = <13>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_DP_AUX1_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK1_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK1_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK1_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL2_CLK_SRC>;
assigned-clock-parents = <&usb_sec_dpphy 0>, <&usb_sec_dpphy 1>;
phys = <&usb_sec_dpphy>;
phy-names = "dp";
#sound-dai-cells = <0>;
operating-points-v2 = <&dp0_opp_table>;
power-domains = <&rpmhpd SC8180X_CX>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dp1_in: endpoint {
remote-endpoint = <&dpu_intf4_out>;
};
};
port@1 {
reg = <1>;
};
};
dp1_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-270000000 {
opp-hz = /bits/ 64 <270000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-540000000 {
opp-hz = /bits/ 64 <540000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-810000000 {
opp-hz = /bits/ 64 <810000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
mdss_edp: displayport-controller@ae9a000 {
compatible = "qcom,sc8180x-edp";
reg = <0 0xae9a000 0 0x200>,
<0 0xae9a200 0 0x200>,
<0 0xae9a400 0 0x600>,
<0 0xae9aa00 0 0x400>;
interrupt-parent = <&mdss>;
interrupts = <14>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
assigned-clock-parents = <&edp_phy 0>, <&edp_phy 1>;
phys = <&edp_phy>;
phy-names = "dp";
#sound-dai-cells = <0>;
operating-points-v2 = <&edp_opp_table>;
power-domains = <&rpmhpd SC8180X_CX>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
edp_in: endpoint {
remote-endpoint = <&dpu_intf5_out>;
};
};
};
edp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-270000000 {
opp-hz = /bits/ 64 <270000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-540000000 {
opp-hz = /bits/ 64 <540000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-810000000 {
opp-hz = /bits/ 64 <810000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
};
edp_phy: phy@aec2a00 {
compatible = "qcom,sc8180x-edp-phy";
reg = <0 0x0aec2a00 0 0x1c0>,
<0 0x0aec2200 0 0xa0>,
<0 0x0aec2600 0 0xa0>,
<0 0x0aec2000 0 0x19c>;
clocks = <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>;
clock-names = "aux", "cfg_ahb";
power-domains = <&dispcc MDSS_GDSC>;
#clock-cells = <1>;
#phy-cells = <0>;
};
dispcc: clock-controller@af00000 {
compatible = "qcom,sc8180x-dispcc";
reg = <0 0x0af00000 0 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
<&usb_prim_dpphy 0>,
<&usb_prim_dpphy 1>,
<&usb_sec_dpphy 0>,
<&usb_sec_dpphy 1>,
<&edp_phy 0>,
<&edp_phy 1>;
clock-names = "bi_tcxo",
"sleep_clk",
"dp_phy_pll_link_clk",
"dp_phy_pll_vco_div_clk",
"dptx1_phy_pll_link_clk",
"dptx1_phy_pll_vco_div_clk",
"edp_phy_pll_link_clk",
"edp_phy_pll_vco_div_clk";
power-domains = <&rpmhpd SC8180X_MMCX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc8180x-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>;