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drm/i915/lrc: allocate separate page for HWSP
On gen8+ we're currently using the PPHWSP of the kernel ctx as the global HWSP. However, when the kernel ctx gets submitted (e.g. from __intel_autoenable_gt_powersave) the HW will use that page as both HWSP and PPHWSP. This causes a conflict in the register arena of the HWSP, i.e. dword indices below 0x30. We don't current utilize this arena, but in the following patches we will take advantage of the cached register state for handling execlist's context status interrupt. To avoid the conflict, instead of re-using the PPHWSP of the kernel ctx we can allocate a separate page for the HWSP like what happens for pre-execlists platform. v2: Add a use-case for the register arena of the HWSP. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Michel Thierry <michel.thierry@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1499357440-34688-1-git-send-email-daniele.ceraolospurio@intel.com Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Michel Thierry <michel.thierry@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20170913085605.18299-3-chris@chris-wilson.co.uk
This commit is contained in:
Daniele Ceraolo Spurio
Chris Wilson
parent
a922c0c7a6
commit
486e93f72a
@ -442,6 +442,114 @@ static void intel_engine_cleanup_scratch(struct intel_engine_cs *engine)
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i915_vma_unpin_and_release(&engine->scratch);
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}
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static void cleanup_phys_status_page(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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if (!dev_priv->status_page_dmah)
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return;
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drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah);
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engine->status_page.page_addr = NULL;
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}
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static void cleanup_status_page(struct intel_engine_cs *engine)
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{
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struct i915_vma *vma;
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struct drm_i915_gem_object *obj;
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vma = fetch_and_zero(&engine->status_page.vma);
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if (!vma)
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return;
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obj = vma->obj;
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i915_vma_unpin(vma);
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i915_vma_close(vma);
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i915_gem_object_unpin_map(obj);
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__i915_gem_object_release_unless_active(obj);
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}
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static int init_status_page(struct intel_engine_cs *engine)
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{
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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unsigned int flags;
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void *vaddr;
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int ret;
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obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
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if (IS_ERR(obj)) {
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DRM_ERROR("Failed to allocate status page\n");
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return PTR_ERR(obj);
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}
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ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
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if (ret)
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goto err;
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vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
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if (IS_ERR(vma)) {
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ret = PTR_ERR(vma);
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goto err;
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}
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flags = PIN_GLOBAL;
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if (!HAS_LLC(engine->i915))
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/* On g33, we cannot place HWS above 256MiB, so
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* restrict its pinning to the low mappable arena.
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* Though this restriction is not documented for
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* gen4, gen5, or byt, they also behave similarly
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* and hang if the HWS is placed at the top of the
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* GTT. To generalise, it appears that all !llc
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* platforms have issues with us placing the HWS
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* above the mappable region (even though we never
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* actually map it).
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*/
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flags |= PIN_MAPPABLE;
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ret = i915_vma_pin(vma, 0, 4096, flags);
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if (ret)
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goto err;
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vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
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if (IS_ERR(vaddr)) {
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ret = PTR_ERR(vaddr);
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goto err_unpin;
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}
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engine->status_page.vma = vma;
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engine->status_page.ggtt_offset = i915_ggtt_offset(vma);
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engine->status_page.page_addr = memset(vaddr, 0, PAGE_SIZE);
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DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
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engine->name, i915_ggtt_offset(vma));
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return 0;
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err_unpin:
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i915_vma_unpin(vma);
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err:
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i915_gem_object_put(obj);
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return ret;
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}
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static int init_phys_status_page(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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GEM_BUG_ON(engine->id != RCS);
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dev_priv->status_page_dmah =
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drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE);
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if (!dev_priv->status_page_dmah)
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return -ENOMEM;
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engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
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memset(engine->status_page.page_addr, 0, PAGE_SIZE);
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return 0;
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}
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/**
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* intel_engines_init_common - initialize cengine state which might require hw access
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* @engine: Engine to initialize.
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@ -477,10 +585,21 @@ int intel_engine_init_common(struct intel_engine_cs *engine)
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ret = i915_gem_render_state_init(engine);
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if (ret)
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goto err_unpin;
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goto err_breadcrumbs;
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if (HWS_NEEDS_PHYSICAL(engine->i915))
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ret = init_phys_status_page(engine);
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else
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ret = init_status_page(engine);
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if (ret)
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goto err_rs_fini;
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return 0;
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err_rs_fini:
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i915_gem_render_state_fini(engine);
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err_breadcrumbs:
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intel_engine_fini_breadcrumbs(engine);
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err_unpin:
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engine->context_unpin(engine, engine->i915->kernel_context);
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return ret;
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@ -497,6 +616,11 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
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{
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intel_engine_cleanup_scratch(engine);
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if (HWS_NEEDS_PHYSICAL(engine->i915))
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cleanup_phys_status_page(engine);
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else
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cleanup_status_page(engine);
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i915_gem_render_state_fini(engine);
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intel_engine_fini_breadcrumbs(engine);
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intel_engine_cleanup_cmd_parser(engine);
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@ -1674,11 +1674,6 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
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if (engine->cleanup)
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engine->cleanup(engine);
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if (engine->status_page.vma) {
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i915_gem_object_unpin_map(engine->status_page.vma->obj);
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engine->status_page.vma = NULL;
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}
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intel_engine_cleanup_common(engine);
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lrc_destroy_wa_ctx(engine);
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@ -1725,24 +1720,6 @@ logical_ring_default_irqs(struct intel_engine_cs *engine)
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engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
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}
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static int
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lrc_setup_hws(struct intel_engine_cs *engine, struct i915_vma *vma)
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{
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const int hws_offset = LRC_PPHWSP_PN * PAGE_SIZE;
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void *hws;
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/* The HWSP is part of the default context object in LRC mode. */
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hws = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
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if (IS_ERR(hws))
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return PTR_ERR(hws);
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engine->status_page.page_addr = hws + hws_offset;
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engine->status_page.ggtt_offset = i915_ggtt_offset(vma) + hws_offset;
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engine->status_page.vma = vma;
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return 0;
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}
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static void
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logical_ring_setup(struct intel_engine_cs *engine)
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{
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@ -1775,23 +1752,14 @@ logical_ring_setup(struct intel_engine_cs *engine)
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logical_ring_default_irqs(engine);
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}
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static int
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logical_ring_init(struct intel_engine_cs *engine)
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static int logical_ring_init(struct intel_engine_cs *engine)
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{
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struct i915_gem_context *dctx = engine->i915->kernel_context;
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int ret;
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ret = intel_engine_init_common(engine);
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if (ret)
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goto error;
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/* And setup the hardware status page. */
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ret = lrc_setup_hws(engine, dctx->engine[engine->id].state);
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if (ret) {
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DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret);
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goto error;
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}
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return 0;
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error:
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@ -1175,113 +1175,7 @@ i915_emit_bb_start(struct drm_i915_gem_request *req,
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return 0;
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}
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static void cleanup_phys_status_page(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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if (!dev_priv->status_page_dmah)
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return;
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drm_pci_free(&dev_priv->drm, dev_priv->status_page_dmah);
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engine->status_page.page_addr = NULL;
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}
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static void cleanup_status_page(struct intel_engine_cs *engine)
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{
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struct i915_vma *vma;
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struct drm_i915_gem_object *obj;
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vma = fetch_and_zero(&engine->status_page.vma);
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if (!vma)
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return;
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obj = vma->obj;
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i915_vma_unpin(vma);
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i915_vma_close(vma);
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i915_gem_object_unpin_map(obj);
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__i915_gem_object_release_unless_active(obj);
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}
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static int init_status_page(struct intel_engine_cs *engine)
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{
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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unsigned int flags;
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void *vaddr;
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int ret;
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obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
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if (IS_ERR(obj)) {
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DRM_ERROR("Failed to allocate status page\n");
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return PTR_ERR(obj);
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}
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ret = i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
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if (ret)
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goto err;
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vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
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if (IS_ERR(vma)) {
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ret = PTR_ERR(vma);
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goto err;
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}
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flags = PIN_GLOBAL;
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if (!HAS_LLC(engine->i915))
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/* On g33, we cannot place HWS above 256MiB, so
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* restrict its pinning to the low mappable arena.
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* Though this restriction is not documented for
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* gen4, gen5, or byt, they also behave similarly
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* and hang if the HWS is placed at the top of the
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* GTT. To generalise, it appears that all !llc
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* platforms have issues with us placing the HWS
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* above the mappable region (even though we never
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* actualy map it).
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*/
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flags |= PIN_MAPPABLE;
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ret = i915_vma_pin(vma, 0, 4096, flags);
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if (ret)
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goto err;
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vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
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if (IS_ERR(vaddr)) {
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ret = PTR_ERR(vaddr);
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goto err_unpin;
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}
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engine->status_page.vma = vma;
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engine->status_page.ggtt_offset = i915_ggtt_offset(vma);
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engine->status_page.page_addr = memset(vaddr, 0, PAGE_SIZE);
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DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
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engine->name, i915_ggtt_offset(vma));
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return 0;
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err_unpin:
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i915_vma_unpin(vma);
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err:
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i915_gem_object_put(obj);
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return ret;
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}
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static int init_phys_status_page(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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GEM_BUG_ON(engine->id != RCS);
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dev_priv->status_page_dmah =
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drm_pci_alloc(&dev_priv->drm, PAGE_SIZE, PAGE_SIZE);
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if (!dev_priv->status_page_dmah)
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return -ENOMEM;
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engine->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
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memset(engine->status_page.page_addr, 0, PAGE_SIZE);
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return 0;
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}
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int intel_ring_pin(struct intel_ring *ring,
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struct drm_i915_private *i915,
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@ -1568,17 +1462,10 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
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if (err)
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goto err;
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if (HWS_NEEDS_PHYSICAL(engine->i915))
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err = init_phys_status_page(engine);
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else
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err = init_status_page(engine);
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if (err)
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goto err;
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ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE);
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if (IS_ERR(ring)) {
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err = PTR_ERR(ring);
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goto err_hws;
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goto err;
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}
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/* Ring wraparound at offset 0 sometimes hangs. No idea why. */
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@ -1593,11 +1480,6 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
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err_ring:
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intel_ring_free(ring);
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err_hws:
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if (HWS_NEEDS_PHYSICAL(engine->i915))
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cleanup_phys_status_page(engine);
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else
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cleanup_status_page(engine);
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err:
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intel_engine_cleanup_common(engine);
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return err;
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@ -1616,11 +1498,6 @@ void intel_engine_cleanup(struct intel_engine_cs *engine)
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if (engine->cleanup)
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engine->cleanup(engine);
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if (HWS_NEEDS_PHYSICAL(dev_priv))
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cleanup_phys_status_page(engine);
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else
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cleanup_status_page(engine);
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intel_engine_cleanup_common(engine);
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dev_priv->engine[engine->id] = NULL;
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