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arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC
The Arria 10 is latest SOC+FPGA from the Altera SOCFPGA platform. The Arria10 SOC shares some similarities with the SOCFPGA Cyclone5 and Arria5, but there are enough differences to warrant a new base dtsi. The differences are: * 3 EMAC controllers * 5 I2C controllers * 3 SPI controllers * 1.5 GHZ dual A9s * Support for DDR4 Besides the usual memory map and IRQ changes, the clock framework will be different, so this patch just adds the fixed-clocks. Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
This commit is contained in:
Dinh Nguyen
parent
c1ad85d772
commit
475dc86d08
@ -397,6 +397,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
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r8a7779-marzen.dtb \
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r8a7794-alt.dtb
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dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
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socfpga_arria10_socdk.dtb \
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socfpga_cyclone5_socdk.dtb \
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socfpga_cyclone5_sockit.dtb \
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socfpga_cyclone5_socrates.dtb \
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374
arch/arm/boot/dts/socfpga_arria10.dtsi
Normal file
374
arch/arm/boot/dts/socfpga_arria10.dtsi
Normal file
@ -0,0 +1,374 @@
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/*
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* Copyright Altera Corporation (C) 2014. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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ethernet2 = &gmac2;
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serial0 = &uart0;
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serial1 = &uart1;
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timer0 = &timer0;
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timer1 = &timer1;
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timer2 = &timer2;
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timer3 = &timer3;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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};
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intc: intc@ffffd000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xffffd000 0x1000>,
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<0xffffc100 0x100>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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device_type = "soc";
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interrupt-parent = <&intc>;
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ranges;
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amba {
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compatible = "arm,amba-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pdma: pdma@ffda1000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xffda1000 0x1000>;
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interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
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<0 84 IRQ_TYPE_LEVEL_HIGH>,
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<0 85 IRQ_TYPE_LEVEL_HIGH>,
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<0 86 IRQ_TYPE_LEVEL_HIGH>,
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<0 87 IRQ_TYPE_LEVEL_HIGH>,
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<0 88 IRQ_TYPE_LEVEL_HIGH>,
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<0 89 IRQ_TYPE_LEVEL_HIGH>,
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<0 90 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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};
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};
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clkmgr@ffd04000 {
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compatible = "altr,clk-mgr";
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reg = <0xffd04000 0x1000>;
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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osc1: osc1 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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main_pll: main_pll {
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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compatible = "altr,socfpga-pll-clock";
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clocks = <&osc1>;
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};
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periph_pll: periph_pll {
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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compatible = "altr,socfpga-pll-clock";
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clocks = <&osc1>;
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};
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};
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};
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gmac0: ethernet@ff800000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
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reg = <0xff800000 0x2000>;
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interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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/* Filled in by bootloader */
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mac-address = [00 00 00 00 00 00];
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status = "disabled";
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};
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gmac1: ethernet@ff802000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
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reg = <0xff802000 0x2000>;
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interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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/* Filled in by bootloader */
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mac-address = [00 00 00 00 00 00];
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status = "disabled";
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};
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gmac2: ethernet@ff804000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
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reg = <0xff804000 0x2000>;
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interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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/* Filled in by bootloader */
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mac-address = [00 00 00 00 00 00];
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status = "disabled";
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};
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gpio0: gpio@ffc02900 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0xffc02900 0x100>;
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status = "disabled";
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porta: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <29>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio1: gpio@ffc02a00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0xffc02a00 0x100>;
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status = "disabled";
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portb: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <29>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio2: gpio@ffc02b00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dw-apb-gpio";
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reg = <0xffc02b00 0x100>;
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status = "disabled";
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portc: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <27>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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i2c0: i2c@ffc02200 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc02200 0x100>;
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interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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i2c1: i2c@ffc02300 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc02300 0x100>;
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interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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i2c2: i2c@ffc02400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc02400 0x100>;
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interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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i2c3: i2c@ffc02500 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc02500 0x100>;
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interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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i2c4: i2c@ffc02600 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,designware-i2c";
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reg = <0xffc02600 0x100>;
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interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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L2: l2-cache@fffff000 {
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compatible = "arm,pl310-cache";
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reg = <0xfffff000 0x1000>;
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interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
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cache-unified;
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cache-level = <2>;
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};
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mmc: dwmmc0@ff808000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "altr,socfpga-dw-mshc";
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reg = <0xff808000 0x1000>;
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interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
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fifo-depth = <0x400>;
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};
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ocram: sram@ffe00000 {
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compatible = "mmio-sram";
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reg = <0xffe00000 0x40000>;
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};
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rst: rstmgr@ffd05000 {
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#reset-cells = <1>;
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compatible = "altr,rst-mgr";
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reg = <0xffd05000 0x100>;
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};
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sysmgr: sysmgr@ffd06000 {
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compatible = "altr,sys-mgr", "syscon";
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reg = <0xffd06000 0x300>;
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};
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/* Local timer */
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timer@ffffc600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xffffc600 0x100>;
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interrupts = <1 13 0xf04>;
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};
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timer0: timer0@ffc02700 {
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compatible = "snps,dw-apb-timer";
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interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xffc02700 0x100>;
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};
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timer1: timer1@ffc02800 {
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compatible = "snps,dw-apb-timer";
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interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xffc02800 0x100>;
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};
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timer2: timer2@ffd00000 {
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compatible = "snps,dw-apb-timer";
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interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xffd00000 0x100>;
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};
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timer3: timer3@ffd00100 {
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compatible = "snps,dw-apb-timer";
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interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xffd01000 0x100>;
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};
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uart0: serial0@ffc02000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xffc02000 0x100>;
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interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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uart1: serial1@ffc02100 {
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compatible = "snps,dw-apb-uart";
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reg = <0xffc02100 0x100>;
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interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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usbphy0: usbphy@0 {
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#phy-cells = <0>;
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compatible = "usb-nop-xceiv";
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status = "okay";
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};
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usb0: usb@ffb00000 {
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compatible = "snps,dwc2";
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reg = <0xffb00000 0xffff>;
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interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&usbphy0>;
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phy-names = "usb2-phy";
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status = "disabled";
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};
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usb1: usb@ffb40000 {
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compatible = "snps,dwc2";
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reg = <0xffb40000 0xffff>;
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interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&usbphy0>;
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phy-names = "usb2-phy";
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status = "disabled";
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};
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watchdog0: watchdog@ffd00200 {
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compatible = "snps,dw-wdt";
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reg = <0xffd00200 0x100>;
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interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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watchdog1: watchdog@ffd00300 {
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compatible = "snps,dw-wdt";
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reg = <0xffd00300 0x100>;
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interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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};
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48
arch/arm/boot/dts/socfpga_arria10_socdk.dts
Executable file
48
arch/arm/boot/dts/socfpga_arria10_socdk.dts
Executable file
@ -0,0 +1,48 @@
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/*
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* Copyright (C) 2014 Altera Corporation <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/dts-v1/;
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#include "socfpga_arria10.dtsi"
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/ {
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model = "Altera SOCFPGA Arria 10";
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compatible = "altr,socfpga-arria10", "altr,socfpga";
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chosen {
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bootargs = "console=ttyS0,115200 rootwait";
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};
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memory {
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name = "memory";
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device_type = "memory";
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reg = <0x0 0x40000000>; /* 1GB */
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};
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soc {
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clkmgr@ffd04000 {
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clocks {
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osc1 {
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clock-frequency = <25000000>;
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};
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};
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};
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serial0@ffc02000 {
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status = "okay";
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};
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};
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};
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