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drm/amd/display: Do not set drr on pipe commit
[WHY] Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a pipe commit can cause underflow. [HOW] Move DMUB p-state delegate into optimze_bandwidth; enabling FAMS sets optimized_required. This change expects that Freesync requests are blocked when optimized_required is true. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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0c1f033159
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@ -2113,6 +2113,12 @@ void dcn20_optimize_bandwidth(
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if (hubbub->funcs->program_compbuf_size)
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hubbub->funcs->program_compbuf_size(hubbub, context->bw_ctx.bw.dcn.compbuf_size_kb, true);
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if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
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dc_dmub_srv_p_state_delegate(dc,
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true, context);
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context->bw_ctx.bw.dcn.clk.p_state_change_support = true;
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}
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dc->clk_mgr->funcs->update_clocks(
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dc->clk_mgr,
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context,
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@ -985,11 +985,18 @@ void dcn30_set_disp_pattern_generator(const struct dc *dc,
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void dcn30_prepare_bandwidth(struct dc *dc,
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struct dc_state *context)
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{
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if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) {
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dc->optimized_required = true;
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context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
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}
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if (dc->clk_mgr->dc_mode_softmax_enabled)
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if (dc->clk_mgr->clks.dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 &&
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context->bw_ctx.bw.dcn.clk.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
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dc->clk_mgr->funcs->set_max_memclk(dc->clk_mgr, dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz);
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dcn20_prepare_bandwidth(dc, context);
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dc_dmub_srv_p_state_delegate(dc, false, context);
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}
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