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drm/i915: use proper FBC base register on all new platforms
Starting from GEN5 the FBC base register is the same on all platforms. GEN>=5 is the same condition as HAS_PCH_SPLIT except on BXT, so make things work on BXT as well. Motivated by Rodrigo's request to check FBC support on BXT. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Antti Koskipää <antti.koskipaa@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -209,7 +209,7 @@ static int i915_setup_compression(struct drm_device *dev, int size, int fb_cpp)
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dev_priv->fbc.threshold = ret;
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if (HAS_PCH_SPLIT(dev))
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if (INTEL_INFO(dev_priv)->gen >= 5)
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I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start);
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else if (IS_GM45(dev)) {
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I915_WRITE(DPFC_CB_BASE, dev_priv->fbc.compressed_fb.start);
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