From 6b16953bec40e6fce853d2a69b8e738d61896568 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 31 Aug 2023 13:17:44 +0200 Subject: [PATCH 1/7] ARM: shmobile: rcar-gen2: Remove unneeded once handling rcar_gen2_pm_init() is only called from the smp_operations.smp_prepare_cpus() callback, which is called at most once. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/116ef21e5f495432d913315bdc25fbc30edcf2e1.1693409184.git.geert+renesas@glider.be --- arch/arm/mach-shmobile/pm-rcar-gen2.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c b/arch/arm/mach-shmobile/pm-rcar-gen2.c index 672081405a7e..7447e5fd7ed4 100644 --- a/arch/arm/mach-shmobile/pm-rcar-gen2.c +++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c @@ -46,16 +46,12 @@ void __init rcar_gen2_pm_init(void) { void __iomem *p; u32 bar; - static int once; struct device_node *np; bool has_a7 = false; bool has_a15 = false; struct resource res; int error; - if (once++) - return; - for_each_of_cpu_node(np) { if (of_device_is_compatible(np, "arm,cortex-a15")) has_a15 = true; From 9797e3519c68fd75eb73eb959f8d11830261e7bb Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 31 Aug 2023 13:17:45 +0200 Subject: [PATCH 2/7] ARM: shmobile: rcar-gen2: Reserve boot area when SMP is enabled CPU core bringup on R-Car Gen2 SoCs uses the Cortex-A7/A15 Boot Address Register to specify the boot area of the System CPU. With this enabled, when the System CPU accesses a physical address in the range from 0x0 to 0x3ffff, the top address bits are replaced by those specified in the SBAR register. Hence any device residing in the low 256 KiB of physical address space cannot be accessed. Prevent conflicts by reserving this memory region using request_mem_region(). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/091150233acb0557a2ad3294d67b2adb6758670c.1693409184.git.geert+renesas@glider.be --- arch/arm/mach-shmobile/pm-rcar-gen2.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/mach-shmobile/pm-rcar-gen2.c b/arch/arm/mach-shmobile/pm-rcar-gen2.c index 7447e5fd7ed4..907a4f8c5aed 100644 --- a/arch/arm/mach-shmobile/pm-rcar-gen2.c +++ b/arch/arm/mach-shmobile/pm-rcar-gen2.c @@ -52,6 +52,11 @@ void __init rcar_gen2_pm_init(void) struct resource res; int error; + if (!request_mem_region(0, SZ_256K, "Boot Area")) { + pr_err("Failed to request boot area\n"); + return; + } + for_each_of_cpu_node(np) { if (of_device_is_compatible(np, "arm,cortex-a15")) has_a15 = true; From 8d17004ebcd2cdcb8192500173fca67004e7c9ca Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 31 Aug 2023 13:17:46 +0200 Subject: [PATCH 3/7] ARM: shmobile: r8a7779: Reserve boot area when SMP is enabled CPU core bringup on R-Car H1 uses the ARM Reset Vector Address Register (AVECR) to specify the base address and size of the boot area of the System CPU. With this enabled, when the System CPU accesses a physical address in the range from zero up to the configured size, the top address bits are replaced by those specified in the AVECR register. Hence any device residing in this low part of physical address space cannot be accessed, Prevent conflicts by reserving this memory region using request_mem_region(). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/924961188abdf2adb52167edb7ed848a6efcca39.1693409184.git.geert+renesas@glider.be --- arch/arm/mach-shmobile/smp-r8a7779.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index 1bc609986c16..474c325323a3 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c @@ -38,7 +38,14 @@ static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) { - void __iomem *base = ioremap(HPBREG_BASE, 0x1000); + void __iomem *base; + + if (!request_mem_region(0, SZ_4K, "Boot Area")) { + pr_err("Failed to request boot area\n"); + return; + } + + base = ioremap(HPBREG_BASE, 0x1000); /* Map the reset vector (in headsmp-scu.S, headsmp.S) */ writel(__pa(shmobile_boot_vector), base + AVECR); From 435d422624b74085e2c0be650dc3a1d3a4a6bfa5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 31 Aug 2023 13:17:47 +0200 Subject: [PATCH 4/7] ARM: shmobile: sh73a0: Reserve boot area when SMP is enabled CPU core bringup on SH-Mobile AG5 uses the SYS Boot Address (SBAR) and Address Translation Area (APARMBAREA) registers to specify the base address and size of the boot area of the System CPU. With this enabled, when the System CPU accesses a physical address in the range from zero up to the configured size, the top address bits are replaced by those specified in the SBAR register. Hence any device residing in this low part of physical address space cannot be accessed. Prevent conflicts by reserving this memory region using request_mem_region(). Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20eb4e7fca9c41a34500fc5984602b41006b4575.1693409184.git.geert+renesas@glider.be --- arch/arm/mach-shmobile/smp-sh73a0.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 453d48865029..9196b37ea292 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c @@ -44,10 +44,16 @@ static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) { - void __iomem *ap = ioremap(AP_BASE, PAGE_SIZE); - void __iomem *sysc = ioremap(SYSC_BASE, PAGE_SIZE); + void __iomem *ap, *sysc; + + if (!request_mem_region(0, SZ_4K, "Boot Area")) { + pr_err("Failed to request boot area\n"); + return; + } /* Map the reset vector (in headsmp.S) */ + ap = ioremap(AP_BASE, PAGE_SIZE); + sysc = ioremap(SYSC_BASE, PAGE_SIZE); writel(0, ap + APARMBAREA); /* 4k */ writel(__pa(shmobile_boot_vector), sysc + SBAR); iounmap(sysc); From fbf37376f8acc47e379fe7411c039e67181bc4b8 Mon Sep 17 00:00:00 2001 From: Brad Larson Date: Mon, 25 Sep 2023 12:56:08 -0700 Subject: [PATCH 5/7] MAINTAINERS: Add entry for AMD PENSANDO Add entry for AMD PENSANDO maintainer and files Signed-off-by: Brad Larson Link: https://lore.kernel.org/r/20230925195610.47971-3-blarson@amd.com Signed-off-by: Arnd Bergmann --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b19995690904..0c9ec4a482f1 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1816,6 +1816,13 @@ N: allwinner N: sun[x456789]i N: sun[25]0i +ARM/AMD PENSANDO ARM64 ARCHITECTURE +M: Brad Larson +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Supported +F: Documentation/devicetree/bindings/*/amd,pensando* +F: arch/arm64/boot/dts/amd/elba* + ARM/Amlogic Meson SoC CLOCK FRAMEWORK M: Neil Armstrong M: Jerome Brunet From 646fe2e4b39049078d18c72832afec21dc9d6b52 Mon Sep 17 00:00:00 2001 From: Brad Larson Date: Mon, 25 Sep 2023 12:56:09 -0700 Subject: [PATCH 6/7] arm64: Add config for AMD Pensando SoC platforms Add ARCH_PENSANDO configuration option for AMD Pensando SoC based platforms. Signed-off-by: Brad Larson Link: https://lore.kernel.org/r/20230925195610.47971-4-blarson@amd.com Signed-off-by: Arnd Bergmann --- arch/arm64/Kconfig.platforms | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6069120199bb..24335565bad5 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -244,6 +244,18 @@ config ARCH_NPCM General support for NPCM8xx BMC (Arbel). Nuvoton NPCM8xx BMC based on the Cortex A35. +config ARCH_PENSANDO + bool "AMD Pensando Platforms" + help + This enables support for the ARMv8 based AMD Pensando SoC + family to include the Elba SoC. + + AMD Pensando SoCs support a range of Distributed Services + Cards in PCIe format installed into servers. The Elba + SoC includes 16 Cortex A-72 CPU cores, 144 P4-programmable + cores for a minimal latency/jitter datapath, and network + interfaces up to 200 Gb/s. + config ARCH_QCOM bool "Qualcomm Platforms" select GPIOLIB From a9838799e2fa9fedd77867942e661b657d5591a0 Mon Sep 17 00:00:00 2001 From: Lukas Bulwahn Date: Wed, 25 Oct 2023 13:21:36 +0200 Subject: [PATCH 7/7] arm: debug: reuse the config DEBUG_OMAP2UART{1,2} for OMAP{3,4,5} Commit d2b310b0234c ("ARM: debug: Use generic 8250 debug_ll for omap2 and omap3/4/5 common uarts") adds address definitions of DEBUG_UART_PHYS for OMAP2, OMAP3, OMAP4 and OMAP5 in ./arch/arm/Kconfig.debug. These definitions depend on DEBUG_OMAP{2,3,4,5}UART{1,2}; however, only DEBUG_OMAP2UART{1,2} are defined in ./arch/arm/Kconfig.debug, and DEBUG_OMAP{3,4,5}UART{1,2} are not defined. Hence, the script ./scripts/checkkconfigsymbols.py warns here on non-existing symbols. Simply reuse the config DEBUG_OMAP2UART{1,2}; there is no need to define separate config symbols for OMAP{3,4,5}. So, just delete the dead references to DEBUG_OMAP{3,4,5}UART{1,2}. Signed-off-by: Lukas Bulwahn Link: https://lore.kernel.org/r/20231025112136.3445-1-lukas.bulwahn@gmail.com Signed-off-by: Arnd Bergmann --- arch/arm/Kconfig.debug | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index b407b7b9b715..fc2b41d41447 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -1593,10 +1593,8 @@ config DEBUG_UART_PHYS default 0x48020000 if DEBUG_OMAP4UART3 || DEBUG_TI81XXUART1 default 0x48022000 if DEBUG_TI81XXUART2 default 0x48024000 if DEBUG_TI81XXUART3 - default 0x4806a000 if DEBUG_OMAP2UART1 || DEBUG_OMAP3UART1 || \ - DEBUG_OMAP4UART1 || DEBUG_OMAP5UART1 - default 0x4806c000 if DEBUG_OMAP2UART2 || DEBUG_OMAP3UART2 || \ - DEBUG_OMAP4UART2 || DEBUG_OMAP5UART2 + default 0x4806a000 if DEBUG_OMAP2UART1 + default 0x4806c000 if DEBUG_OMAP2UART2 default 0x4806e000 if DEBUG_OMAP2UART3 || DEBUG_OMAP4UART4 default 0x49020000 if DEBUG_OMAP3UART3 default 0x49042000 if DEBUG_OMAP3UART4 @@ -1719,10 +1717,8 @@ config DEBUG_UART_VIRT default 0xfa020000 if DEBUG_OMAP4UART3 || DEBUG_TI81XXUART1 default 0xfa022000 if DEBUG_TI81XXUART2 default 0xfa024000 if DEBUG_TI81XXUART3 - default 0xfa06a000 if DEBUG_OMAP2UART1 || DEBUG_OMAP3UART1 || \ - DEBUG_OMAP4UART1 || DEBUG_OMAP5UART1 - default 0xfa06c000 if DEBUG_OMAP2UART2 || DEBUG_OMAP3UART2 || \ - DEBUG_OMAP4UART2 || DEBUG_OMAP5UART2 + default 0xfa06a000 if DEBUG_OMAP2UART1 + default 0xfa06c000 if DEBUG_OMAP2UART2 default 0xfa06e000 if DEBUG_OMAP2UART3 || DEBUG_OMAP4UART4 default 0xfa71e000 if DEBUG_QCOM_UARTDM default 0xfb009000 if DEBUG_REALVIEW_STD_PORT