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drm/exynos/hdmi: fix PHY configuration sequence
Proper PHY configuration should be as follow: 1. set HDMI clock parents to OSCCLK. 2. reconfigure PHY. 3. set HDMI clock parents to PHY. 4. wait for PLL stabilization. The patch fixes it and consolidates the code. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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@ -1654,15 +1654,11 @@ static void hdmi_mode_apply(struct hdmi_context *hdata)
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else
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hdmi_v14_mode_apply(hdata);
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hdmiphy_wait_for_pll(hdata);
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hdmi_clk_set_parents(hdata, true);
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hdmi_start(hdata, true);
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}
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static void hdmiphy_conf_reset(struct hdmi_context *hdata)
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{
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hdmi_clk_set_parents(hdata, false);
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hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT);
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usleep_range(10000, 12000);
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hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, 0, HDMI_PHY_SW_RSTOUT);
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@ -1680,29 +1676,33 @@ static void hdmiphy_enable_mode_set(struct hdmi_context *hdata, bool enable)
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static void hdmiphy_conf_apply(struct hdmi_context *hdata)
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{
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int ret;
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int i;
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const u8 *phy_conf;
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i = hdmi_find_phy_conf(hdata, hdata->current_mode.clock * 1000);
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if (i < 0) {
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ret = hdmi_find_phy_conf(hdata, hdata->current_mode.clock * 1000);
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if (ret < 0) {
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DRM_ERROR("failed to find hdmiphy conf\n");
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return;
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}
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phy_conf = hdata->drv_data->phy_confs.data[ret].conf;
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hdmi_clk_set_parents(hdata, false);
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hdmiphy_conf_reset(hdata);
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hdmiphy_enable_mode_set(hdata, true);
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ret = hdmiphy_reg_write_buf(hdata, 0,
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hdata->drv_data->phy_confs.data[i].conf, 32);
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ret = hdmiphy_reg_write_buf(hdata, 0, phy_conf, 32);
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if (ret) {
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DRM_ERROR("failed to configure hdmiphy\n");
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return;
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}
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hdmiphy_enable_mode_set(hdata, false);
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hdmi_clk_set_parents(hdata, true);
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usleep_range(10000, 12000);
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hdmiphy_wait_for_pll(hdata);
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}
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static void hdmi_conf_apply(struct hdmi_context *hdata)
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{
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hdmiphy_conf_reset(hdata);
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hdmiphy_conf_apply(hdata);
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hdmi_start(hdata, false);
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hdmi_conf_init(hdata);
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