From 347c80f7c7b207ad8cb183822df75f70b7dc0773 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 27 Dec 2023 15:08:10 +0200 Subject: [PATCH 01/29] arm64: dts: renesas: rzg3s-smarc: Add gpio keys RZ SMARC Carrier II board has 3 user buttons called USER_SW1, USER_SW2, USER_SW3. Add a DT node in device tree to propertly instantiate the gpio-keys driver for these buttons. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20231227130810.2744550-1-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 53 ++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index 214520137230..deb2ad37bb2e 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include / { @@ -14,6 +15,37 @@ mmc1 = &sdhi1; }; + keys { + compatible = "gpio-keys"; + + key-1 { + interrupts = ; + interrupt-parent = <&pinctrl>; + linux,code = ; + label = "USER_SW1"; + wakeup-source; + debounce-interval = <20>; + }; + + key-2 { + interrupts = ; + interrupt-parent = <&pinctrl>; + linux,code = ; + label = "USER_SW2"; + wakeup-source; + debounce-interval = <20>; + }; + + key-3 { + interrupts = ; + interrupt-parent = <&pinctrl>; + linux,code = ; + label = "USER_SW3"; + wakeup-source; + debounce-interval = <20>; + }; + }; + vcc_sdhi1: regulator-vcc-sdhi1 { compatible = "regulator-fixed"; regulator-name = "SDHI1 Vcc"; @@ -35,6 +67,27 @@ }; &pinctrl { + key-1-gpio-hog { + gpio-hog; + gpios = ; + input; + line-name = "key-1-gpio-irq"; + }; + + key-2-gpio-hog { + gpio-hog; + gpios = ; + input; + line-name = "key-2-gpio-irq"; + }; + + key-3-gpio-hog { + gpio-hog; + gpios = ; + input; + line-name = "key-3-gpio-irq"; + }; + scif0_pins: scif0 { pinmux = , /* RXD */ ; /* TXD */ From 090c4094574705b0afc7d37825cdc5d06f0e7e02 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 15 Jan 2024 12:03:03 +0100 Subject: [PATCH 02/29] ARM: dts: renesas: r8a73a4: Fix external clocks and clock rate MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit External clocks should be defined as zero-Hz clocks in the SoC .dtsi, and overridden in the board .dts when present. Correct the clock rate of extal1 from 25 to 26 MHz, to match the crystal oscillator present on the APE6-EVM board. Fixes: a76809a329d6ebae ("ARM: shmobile: r8a73a4: Common clock framework DT description") Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/1692bc8cd465d62168cbf110522ad62a7af3f606.1705315614.git.geert+renesas@glider.be --- arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts | 12 ++++++++++++ arch/arm/boot/dts/renesas/r8a73a4.dtsi | 9 ++++++--- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts index ed75c01dbee1..3d02f065f71c 100644 --- a/arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts +++ b/arch/arm/boot/dts/renesas/r8a73a4-ape6evm.dts @@ -209,6 +209,18 @@ status = "okay"; }; +&extal1_clk { + clock-frequency = <26000000>; +}; + +&extal2_clk { + clock-frequency = <48000000>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + &pfc { scifa0_pins: scifa0 { groups = "scifa0_data"; diff --git a/arch/arm/boot/dts/renesas/r8a73a4.dtsi b/arch/arm/boot/dts/renesas/r8a73a4.dtsi index c39066967053..d1f4cbd099ef 100644 --- a/arch/arm/boot/dts/renesas/r8a73a4.dtsi +++ b/arch/arm/boot/dts/renesas/r8a73a4.dtsi @@ -450,17 +450,20 @@ extalr_clk: extalr { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32768>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; extal1_clk: extal1 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <25000000>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; extal2_clk: extal2 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <48000000>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; }; fsiack_clk: fsiack { compatible = "fixed-clock"; From dd9cc6afcbe7a81b73ad05a46bb51300e6f37a10 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 15 Jan 2024 12:03:04 +0100 Subject: [PATCH 03/29] ARM: dts: renesas: r8a73a4: Add cp clock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the Common Peripheral (CP) clock, which is driven by the main clock / 2 during normal system operation, but may be driven by EXTALR during early system boot, when SYSCLK_EN is still low. As the latter is irrelevant to Linux, just model it as a fixed clock driven from main_div2_clk. Switch all users of main_div2_clk that are documented to be clocked by the CP clock to cp_clk, to better reflect the actual clock topology. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/f9826b0755207a1e16871c17daca109fb11f3868.1705315614.git.geert+renesas@glider.be --- arch/arm/boot/dts/renesas/r8a73a4.dtsi | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/renesas/r8a73a4.dtsi b/arch/arm/boot/dts/renesas/r8a73a4.dtsi index d1f4cbd099ef..c2be1934490b 100644 --- a/arch/arm/boot/dts/renesas/r8a73a4.dtsi +++ b/arch/arm/boot/dts/renesas/r8a73a4.dtsi @@ -624,6 +624,13 @@ clock-div = <2>; clock-mult = <1>; }; + cp_clk: cp { + compatible = "fixed-factor-clock"; + clocks = <&main_div2_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; pll0_div2_clk: pll0_div2 { compatible = "fixed-factor-clock"; clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; @@ -689,9 +696,8 @@ mstp4_clks: mstp4_clks@e6150140 { compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_ZS>, - <&main_div2_clk>, - <&cpg_clocks R8A73A4_CLK_HP>, + clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_ZS>, + <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks R8A73A4_CLK_HP>; #clock-cells = <1>; clock-indices = < From d2339555c36a07ace3fdd5d7ad584072b3214ff6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 15 Jan 2024 12:03:05 +0100 Subject: [PATCH 04/29] ARM: dts: renesas: r8a73a4: Fix thermal parent clock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to Table 8.1, "Summary of Module Power, Reset condition and Clock assignment" of the R-Mobile APE6 Hardware Manual Rev. 0.7, the parent clock of the thermal sensor clock is the Common Peripheral (CP) clock, which runs at 13 MHz (main clock / 2). As the R-Car Thermal driver does not use the clock rate, this change has no functional impact. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/aac49d67d7a38230875543d49e84fcca587fb9e1.1705315614.git.geert+renesas@glider.be --- arch/arm/boot/dts/renesas/r8a73a4.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/renesas/r8a73a4.dtsi b/arch/arm/boot/dts/renesas/r8a73a4.dtsi index c2be1934490b..ac654ff45d0e 100644 --- a/arch/arm/boot/dts/renesas/r8a73a4.dtsi +++ b/arch/arm/boot/dts/renesas/r8a73a4.dtsi @@ -711,7 +711,7 @@ mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>; + clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; #clock-cells = <1>; clock-indices = < R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 From 8b93657c976a61726d7ffbe8d019b84b4abfb673 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 15 Jan 2024 14:33:18 +0100 Subject: [PATCH 05/29] arm64: dts: renesas: r8a779g0: Restore sort order Numerical by unit address, alphabetical by node name. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/f00ef274a73c8fd60f940a1649423a8927b9ae8a.1705324708.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 72 +++++++++++------------ 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index d3d25e077c5d..3be1159982b2 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -161,11 +161,6 @@ }; }; - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; @@ -185,6 +180,11 @@ interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; }; + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + /* External SCIF clock - to be overridden by boards that provide it */ scif_clk: scif { compatible = "fixed-clock"; @@ -1777,6 +1777,37 @@ }; }; + mmc0: mmc@ee140000 { + compatible = "renesas,sdhi-r8a779g0", + "renesas,rcar-gen4-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 706>, + <&cpg CPG_CORE R8A779G0_CLK_SD0H>; + clock-names = "core", "clkh"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 706>; + max-frequency = <200000000>; + iommus = <&ipmmu_ds0 32>; + status = "disabled"; + }; + + rpc: spi@ee200000 { + compatible = "renesas,r8a779g0-rpc-if", + "renesas,rcar-gen4-rpc-if"; + reg = <0 0xee200000 0 0x200>, + <0 0x08000000 0 0x04000000>, + <0 0xee208000 0 0x100>; + reg-names = "regs", "dirmap", "wbuf"; + interrupts = ; + clocks = <&cpg CPG_MOD 629>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 629>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + ipmmu_rt0: iommu@ee480000 { compatible = "renesas,ipmmu-r8a779g0", "renesas,rcar-gen4-ipmmu-vmsa"; @@ -1886,37 +1917,6 @@ #iommu-cells = <1>; }; - mmc0: mmc@ee140000 { - compatible = "renesas,sdhi-r8a779g0", - "renesas,rcar-gen4-sdhi"; - reg = <0 0xee140000 0 0x2000>; - interrupts = ; - clocks = <&cpg CPG_MOD 706>, - <&cpg CPG_CORE R8A779G0_CLK_SD0H>; - clock-names = "core", "clkh"; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 706>; - max-frequency = <200000000>; - iommus = <&ipmmu_ds0 32>; - status = "disabled"; - }; - - rpc: spi@ee200000 { - compatible = "renesas,r8a779g0-rpc-if", - "renesas,rcar-gen4-rpc-if"; - reg = <0 0xee200000 0 0x200>, - <0 0x08000000 0 0x04000000>, - <0 0xee208000 0 0x100>; - reg-names = "regs", "dirmap", "wbuf"; - interrupts = ; - clocks = <&cpg CPG_MOD 629>; - power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; - resets = <&cpg 629>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - gic: interrupt-controller@f1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; From bb235b728bf6ba0a1e369c9f88265ddf4f284aad Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 17 Jan 2024 14:18:06 +0100 Subject: [PATCH 06/29] arm64: dts: renesas: ulcb-kf: Drop duplicate 3.3v regulators Schematics say that all these 3.3v sources are driven by "D3.3V". We have a regulator for it already in ulcb.dtsi. Use it instead. Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240117131807.24997-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 35 +++++------------------- 1 file changed, 7 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 3885ef3454ff..40a5f98c1190 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -32,13 +32,6 @@ }; }; - accel_3v3: regulator-acc-3v3 { - compatible = "regulator-fixed"; - regulator-name = "accel-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - hdmi_1v8: regulator-hdmi-1v8 { compatible = "regulator-fixed"; regulator-name = "hdmi-1v8"; @@ -46,20 +39,6 @@ regulator-max-microvolt = <1800000>; }; - hdmi_3v3: regulator-hdmi-3v3 { - compatible = "regulator-fixed"; - regulator-name = "hdmi-3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - snd_3p3v: regulator-snd_3p3v { - compatible = "regulator-fixed"; - regulator-name = "snd-3.3v"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - snd_vcc5v: regulator-snd_vcc5v { compatible = "regulator-fixed"; regulator-name = "snd-vcc5v"; @@ -160,7 +139,7 @@ avdd-supply = <&hdmi_1v8>; dvdd-supply = <&hdmi_1v8>; pvdd-supply = <&hdmi_1v8>; - dvdd-3v-supply = <&hdmi_3v3>; + dvdd-3v-supply = <®_3p3v>; bgvdd-supply = <&hdmi_1v8>; adi,input-depth = <8>; @@ -198,8 +177,8 @@ compatible = "st,lsm9ds0-imu"; reg = <0x1d>; - vdd-supply = <&accel_3v3>; - vddio-supply = <&accel_3v3>; + vdd-supply = <®_3p3v>; + vddio-supply = <®_3p3v>; }; pcm3168a: audio-codec@44 { @@ -209,8 +188,8 @@ clocks = <&clksndsel>; clock-names = "scki"; - VDD1-supply = <&snd_3p3v>; - VDD2-supply = <&snd_3p3v>; + VDD1-supply = <®_3p3v>; + VDD2-supply = <®_3p3v>; VCCAD1-supply = <&snd_vcc5v>; VCCAD2-supply = <&snd_vcc5v>; VCCDA1-supply = <&snd_vcc5v>; @@ -221,8 +200,8 @@ compatible = "st,lsm9ds0-gyro"; reg = <0x6b>; - vdd-supply = <&accel_3v3>; - vddio-supply = <&accel_3v3>; + vdd-supply = <®_3p3v>; + vddio-supply = <®_3p3v>; }; }; }; From 7eb30251e157eb34814fdcaed2f54c5b400290ae Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 17 Jan 2024 14:18:07 +0100 Subject: [PATCH 07/29] arm64: dts: renesas: ulcb-kf: Add node for GNSS Signed-off-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240117131807.24997-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/ulcb-kf.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi index 40a5f98c1190..e3cc0e0e73cc 100644 --- a/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb-kf.dtsi @@ -392,6 +392,13 @@ pinctrl-names = "default"; status = "okay"; + + gnss { + compatible = "u-blox,neo-m8"; + reset-gpios = <&gpio_exp_75 6 GPIO_ACTIVE_LOW>; + vcc-supply = <®_3p3v>; + current-speed = <9600>; + }; }; &sdhi3 { From c90efc452ac121c11ea4dcd5a235f66fc2b5b46b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 25 Jan 2024 15:48:52 +0100 Subject: [PATCH 08/29] arm64: dts: renesas: r8a779g0: Add standalone White Hawk CPU support The White Hawk CPU board can be used standalone, without connecting it to the White Hawk BreakOut board. Add a DTS file for supporting this use case. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/95ac53e7f2bc42402eb411ad7f64a66864a3de01.1706192990.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../boot/dts/renesas/r8a779g0-white-hawk-cpu.dts | 13 +++++++++++++ .../boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi | 2 +- 3 files changed, 15 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 8ea68d582710..b959ae4a586b 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -82,6 +82,7 @@ dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f0-spider.dtb dtb-$(CONFIG_ARCH_R8A779F0) += r8a779f4-s4sk.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk.dtb +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-cpu.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-ard-audio-da7212.dtbo r8a779g0-white-hawk-ard-audio-da7212-dtbs := r8a779g0-white-hawk.dtb r8a779g0-white-hawk-ard-audio-da7212.dtbo dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-ard-audio-da7212.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dts b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dts new file mode 100644 index 000000000000..c8b1bb50a8cf --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the standalone R-Car V4H White Hawk CPU board + * + * Copyright (C) 2023 Glider bv + */ + +/dts-v1/; +#include "r8a779g0-white-hawk-cpu.dtsi" + +/ { + model = "Renesas White Hawk CPU board based on r8a779g0"; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi index 913f70fe6c5c..19ca831756f7 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the White Hawk CPU board + * Device Tree Source for the R-Car V4H White Hawk CPU board * * Copyright (C) 2022 Renesas Electronics Corp. */ From 48683d4a88ddf08f5582655c651736c0887618b9 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 25 Jan 2024 15:48:53 +0100 Subject: [PATCH 09/29] arm64: dts: renesas: white-hawk-cpu: Restore sort order Alphabetical by node name. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/f375293d6e21659ee30a86e2b46e4998a75ea3b5.1706192990.git.geert+renesas@glider.be --- .../boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi index 19ca831756f7..6d53b4006db3 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi @@ -25,6 +25,12 @@ stdout-path = "serial0:921600n8"; }; + sn65dsi86_refclk: clk-x6 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; + keys { compatible = "gpio-keys"; @@ -135,12 +141,6 @@ regulator-boot-on; regulator-always-on; }; - - sn65dsi86_refclk: clk-x6 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - }; }; &avb0 { From 1b940d036d5a2235323851c579100d1d835d1474 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 25 Jan 2024 15:48:54 +0100 Subject: [PATCH 10/29] arm64: dts: renesas: white-hawk: Drop SoC parts from sub boards The White Hawk CSI/DSI and RAVB/Ethernet(1000Base-T1) sub boards are not specific to R-Car V4H. Hence rename their DTS file names to drop the "r8a779g0-" prefix, and remove any references to R-Car V4H. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/f89613d0df04cfa6196f8797fe655cf7cec812de.1706192990.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts | 4 ++-- ...a779g0-white-hawk-csi-dsi.dtsi => white-hawk-csi-dsi.dtsi} | 2 +- ...79g0-white-hawk-ethernet.dtsi => white-hawk-ethernet.dtsi} | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) rename arch/arm64/boot/dts/renesas/{r8a779g0-white-hawk-csi-dsi.dtsi => white-hawk-csi-dsi.dtsi} (97%) rename arch/arm64/boot/dts/renesas/{r8a779g0-white-hawk-ethernet.dtsi => white-hawk-ethernet.dtsi} (76%) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts index eff1ef6e2cc8..8d82294a1a56 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts @@ -7,8 +7,8 @@ /dts-v1/; #include "r8a779g0-white-hawk-cpu.dtsi" -#include "r8a779g0-white-hawk-csi-dsi.dtsi" -#include "r8a779g0-white-hawk-ethernet.dtsi" +#include "white-hawk-csi-dsi.dtsi" +#include "white-hawk-ethernet.dtsi" / { model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0"; diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-csi-dsi.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi similarity index 97% rename from arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-csi-dsi.dtsi rename to arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi index f8537f7ea4de..3006b0a64f41 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-csi-dsi.dtsi +++ b/arch/arm64/boot/dts/renesas/white-hawk-csi-dsi.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the R-Car V4H White Hawk CSI/DSI sub-board + * Device Tree Source for the White Hawk CSI/DSI sub-board * * Copyright (C) 2022 Glider bv */ diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ethernet.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-ethernet.dtsi similarity index 76% rename from arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ethernet.dtsi rename to arch/arm64/boot/dts/renesas/white-hawk-ethernet.dtsi index 4f411f95c674..a218fda337cf 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-ethernet.dtsi +++ b/arch/arm64/boot/dts/renesas/white-hawk-ethernet.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the R-Car V4H White Hawk RAVB/Ethernet(1000Base-T1) + * Device Tree Source for the White Hawk RAVB/Ethernet(1000Base-T1) * sub-board * * Copyright (C) 2022 Glider bv From a9baf0b42d2048984027ab456f30ee3e93815893 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 25 Jan 2024 15:48:55 +0100 Subject: [PATCH 11/29] arm64: dts: renesas: white-hawk: Add SoC name to top-level comment The White Hawk CPU and BreakOut board DTS is specific to R-Car V4H. Document it in the top-level comment. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/de81db7ca38c8f4737092bdac6891e9db4bb9bd6.1706192990.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts index 8d82294a1a56..a9bc258cbf55 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) /* - * Device Tree Source for the White Hawk CPU and BreakOut boards + * Device Tree Source for the R-Car V4H White Hawk CPU and BreakOut boards * * Copyright (C) 2022 Renesas Electronics Corp. */ From b84bd2230a58e5c208ac3ebe75047179e7441866 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 25 Jan 2024 15:48:56 +0100 Subject: [PATCH 12/29] arm64: dts: renesas: white-hawk-cpu: Factor out common parts Factor out the parts on the White Hawk CPU board that are also present on the White Hawk Single board, so they can be reused when introducing support for the latter. Signed-off-by: Geert Uytterhoeven Acked-by: Wolfram Sang Link: https://lore.kernel.org/r/50676e7e9ac1c50ab450c030481f60ece4c3947e.1706192990.git.geert+renesas@glider.be --- .../dts/renesas/r8a779g0-white-hawk-cpu.dtsi | 366 +---------------- .../dts/renesas/white-hawk-cpu-common.dtsi | 375 ++++++++++++++++++ 2 files changed, 376 insertions(+), 365 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi index 6d53b4006db3..b1fe1aedc27d 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk-cpu.dtsi @@ -6,373 +6,9 @@ */ #include "r8a779g0.dtsi" - -#include -#include -#include +#include "white-hawk-cpu-common.dtsi" / { model = "Renesas White Hawk CPU board"; compatible = "renesas,white-hawk-cpu", "renesas,r8a779g0"; - - aliases { - ethernet0 = &avb0; - serial0 = &hscif0; - }; - - chosen { - bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; - stdout-path = "serial0:921600n8"; - }; - - sn65dsi86_refclk: clk-x6 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <38400000>; - }; - - keys { - compatible = "gpio-keys"; - - pinctrl-0 = <&keys_pins>; - pinctrl-names = "default"; - - key-1 { - gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW47"; - wakeup-source; - debounce-interval = <20>; - }; - - key-2 { - gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW48"; - wakeup-source; - debounce-interval = <20>; - }; - - key-3 { - gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; - linux,code = ; - label = "SW49"; - wakeup-source; - debounce-interval = <20>; - }; - }; - - leds { - compatible = "gpio-leds"; - - led-1 { - gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <1>; - }; - - led-2 { - gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <2>; - }; - - led-3 { - gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; - color = ; - function = LED_FUNCTION_INDICATOR; - function-enumerator = <3>; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x78000000>; - }; - - memory@480000000 { - device_type = "memory"; - reg = <0x4 0x80000000 0x0 0x80000000>; - }; - - memory@600000000 { - device_type = "memory"; - reg = <0x6 0x00000000 0x1 0x00000000>; - }; - - mini-dp-con { - compatible = "dp-connector"; - label = "CN5"; - type = "mini"; - - port { - mini_dp_con_in: endpoint { - remote-endpoint = <&sn65dsi86_out>; - }; - }; - }; - - reg_1p2v: regulator-1p2v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.2V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_1p8v: regulator-1p8v { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; -}; - -&avb0 { - pinctrl-0 = <&avb0_pins>; - pinctrl-names = "default"; - phy-handle = <&phy0>; - tx-internal-delay-ps = <2000>; - status = "okay"; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio7>; - interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; - }; -}; - -&dsi0 { - status = "okay"; - - ports { - port@1 { - dsi0_out: endpoint { - remote-endpoint = <&sn65dsi86_in>; - data-lanes = <1 2 3 4>; - }; - }; - }; -}; - -&du { - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&hscif0 { - pinctrl-0 = <&hscif0_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - io_expander_a: gpio@20 { - compatible = "onnn,pca9654"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - eeprom@50 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "cpu-board"; - reg = <0x50>; - pagesize = <8>; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - bridge@2c { - compatible = "ti,sn65dsi86"; - reg = <0x2c>; - - clocks = <&sn65dsi86_refclk>; - clock-names = "refclk"; - - interrupt-parent = <&intc_ex>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - - enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - - vccio-supply = <®_1p8v>; - vpll-supply = <®_1p8v>; - vcca-supply = <®_1p2v>; - vcc-supply = <®_1p2v>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - sn65dsi86_in: endpoint { - remote-endpoint = <&dsi0_out>; - }; - }; - - port@1 { - reg = <1>; - sn65dsi86_out: endpoint { - remote-endpoint = <&mini_dp_con_in>; - }; - }; - }; - }; -}; - -&mmc0 { - pinctrl-0 = <&mmc_pins>; - pinctrl-1 = <&mmc_pins>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <®_3p3v>; - vqmmc-supply = <®_1p8v>; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - bus-width = <8>; - no-sd; - no-sdio; - non-removable; - full-pwr-cycle-in-suspend; - status = "okay"; -}; - -&pfc { - pinctrl-0 = <&scif_clk_pins>; - pinctrl-names = "default"; - - avb0_pins: avb0 { - mux { - groups = "avb0_link", "avb0_mdio", "avb0_rgmii", - "avb0_txcrefclk"; - function = "avb0"; - }; - - pins_mdio { - groups = "avb0_mdio"; - drive-strength = <21>; - }; - - pins_mii { - groups = "avb0_rgmii"; - drive-strength = <21>; - }; - - }; - hscif0_pins: hscif0 { - groups = "hscif0_data"; - function = "hscif0"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - keys_pins: keys { - pins = "GP_5_0", "GP_5_1", "GP_5_2"; - bias-pull-up; - }; - - mmc_pins: mmc { - groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; - function = "mmc"; - power-source = <1800>; - }; - - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data4"; - function = "qspi0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk"; - function = "scif_clk"; - }; -}; - -&rpc { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fs512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <40000000>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - boot@0 { - reg = <0x0 0x1200000>; - read-only; - }; - user@1200000 { - reg = <0x1200000 0x2e00000>; - }; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif_clk { - clock-frequency = <24000000>; }; diff --git a/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi new file mode 100644 index 000000000000..8ac17370ff36 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi @@ -0,0 +1,375 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the common parts shared by the White Hawk CPU and + * White Hawk Single boards + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include +#include + +/ { + aliases { + ethernet0 = &avb0; + serial0 = &hscif0; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + stdout-path = "serial0:921600n8"; + }; + + sn65dsi86_refclk: clk-x6 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <38400000>; + }; + + keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&keys_pins>; + pinctrl-names = "default"; + + key-1 { + gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW47"; + wakeup-source; + debounce-interval = <20>; + }; + + key-2 { + gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW48"; + wakeup-source; + debounce-interval = <20>; + }; + + key-3 { + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "SW49"; + wakeup-source; + debounce-interval = <20>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-1 { + gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <1>; + }; + + led-2 { + gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <2>; + }; + + led-3 { + gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; + color = ; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <3>; + }; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x0 0x80000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x1 0x00000000>; + }; + + mini-dp-con { + compatible = "dp-connector"; + label = "CN5"; + type = "mini"; + + port { + mini_dp_con_in: endpoint { + remote-endpoint = <&sn65dsi86_out>; + }; + }; + }; + + reg_1p2v: regulator-1p2v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&avb0 { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + tx-internal-delay-ps = <2000>; + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio7>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio7 10 GPIO_ACTIVE_LOW>; + }; +}; + +&dsi0 { + status = "okay"; + + ports { + port@1 { + dsi0_out: endpoint { + remote-endpoint = <&sn65dsi86_in>; + data-lanes = <1 2 3 4>; + }; + }; + }; +}; + +&du { + status = "okay"; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&hscif0 { + pinctrl-0 = <&hscif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + io_expander_a: gpio@20 { + compatible = "onnn,pca9654"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + eeprom@50 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "cpu-board"; + reg = <0x50>; + pagesize = <8>; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + + clocks = <&sn65dsi86_refclk>; + clock-names = "refclk"; + + interrupt-parent = <&intc_ex>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + + vccio-supply = <®_1p8v>; + vpll-supply = <®_1p8v>; + vcca-supply = <®_1p2v>; + vcc-supply = <®_1p2v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + sn65dsi86_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + + port@1 { + reg = <1>; + sn65dsi86_out: endpoint { + remote-endpoint = <&mini_dp_con_in>; + }; + }; + }; + }; +}; + +&mmc0 { + pinctrl-0 = <&mmc_pins>; + pinctrl-1 = <&mmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + avb0_pins: avb0 { + mux { + groups = "avb0_link", "avb0_mdio", "avb0_rgmii", + "avb0_txcrefclk"; + function = "avb0"; + }; + + pins_mdio { + groups = "avb0_mdio"; + drive-strength = <21>; + }; + + pins_mii { + groups = "avb0_rgmii"; + drive-strength = <21>; + }; + + }; + + hscif0_pins: hscif0 { + groups = "hscif0_data"; + function = "hscif0"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + + keys_pins: keys { + pins = "GP_5_0", "GP_5_1", "GP_5_2"; + bias-pull-up; + }; + + mmc_pins: mmc { + groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; + function = "mmc"; + power-source = <1800>; + }; + + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; +}; + +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + compatible = "spansion,s25fs512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x0 0x1200000>; + read-only; + }; + user@1200000 { + reg = <0x1200000 0x2e00000>; + }; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif_clk { + clock-frequency = <24000000>; +}; From 874dca5d211559e6124d422809687381e2534cfe Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 25 Jan 2024 15:48:57 +0100 Subject: [PATCH 13/29] arm64: dts: renesas: white-hawk: Factor out common parts Factor out the parts on the White Hawk BreakOut board that are also present on the White Hawk Single board, so they can be reused when introducing support for the latter. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/8c05b4d283b5d765fbc6f64cee9a247cded29409.1706192990.git.geert+renesas@glider.be --- .../boot/dts/renesas/r8a779g0-white-hawk.dts | 56 +--------------- .../boot/dts/renesas/white-hawk-common.dtsi | 65 +++++++++++++++++++ 2 files changed, 66 insertions(+), 55 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/white-hawk-common.dtsi diff --git a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts index a9bc258cbf55..784d4e8b204c 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts +++ b/arch/arm64/boot/dts/renesas/r8a779g0-white-hawk.dts @@ -7,63 +7,9 @@ /dts-v1/; #include "r8a779g0-white-hawk-cpu.dtsi" -#include "white-hawk-csi-dsi.dtsi" -#include "white-hawk-ethernet.dtsi" +#include "white-hawk-common.dtsi" / { model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0"; compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu", "renesas,r8a779g0"; - - can_transceiver0: can-phy0 { - compatible = "nxp,tjr1443"; - #phy-cells = <0>; - enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - max-bitrate = <5000000>; - }; -}; - -&can_clk { - clock-frequency = <40000000>; -}; - -&canfd { - pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>; - pinctrl-names = "default"; - - status = "okay"; - - channel0 { - status = "okay"; - phys = <&can_transceiver0>; - }; - - channel1 { - status = "okay"; - }; -}; - -&i2c0 { - eeprom@51 { - compatible = "rohm,br24g01", "atmel,24c01"; - label = "breakout-board"; - reg = <0x51>; - pagesize = <8>; - }; -}; - -&pfc { - can_clk_pins: can-clk { - groups = "can_clk"; - function = "can_clk"; - }; - - canfd0_pins: canfd0 { - groups = "canfd0_data"; - function = "canfd0"; - }; - - canfd1_pins: canfd1 { - groups = "canfd1_data"; - function = "canfd1"; - }; }; diff --git a/arch/arm64/boot/dts/renesas/white-hawk-common.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-common.dtsi new file mode 100644 index 000000000000..c99086edadca --- /dev/null +++ b/arch/arm64/boot/dts/renesas/white-hawk-common.dtsi @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the common parts shared by the White Hawk BreakOut + * and White Hawk Single boards + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include "white-hawk-csi-dsi.dtsi" +#include "white-hawk-ethernet.dtsi" + +/ { + can_transceiver0: can-phy0 { + compatible = "nxp,tjr1443"; + #phy-cells = <0>; + enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; + max-bitrate = <5000000>; + }; +}; + +&can_clk { + clock-frequency = <40000000>; +}; + +&canfd { + pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>, <&can_clk_pins>; + pinctrl-names = "default"; + + status = "okay"; + + channel0 { + status = "okay"; + phys = <&can_transceiver0>; + }; + + channel1 { + status = "okay"; + }; +}; + +&i2c0 { + eeprom@51 { + compatible = "rohm,br24g01", "atmel,24c01"; + label = "breakout-board"; + reg = <0x51>; + pagesize = <8>; + }; +}; + +&pfc { + can_clk_pins: can-clk { + groups = "can_clk"; + function = "can_clk"; + }; + + canfd0_pins: canfd0 { + groups = "canfd0_data"; + function = "canfd0"; + }; + + canfd1_pins: canfd1 { + groups = "canfd1_data"; + function = "canfd1"; + }; +}; From 7605e7e90b6a5c87e05d031018a8e6d024b73953 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 25 Jan 2024 15:48:58 +0100 Subject: [PATCH 14/29] arm64: dts: renesas: Add Renesas R8A779G2 SoC support Add support for the Renesas R-Car V4H ES2.0 (R8A779G2) SoC, which is an updated version of the R-Car V4H (R8A779G0) SoC. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/4f773dbb66af5da51d1e171424ec8f97ee933b36.1706192990.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g2.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779g2.dtsi diff --git a/arch/arm64/boot/dts/renesas/r8a779g2.dtsi b/arch/arm64/boot/dts/renesas/r8a779g2.dtsi new file mode 100644 index 000000000000..e08f531843e2 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g2.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4H (R8A779G2) SoC + * + * Copyright (C) 2023 Glider bv + */ + +#include "r8a779g0.dtsi" + +/ { + compatible = "renesas,r8a779g2", "renesas,r8a779g0"; +}; From 55cda67bf3121c7cdf9aa65ed2a5d1927027c5b0 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 25 Jan 2024 15:48:59 +0100 Subject: [PATCH 15/29] arm64: dts: renesas: r8a779g2: Add White Hawk Single support The White Hawk Single board is a single-board integration of the Renesas White Hawk CPU and Breakout board stack, based on the R-Car V4H ES2.0 (R8A779G2) SoC. For now, the only visible differences compared to the board stack are: - The SoC is an updated version of R-Car V4H (R8A779G0), - The serial console uses an FT2232H instead of a CP2102 USB-UART bridge, with CTS/RTS wired. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/2b8d37949c17cca170c1d9e97f10a100b20c5cd9.1706192990.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/Makefile | 2 ++ .../renesas/r8a779g2-white-hawk-single.dts | 26 +++++++++++++++++++ 2 files changed, 28 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779g2-white-hawk-single.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index b959ae4a586b..1d7d69657a1f 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -87,6 +87,8 @@ dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-ard-audio-da7212.dtbo r8a779g0-white-hawk-ard-audio-da7212-dtbs := r8a779g0-white-hawk.dtb r8a779g0-white-hawk-ard-audio-da7212.dtbo dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-ard-audio-da7212.dtb +dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g2-white-hawk-single.dtb + dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs.dtb r8a779m1-salvator-xs-panel-aa104xd12-dtbs := r8a779m1-salvator-xs.dtb salvator-panel-aa104xd12.dtbo dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs-panel-aa104xd12.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a779g2-white-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779g2-white-hawk-single.dts new file mode 100644 index 000000000000..2f79e5a61248 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779g2-white-hawk-single.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4H ES2.0 White Hawk Single board + * + * Copyright (C) 2023 Glider bv + */ + +/dts-v1/; +#include "r8a779g2.dtsi" +#include "white-hawk-cpu-common.dtsi" +#include "white-hawk-common.dtsi" + +/ { + model = "Renesas White Hawk Single board based on r8a779g2"; + compatible = "renesas,white-hawk-single", "renesas,r8a779g2", + "renesas,r8a779g0"; +}; + +&hscif0 { + uart-has-rtscts; +}; + +&hscif0_pins { + groups = "hscif0_data", "hscif0_ctrl"; + function = "hscif0"; +}; From 1fa8924a488a46b2709f1babd7176193fa077a93 Mon Sep 17 00:00:00 2001 From: Duy Nguyen Date: Thu, 25 Jan 2024 16:34:31 +0100 Subject: [PATCH 16/29] dt-bindings: power: renesas,rcar-sysc: Document R-Car V4M support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document support for the System Controller (SYSC) in the R-Car V4M (R8A779H0) SoC. Signed-off-by: Duy Nguyen Signed-off-by: Geert Uytterhoeven Acked-by: Conor Dooley Reviewed-by: Niklas Söderlund Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/6315cbd0b6e9b92a7914d98f397a2c663ad521c6.1706194617.git.geert+renesas@glider.be Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml index 0720b54881c2..e76fb273490f 100644 --- a/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml +++ b/Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml @@ -45,6 +45,7 @@ properties: - renesas,r8a779a0-sysc # R-Car V3U - renesas,r8a779f0-sysc # R-Car S4-8 - renesas,r8a779g0-sysc # R-Car V4H + - renesas,r8a779h0-sysc # R-Car V4M reg: maxItems: 1 From 8923149ffc77eefa16d5412e30cf0e9cf26a01ba Mon Sep 17 00:00:00 2001 From: Duy Nguyen Date: Thu, 25 Jan 2024 16:34:32 +0100 Subject: [PATCH 17/29] dt-bindings: power: Add r8a779h0 SYSC power domain definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add power domain indices for the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Duy Nguyen Signed-off-by: Hai Pham Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/c5cbef71178cada761e9da7bcbb6f21334f93ef8.1706194617.git.geert+renesas@glider.be Signed-off-by: Ulf Hansson --- .../dt-bindings/power/renesas,r8a779h0-sysc.h | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 include/dt-bindings/power/renesas,r8a779h0-sysc.h diff --git a/include/dt-bindings/power/renesas,r8a779h0-sysc.h b/include/dt-bindings/power/renesas,r8a779h0-sysc.h new file mode 100644 index 000000000000..f27976f523e8 --- /dev/null +++ b/include/dt-bindings/power/renesas,r8a779h0-sysc.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ +#define __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ + +/* + * These power domain indices match the Power Domain Register Numbers (PDR) + */ + +#define R8A779H0_PD_A1E0D0C0 0 +#define R8A779H0_PD_A1E0D0C1 1 +#define R8A779H0_PD_A1E0D0C2 2 +#define R8A779H0_PD_A1E0D0C3 3 +#define R8A779H0_PD_A2E0D0 16 +#define R8A779H0_PD_A3CR0 21 +#define R8A779H0_PD_A3CR1 22 +#define R8A779H0_PD_A3CR2 23 +#define R8A779H0_PD_A33DGA 24 +#define R8A779H0_PD_A23DGB 25 +#define R8A779H0_PD_C4 31 +#define R8A779H0_PD_A1DSP0 33 +#define R8A779H0_PD_A2IMP01 34 +#define R8A779H0_PD_A2PSC 35 +#define R8A779H0_PD_A2CV0 36 +#define R8A779H0_PD_A2CV1 37 +#define R8A779H0_PD_A3IMR0 38 +#define R8A779H0_PD_A3IMR1 39 +#define R8A779H0_PD_A3VC 40 +#define R8A779H0_PD_A2CN0 42 +#define R8A779H0_PD_A1CN0 44 +#define R8A779H0_PD_A1DSP1 45 +#define R8A779H0_PD_A2DMA 47 +#define R8A779H0_PD_A2CV2 48 +#define R8A779H0_PD_A2CV3 49 +#define R8A779H0_PD_A3IMR2 50 +#define R8A779H0_PD_A3IMR3 51 +#define R8A779H0_PD_A3PCI 52 +#define R8A779H0_PD_A2PCIPHY 53 +#define R8A779H0_PD_A3VIP0 56 +#define R8A779H0_PD_A3VIP2 58 +#define R8A779H0_PD_A3ISP0 60 +#define R8A779H0_PD_A3DUL 62 + +/* Always-on power area */ +#define R8A779H0_PD_ALWAYS_ON 64 + +#endif /* __DT_BINDINGS_POWER_RENESAS_R8A779H0_SYSC_H__ */ From 2a8998479328a6eb6a2b07a68c7a756fe717b9e2 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 25 Jan 2024 16:34:29 +0100 Subject: [PATCH 18/29] dt-bindings: clock: renesas,cpg-mssr: Document R-Car V4M support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document support for the Clock Pulse Generator (CPG) and Module Standby Software Reset (MSSR) module on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Geert Uytterhoeven Acked-by: Conor Dooley Reviewed-by: Niklas Söderlund Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/eb3cd02b62f3ca834df079a3f1e551d9414fe42a.1706194617.git.geert+renesas@glider.be --- Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml index 9c3dc6c4fa94..084259d30232 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml @@ -50,6 +50,7 @@ properties: - renesas,r8a779a0-cpg-mssr # R-Car V3U - renesas,r8a779f0-cpg-mssr # R-Car S4-8 - renesas,r8a779g0-cpg-mssr # R-Car V4H + - renesas,r8a779h0-cpg-mssr # R-Car V4M reg: maxItems: 1 From 3bbdf8c3d32103e21d9a826e40340fa59fc579ea Mon Sep 17 00:00:00 2001 From: Duy Nguyen Date: Thu, 25 Jan 2024 16:34:30 +0100 Subject: [PATCH 19/29] dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add all Clock Pulse Generator Core Clock Outputs for the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Duy Nguyen Signed-off-by: Hai Pham Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/11acbd2a30b58607474e9c32eb798b3a00e85e73.1706194617.git.geert+renesas@glider.be --- .../clock/renesas,r8a779h0-cpg-mssr.h | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h diff --git a/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h b/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h new file mode 100644 index 000000000000..7ab6cfbaf901 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ + +#include + +/* r8a779h0 CPG Core Clocks */ + +#define R8A779H0_CLK_ZX 0 +#define R8A779H0_CLK_ZD 1 +#define R8A779H0_CLK_ZS 2 +#define R8A779H0_CLK_ZT 3 +#define R8A779H0_CLK_ZTR 4 +#define R8A779H0_CLK_S0D2 5 +#define R8A779H0_CLK_S0D3 6 +#define R8A779H0_CLK_S0D4 7 +#define R8A779H0_CLK_S0D1_VIO 8 +#define R8A779H0_CLK_S0D2_VIO 9 +#define R8A779H0_CLK_S0D4_VIO 10 +#define R8A779H0_CLK_S0D8_VIO 11 +#define R8A779H0_CLK_VIOBUSD1 12 +#define R8A779H0_CLK_VIOBUSD2 13 +#define R8A779H0_CLK_S0D1_VC 14 +#define R8A779H0_CLK_S0D2_VC 15 +#define R8A779H0_CLK_S0D4_VC 16 +#define R8A779H0_CLK_VCBUSD1 17 +#define R8A779H0_CLK_VCBUSD2 18 +#define R8A779H0_CLK_S0D2_MM 19 +#define R8A779H0_CLK_S0D4_MM 20 +#define R8A779H0_CLK_S0D2_U3DG 21 +#define R8A779H0_CLK_S0D4_U3DG 22 +#define R8A779H0_CLK_S0D2_RT 23 +#define R8A779H0_CLK_S0D3_RT 24 +#define R8A779H0_CLK_S0D4_RT 25 +#define R8A779H0_CLK_S0D6_RT 26 +#define R8A779H0_CLK_S0D2_PER 27 +#define R8A779H0_CLK_S0D3_PER 28 +#define R8A779H0_CLK_S0D4_PER 29 +#define R8A779H0_CLK_S0D6_PER 30 +#define R8A779H0_CLK_S0D12_PER 31 +#define R8A779H0_CLK_S0D24_PER 32 +#define R8A779H0_CLK_S0D1_HSC 33 +#define R8A779H0_CLK_S0D2_HSC 34 +#define R8A779H0_CLK_S0D4_HSC 35 +#define R8A779H0_CLK_S0D8_HSC 36 +#define R8A779H0_CLK_SVD1_IR 37 +#define R8A779H0_CLK_SVD2_IR 38 +#define R8A779H0_CLK_IMPAD1 39 +#define R8A779H0_CLK_IMPAD4 40 +#define R8A779H0_CLK_IMPB 41 +#define R8A779H0_CLK_SVD1_VIP 42 +#define R8A779H0_CLK_SVD2_VIP 43 +#define R8A779H0_CLK_CL 44 +#define R8A779H0_CLK_CL16M 45 +#define R8A779H0_CLK_CL16M_MM 46 +#define R8A779H0_CLK_CL16M_RT 47 +#define R8A779H0_CLK_CL16M_PER 48 +#define R8A779H0_CLK_CL16M_HSC 49 +#define R8A779H0_CLK_ZC0 50 +#define R8A779H0_CLK_ZC1 51 +#define R8A779H0_CLK_ZC2 52 +#define R8A779H0_CLK_ZC3 53 +#define R8A779H0_CLK_ZB3 54 +#define R8A779H0_CLK_ZB3D2 55 +#define R8A779H0_CLK_ZB3D4 56 +#define R8A779H0_CLK_ZG 57 +#define R8A779H0_CLK_SD0H 58 +#define R8A779H0_CLK_SD0 59 +#define R8A779H0_CLK_RPC 60 +#define R8A779H0_CLK_RPCD2 61 +#define R8A779H0_CLK_MSO 62 +#define R8A779H0_CLK_CANFD 63 +#define R8A779H0_CLK_CSI 64 +#define R8A779H0_CLK_FRAY 65 +#define R8A779H0_CLK_IPC 66 +#define R8A779H0_CLK_SASYNCRT 67 +#define R8A779H0_CLK_SASYNCPERD1 68 +#define R8A779H0_CLK_SASYNCPERD2 69 +#define R8A779H0_CLK_SASYNCPERD4 70 +#define R8A779H0_CLK_DSIEXT 71 +#define R8A779H0_CLK_DSIREF 72 +#define R8A779H0_CLK_ADGH 73 +#define R8A779H0_CLK_OSC 74 +#define R8A779H0_CLK_ZR0 75 +#define R8A779H0_CLK_ZR1 76 +#define R8A779H0_CLK_ZR2 77 +#define R8A779H0_CLK_RGMII 78 +#define R8A779H0_CLK_CPEX 79 +#define R8A779H0_CLK_CP 80 +#define R8A779H0_CLK_CBFUSA 81 +#define R8A779H0_CLK_R 82 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A779H0_CPG_MSSR_H__ */ From 08e799f6bce80dd63c174d8d0fc61d1a6149960b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 18 Jan 2024 17:32:37 +0100 Subject: [PATCH 20/29] arm64: dts: renesas: r8a779g0: Add missing SCIF_CLK2 R-Car V4H actually has two SCIF_CLK pins. The second pin provides the SCIF_CLK signal for HSCIF2 and SCIF4. Fixes: a4c31c56d2d35641 ("arm64: dts: renesas: r8a779g0: Add SCIF nodes") Fixes: 39d9dfc6fbe1860e ("arm64: dts: renesas: r8a779g0: Add remaining HSCIF nodes") Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/72f20c1bf32187bd30a963cafe27252907d661f9.1705589612.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 3be1159982b2..0c83940b3d8a 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -185,13 +185,19 @@ method = "smc"; }; - /* External SCIF clock - to be overridden by boards that provide it */ + /* External SCIF clocks - to be overridden by boards that provide them */ scif_clk: scif { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; + scif_clk2: scif2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; @@ -681,7 +687,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 516>, <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, - <&scif_clk>; + <&scif_clk2>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x35>, <&dmac0 0x34>, <&dmac1 0x35>, <&dmac1 0x34>; @@ -1057,7 +1063,7 @@ interrupts = ; clocks = <&cpg CPG_MOD 705>, <&cpg CPG_CORE R8A779G0_CLK_SASYNCPERD1>, - <&scif_clk>; + <&scif_clk2>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x59>, <&dmac0 0x58>, <&dmac1 0x59>, <&dmac1 0x58>; From cee7bef61f51c04c9946cf4ddb81e85d9c1833d2 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Mon, 22 Jan 2024 13:11:14 +0200 Subject: [PATCH 21/29] arm64: dts: renesas: r9a08g045: Add watchdog node Add the DT node for the watchdog IP accessible by Cortex-A of RZ/G3S SoC (R9108G045). Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240122111115.2861835-10-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 5facfad96158..dfee878c0f49 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -264,6 +264,20 @@ <0x0 0x12440000 0 0x60000>; interrupts = ; }; + + wdt0: watchdog@12800800 { + compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt"; + reg = <0 0x12800800 0 0x400>; + clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>, + <&cpg CPG_MOD R9A08G045_WDT0_CLK>; + clock-names = "pclk", "oscclk"; + interrupts = , + ; + interrupt-names = "wdt", "perrout"; + resets = <&cpg R9A08G045_WDT0_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; }; timer { From 2c0f4dfad96a6809506265f53f251b83ab2c848a Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Mon, 22 Jan 2024 13:11:15 +0200 Subject: [PATCH 22/29] arm64: dts: renesas: rzg3s-smarc-som: Enable the watchdog interface Enable the watchdog interface (accessible by Cortex-A of RZ/G3S SoC) on RZ/G3S SMARC SoM. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240122111115.2861835-11-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index f062d4ad78b7..2b7fa5817d58 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -336,3 +336,8 @@ }; }; }; + +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; From 227ec979581047bad97ec6ac8307fc1e85befff8 Mon Sep 17 00:00:00 2001 From: Hai Pham Date: Thu, 25 Jan 2024 16:34:41 +0100 Subject: [PATCH 23/29] arm64: dts: renesas: Add Renesas R8A779H0 SoC support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add initial support for the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Hai Pham Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/4107bc3d7c31932da29e671ddf4b1564ba38a84c.1706194617.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 121 ++++++++++++++++++++++ 1 file changed, 121 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779h0.dtsi diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi new file mode 100644 index 000000000000..a082e2d06b69 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4M (R8A779H0) SoC + * + * Copyright (C) 2023 Renesas Electronics Corp. + */ + +#include +#include +#include + +/ { + compatible = "renesas,r8a779h0"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a76_0: cpu@0 { + compatible = "arm,cortex-a76"; + reg = <0>; + device_type = "cpu"; + power-domains = <&sysc R8A779H0_PD_A1E0D0C0>; + }; + }; + + extal_clk: extal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + pmu-a76 { + compatible = "arm,cortex-a76-pmu"; + interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a779h0-cpg-mssr"; + reg = <0 0xe6150000 0 0x4000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a779h0-rst"; + reg = <0 0xe6160000 0 0x4000>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a779h0-sysc"; + reg = <0 0xe6180000 0 0x4000>; + #power-domain-cells = <1>; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a779h0", + "renesas,rcar-gen4-hscif", "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 514>, + <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 514>; + status = "disabled"; + }; + + gic: interrupt-controller@f1000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1000000 0 0x20000>, + <0x0 0xf1060000 0 0x110000>; + interrupts = ; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + }; +}; From 0c7a8cbbcee00631aa643b54e67f7245a98f6f8e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 25 Jan 2024 16:34:42 +0100 Subject: [PATCH 24/29] arm64: dts: renesas: Add Gray Hawk Single board support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add initial support for the Renesas Gray Hawk Single board, which is based on the R-Car V4M (R8A779H0) SoC: - Memory, - Crystal oscillators, - Serial console. Based on the White Hawk Single DTS, and on a patch for the Gray Hawk board stack in the BSP by Hai Pham. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/b657402113267acd57aece0b4c681b707e704455.1706194617.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/Makefile | 2 + .../dts/renesas/r8a779h0-gray-hawk-single.dts | 52 +++++++++++++++++++ 2 files changed, 54 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 1d7d69657a1f..4c5ac5f02829 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -89,6 +89,8 @@ dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g0-white-hawk-ard-audio-da7212.dtb dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g2-white-hawk-single.dtb +dtb-$(CONFIG_ARCH_R8A779H0) += r8a779h0-gray-hawk-single.dtb + dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs.dtb r8a779m1-salvator-xs-panel-aa104xd12-dtbs := r8a779m1-salvator-xs.dtb salvator-panel-aa104xd12.dtbo dtb-$(CONFIG_ARCH_R8A77951) += r8a779m1-salvator-xs-panel-aa104xd12.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts new file mode 100644 index 000000000000..1ed404712d82 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the R-Car V4M Gray Hawk Single board + * + * Copyright (C) 2023 Renesas Electronics Corp. + * Copyright (C) 2024 Glider bv + */ + +/dts-v1/; +#include "r8a779h0.dtsi" + +/ { + model = "Renesas Gray Hawk Single board based on r8a779h0"; + compatible = "renesas,gray-hawk-single", "renesas,r8a779h0"; + + aliases { + serial0 = &hscif0; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:921600n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@480000000 { + device_type = "memory"; + reg = <0x4 0x80000000 0x1 0x80000000>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&hscif0 { + uart-has-rtscts; + status = "okay"; +}; + +&scif_clk { + clock-frequency = <24000000>; +}; From 971c17f879352adc719ff215e0769f8e0a49d7c4 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 26 Jan 2024 13:31:14 +0000 Subject: [PATCH 25/29] arm64: dts: renesas: r9a07g043u: Add CSI and CRU nodes Add CSI and CRU nodes r9a07g043 (RZ/G2UL) SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20240126133116.121981-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 69 +++++++++++++++++++++ 1 file changed, 69 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index 2ab231572d95..01d08ebb4a78 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -61,6 +61,75 @@ &soc { interrupt-parent = <&gic>; + cru: video@10830000 { + compatible = "renesas,r9a07g043-cru", "renesas,rzg2l-cru"; + reg = <0 0x10830000 0 0x400>; + clocks = <&cpg CPG_MOD R9A07G043_CRU_VCLK>, + <&cpg CPG_MOD R9A07G043_CRU_PCLK>, + <&cpg CPG_MOD R9A07G043_CRU_ACLK>; + clock-names = "video", "apb", "axi"; + interrupts = , + , + ; + interrupt-names = "image_conv", "image_conv_err", "axi_mst_err"; + resets = <&cpg R9A07G043_CRU_PRESETN>, + <&cpg R9A07G043_CRU_ARESETN>; + reset-names = "presetn", "aresetn"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + crucsi2: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi2cru>; + }; + }; + }; + }; + + csi2: csi2@10830400 { + compatible = "renesas,r9a07g043-csi2", "renesas,rzg2l-csi2"; + reg = <0 0x10830400 0 0xfc00>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_CRU_SYSCLK>, + <&cpg CPG_MOD R9A07G043_CRU_VCLK>, + <&cpg CPG_MOD R9A07G043_CRU_PCLK>; + clock-names = "system", "video", "apb"; + resets = <&cpg R9A07G043_CRU_PRESETN>, + <&cpg R9A07G043_CRU_CMN_RSTB>; + reset-names = "presetn", "cmn-rstb"; + power-domains = <&cpg>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + csi2cru: endpoint@0 { + reg = <0>; + remote-endpoint = <&crucsi2>; + }; + }; + }; + }; + irqc: interrupt-controller@110a0000 { compatible = "renesas,r9a07g043u-irqc", "renesas,rzg2l-irqc"; From c1ff917c88dc5c20084467150e0c852351e3352c Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 15 Jan 2024 14:46:39 +0100 Subject: [PATCH 26/29] ARM: dts: renesas: Improve TMU interrupt descriptions Add the input capture interrupt on Timer Unit instances that have it. Add "interrupt-names" properties for clarity. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/389a18ee2cea96726462c28463cf212330f74ee3.1705325654.git.geert+renesas@glider.be --- arch/arm/boot/dts/renesas/r8a7740.dtsi | 2 ++ arch/arm/boot/dts/renesas/r8a7778.dtsi | 9 +++++++-- arch/arm/boot/dts/renesas/r8a7779.dtsi | 9 +++++++-- 3 files changed, 16 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/renesas/r8a7740.dtsi b/arch/arm/boot/dts/renesas/r8a7740.dtsi index 55884ec701f8..d13ab86c3ab4 100644 --- a/arch/arm/boot/dts/renesas/r8a7740.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7740.dtsi @@ -459,6 +459,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&mstp1_clks R8A7740_CLK_TMU0>; clock-names = "fck"; power-domains = <&pd_a4r>; @@ -474,6 +475,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&mstp1_clks R8A7740_CLK_TMU1>; clock-names = "fck"; power-domains = <&pd_a4r>; diff --git a/arch/arm/boot/dts/renesas/r8a7778.dtsi b/arch/arm/boot/dts/renesas/r8a7778.dtsi index 8d4530ed2fc6..97f71c1f69dd 100644 --- a/arch/arm/boot/dts/renesas/r8a7778.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7778.dtsi @@ -199,7 +199,9 @@ reg = <0xffd80000 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&mstp0_clks R8A7778_CLK_TMU0>; clock-names = "fck"; power-domains = <&cpg_clocks>; @@ -214,7 +216,9 @@ reg = <0xffd81000 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&mstp0_clks R8A7778_CLK_TMU1>; clock-names = "fck"; power-domains = <&cpg_clocks>; @@ -230,6 +234,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&mstp0_clks R8A7778_CLK_TMU2>; clock-names = "fck"; power-domains = <&cpg_clocks>; diff --git a/arch/arm/boot/dts/renesas/r8a7779.dtsi b/arch/arm/boot/dts/renesas/r8a7779.dtsi index 7743af5e2a6f..1944703cba4f 100644 --- a/arch/arm/boot/dts/renesas/r8a7779.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7779.dtsi @@ -402,7 +402,9 @@ reg = <0xffd80000 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&mstp0_clks R8A7779_CLK_TMU0>; clock-names = "fck"; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; @@ -417,7 +419,9 @@ reg = <0xffd81000 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&mstp0_clks R8A7779_CLK_TMU1>; clock-names = "fck"; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; @@ -433,6 +437,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&mstp0_clks R8A7779_CLK_TMU2>; clock-names = "fck"; power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; From c53866cb27fb3a051cb5b6bbeb2e4967bf51c923 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 15 Jan 2024 14:46:40 +0100 Subject: [PATCH 27/29] arm64: dts: renesas: Improve TMU interrupt descriptions Add the input capture interrupt on Timer Unit instances that have it. Add "interrupt-names" properties for clarity. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/5c70ad8c2ea14333616c5add31a4a958f4a47081.1705325654.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 11 +++++++++-- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 11 +++++++++-- arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 11 +++++++++-- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 11 +++++++++-- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 11 +++++++++-- arch/arm64/boot/dts/renesas/r8a77960.dtsi | 11 +++++++++-- arch/arm64/boot/dts/renesas/r8a77961.dtsi | 11 +++++++++-- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 11 +++++++++-- arch/arm64/boot/dts/renesas/r8a77970.dtsi | 11 +++++++++-- arch/arm64/boot/dts/renesas/r8a77980.dtsi | 17 +++++++++++++---- arch/arm64/boot/dts/renesas/r8a77990.dtsi | 11 +++++++++-- arch/arm64/boot/dts/renesas/r8a77995.dtsi | 11 +++++++++-- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 17 +++++++++++++---- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 17 +++++++++++++---- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 17 +++++++++++++---- 15 files changed, 151 insertions(+), 38 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index 95b0a1f6debf..a8a44fe5e83b 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -529,6 +529,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; @@ -541,7 +542,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; @@ -554,7 +557,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; @@ -568,6 +573,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; @@ -581,6 +587,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 786660fcdea4..4fff511e994c 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -413,6 +413,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; @@ -425,7 +426,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; @@ -438,7 +441,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; @@ -452,6 +457,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; @@ -465,6 +471,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index eed94ffed7c1..1ef43d78c3a5 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -384,6 +384,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; @@ -396,7 +397,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; @@ -409,7 +412,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; @@ -423,6 +428,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; @@ -436,6 +442,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 175e5d296da6..be55ae83944c 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -593,6 +593,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; @@ -605,7 +606,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; @@ -618,7 +621,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; @@ -632,6 +637,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; @@ -645,6 +651,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index a4260d9291ba..bea4edd17d53 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -614,6 +614,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -626,7 +627,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -639,7 +642,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -653,6 +658,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -666,6 +672,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index a631ead171b2..7846fea8e40d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -578,6 +578,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -590,7 +591,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -603,7 +606,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -617,6 +622,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -630,6 +636,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; diff --git a/arch/arm64/boot/dts/renesas/r8a77961.dtsi b/arch/arm64/boot/dts/renesas/r8a77961.dtsi index 7254912a241f..58f9286a5ab5 100644 --- a/arch/arm64/boot/dts/renesas/r8a77961.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77961.dtsi @@ -578,6 +578,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; @@ -590,7 +591,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; @@ -603,7 +606,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; @@ -617,6 +622,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; @@ -630,6 +636,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index e57b9027066e..692940662d38 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -449,6 +449,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; @@ -461,7 +462,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; @@ -474,7 +477,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; @@ -488,6 +493,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; @@ -501,6 +507,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A77965_PD_ALWAYS_ON>; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index ed6e2e47c604..d2d3cecc76d5 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -328,6 +328,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; @@ -340,7 +341,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; @@ -353,7 +356,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; @@ -367,6 +372,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; @@ -380,6 +386,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 5ed2daaca1f0..c0ba110c74d6 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -357,6 +357,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; @@ -369,7 +370,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; @@ -382,7 +385,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; @@ -395,7 +400,9 @@ reg = <0 0xe6fe0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; @@ -408,7 +415,9 @@ reg = <0 0xffc00000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 8c2b28342387..37063e3f4e1b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -415,6 +415,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; @@ -427,7 +428,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; @@ -440,7 +443,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; @@ -454,6 +459,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; @@ -467,6 +473,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi index 8cf6473c63d3..89990dd8ebf7 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi @@ -336,6 +336,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 125>; clock-names = "fck"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; @@ -348,7 +349,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; @@ -361,7 +364,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 123>; clock-names = "fck"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; @@ -375,6 +380,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 122>; clock-names = "fck"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; @@ -388,6 +394,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 121>; clock-names = "fck"; power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 4e67a0356497..2f8f2ccab8c2 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -370,6 +370,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 713>; clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -382,7 +383,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 714>; clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -395,7 +398,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 715>; clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -408,7 +413,9 @@ reg = <0 0xe6fe0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 716>; clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; @@ -421,7 +428,9 @@ reg = <0 0xffc00000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 717>; clock-names = "fck"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 7fb4989cce8a..72cf30341fc4 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -501,6 +501,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 713>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; @@ -513,7 +514,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 714>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; @@ -526,7 +529,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 715>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; @@ -539,7 +544,9 @@ reg = <0 0xe6fe0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 716>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; @@ -552,7 +559,9 @@ reg = <0 0xffc00000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 717>; clock-names = "fck"; power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 0c83940b3d8a..7b05b9b3e0a8 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -485,6 +485,7 @@ interrupts = , , ; + interrupt-names = "tuni0", "tuni1", "tuni2"; clocks = <&cpg CPG_MOD 713>; clock-names = "fck"; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; @@ -497,7 +498,9 @@ reg = <0 0xe6fc0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 714>; clock-names = "fck"; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; @@ -510,7 +513,9 @@ reg = <0 0xe6fd0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 715>; clock-names = "fck"; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; @@ -523,7 +528,9 @@ reg = <0 0xe6fe0000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 716>; clock-names = "fck"; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; @@ -536,7 +543,9 @@ reg = <0 0xffc00000 0 0x30>; interrupts = , , - ; + , + ; + interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; clocks = <&cpg CPG_MOD 717>; clock-names = "fck"; power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; From 10c353c7a289a54e19b69d775698bf25ddeac5b8 Mon Sep 17 00:00:00 2001 From: Minh Le Date: Thu, 1 Feb 2024 15:09:16 +0100 Subject: [PATCH 28/29] arm64: dts: renesas: r8a779h0: Add RWDT node Add a device node for the RCLK Watchdog Timer (RWDT) on the Renesas R-Car V4M (R8A779H0) SoC. Signed-off-by: Minh Le Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/43bb03f3baa87b4be8ce953b1955df6b89387e4c.1706790320.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index a082e2d06b69..9ad53e85cf60 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -59,6 +59,17 @@ #size-cells = <2>; ranges; + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a779h0-wdt", + "renesas,rcar-gen4-wdt"; + reg = <0 0xe6020000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; + resets = <&cpg 907>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a779h0-cpg-mssr"; reg = <0 0xe6150000 0 0x4000>; From 785b3c25761a828c5e22b3361541c50fd3b92fde Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 1 Feb 2024 15:09:17 +0100 Subject: [PATCH 29/29] arm64: dts: renesas: gray-hawk-single: Enable watchdog timer Enable the watchdog timer on the Gray Hawk Single board. Signed-off-by: Geert Uytterhoeven Reviewed-by: Wolfram Sang Link: https://lore.kernel.org/r/cf6effafd9e0472a457eed9d84a834abc3e1c833.1706790320.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts index 1ed404712d82..e04de1d74825 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts @@ -47,6 +47,11 @@ status = "okay"; }; +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + &scif_clk { clock-frequency = <24000000>; };