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x86/cpu: Add new VMX feature, Tertiary VM-Execution control
A new 64-bit control field "tertiary processor-based VM-execution controls", is defined [1]. It's controlled by bit 17 of the primary processor-based VM-execution controls. Different from its brother VM-execution fields, this tertiary VM- execution controls field is 64 bit. So it occupies 2 vmx_feature_leafs, TERTIARY_CTLS_LOW and TERTIARY_CTLS_HIGH. Its companion VMX capability reporting MSR,MSR_IA32_VMX_PROCBASED_CTLS3 (0x492), is also semantically different from its brothers, whose 64 bits consist of all allow-1, rather than 32-bit allow-0 and 32-bit allow-1 [1][2]. Therefore, its init_vmx_capabilities() is a little different from others. [1] ISE 6.2 "VMCS Changes" https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html [2] SDM Vol3. Appendix A.3 Reviewed-by: Sean Christopherson <seanjc@google.com> Reviewed-by: Maxim Levitsky <mlevitsk@redhat.com> Signed-off-by: Robert Hoo <robert.hu@linux.intel.com> Signed-off-by: Zeng Guang <guang.zeng@intel.com> Message-Id: <20220419153240.11549-1-guang.zeng@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -980,6 +980,7 @@
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#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
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#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
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#define MSR_IA32_VMX_VMFUNC 0x00000491
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#define MSR_IA32_VMX_PROCBASED_CTLS3 0x00000492
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/* VMX_BASIC bits and bitmasks */
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#define VMX_BASIC_VMCS_SIZE_SHIFT 32
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@ -5,7 +5,7 @@
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/*
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* Defines VMX CPU feature bits
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*/
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#define NVMXINTS 3 /* N 32-bit words worth of info */
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#define NVMXINTS 5 /* N 32-bit words worth of info */
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/*
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* Note: If the comment begins with a quoted string, that string is used
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@ -43,6 +43,7 @@
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#define VMX_FEATURE_RDTSC_EXITING ( 1*32+ 12) /* "" VM-Exit on RDTSC */
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#define VMX_FEATURE_CR3_LOAD_EXITING ( 1*32+ 15) /* "" VM-Exit on writes to CR3 */
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#define VMX_FEATURE_CR3_STORE_EXITING ( 1*32+ 16) /* "" VM-Exit on reads from CR3 */
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#define VMX_FEATURE_TERTIARY_CONTROLS ( 1*32+ 17) /* "" Enable Tertiary VM-Execution Controls */
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#define VMX_FEATURE_CR8_LOAD_EXITING ( 1*32+ 19) /* "" VM-Exit on writes to CR8 */
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#define VMX_FEATURE_CR8_STORE_EXITING ( 1*32+ 20) /* "" VM-Exit on reads from CR8 */
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#define VMX_FEATURE_VIRTUAL_TPR ( 1*32+ 21) /* "vtpr" TPR virtualization, a.k.a. TPR shadow */
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@ -15,6 +15,8 @@ enum vmx_feature_leafs {
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MISC_FEATURES = 0,
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PRIMARY_CTLS,
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SECONDARY_CTLS,
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TERTIARY_CTLS_LOW,
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TERTIARY_CTLS_HIGH,
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NR_VMX_FEATURE_WORDS,
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};
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@ -22,7 +24,7 @@ enum vmx_feature_leafs {
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static void init_vmx_capabilities(struct cpuinfo_x86 *c)
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{
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u32 supported, funcs, ept, vpid, ign;
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u32 supported, funcs, ept, vpid, ign, low, high;
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BUILD_BUG_ON(NVMXINTS != NR_VMX_FEATURE_WORDS);
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@ -42,6 +44,11 @@ static void init_vmx_capabilities(struct cpuinfo_x86 *c)
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rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS2, &ign, &supported);
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c->vmx_capability[SECONDARY_CTLS] = supported;
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/* All 64 bits of tertiary controls MSR are allowed-1 settings. */
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rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS3, &low, &high);
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c->vmx_capability[TERTIARY_CTLS_LOW] = low;
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c->vmx_capability[TERTIARY_CTLS_HIGH] = high;
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rdmsr(MSR_IA32_VMX_PINBASED_CTLS, ign, supported);
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rdmsr_safe(MSR_IA32_VMX_VMFUNC, &ign, &funcs);
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