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Merge branch 'drm-intel-fixes' into drm-intel-next
This commit is contained in:
commit
46168f3936
@ -1269,6 +1269,7 @@ extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_ove
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#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
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#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
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#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
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#define PRIMARY_RINGBUFFER_SIZE (128*1024)
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@ -862,8 +862,10 @@ int i915_restore_state(struct drm_device *dev)
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/* Clock gating state */
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intel_init_clock_gating(dev);
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if (HAS_PCH_SPLIT(dev))
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if (HAS_PCH_SPLIT(dev)) {
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ironlake_enable_drps(dev);
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intel_init_emon(dev);
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}
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/* Cache mode state */
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I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
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@ -1683,6 +1683,37 @@ static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
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udelay(500);
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}
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static void intel_fdi_normal_train(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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u32 reg, temp;
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/* enable normal train */
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reg = FDI_TX_CTL(pipe);
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temp = I915_READ(reg);
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temp &= ~FDI_LINK_TRAIN_NONE;
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temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
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I915_WRITE(reg, temp);
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reg = FDI_RX_CTL(pipe);
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temp = I915_READ(reg);
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if (HAS_PCH_CPT(dev)) {
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temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
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temp |= FDI_LINK_TRAIN_NORMAL_CPT;
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} else {
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temp &= ~FDI_LINK_TRAIN_NONE;
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temp |= FDI_LINK_TRAIN_NONE;
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}
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I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
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/* wait one idle pattern time */
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POSTING_READ(reg);
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udelay(1000);
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}
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/* The FDI link training functions for ILK/Ibexpeak. */
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static void ironlake_fdi_link_train(struct drm_crtc *crtc)
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{
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@ -1769,27 +1800,6 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
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DRM_DEBUG_KMS("FDI train done\n");
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/* enable normal train */
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reg = FDI_TX_CTL(pipe);
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temp = I915_READ(reg);
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temp &= ~FDI_LINK_TRAIN_NONE;
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temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
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I915_WRITE(reg, temp);
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reg = FDI_RX_CTL(pipe);
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temp = I915_READ(reg);
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if (HAS_PCH_CPT(dev)) {
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temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
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temp |= FDI_LINK_TRAIN_NORMAL_CPT;
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} else {
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temp &= ~FDI_LINK_TRAIN_NONE;
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temp |= FDI_LINK_TRAIN_NONE;
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}
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I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
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/* wait one idle pattern time */
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POSTING_READ(reg);
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udelay(1000);
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}
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static const int const snb_b_fdi_train_param [] = {
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@ -2092,6 +2102,8 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
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I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
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I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
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intel_fdi_normal_train(crtc);
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/* For PCH DP, enable TRANS_DP_CTL */
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if (HAS_PCH_CPT(dev) &&
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intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
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@ -2202,9 +2214,10 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
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udelay(100);
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/* Ironlake workaround, disable clock pointer after downing FDI */
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I915_WRITE(FDI_RX_CHICKEN(pipe),
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I915_READ(FDI_RX_CHICKEN(pipe) &
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~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
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if (HAS_PCH_IBX(dev))
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I915_WRITE(FDI_RX_CHICKEN(pipe),
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I915_READ(FDI_RX_CHICKEN(pipe) &
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~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
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/* still set train pattern 1 */
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reg = FDI_TX_CTL(pipe);
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@ -296,6 +296,7 @@ extern void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
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extern void intel_init_clock_gating(struct drm_device *dev);
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extern void ironlake_enable_drps(struct drm_device *dev);
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extern void ironlake_disable_drps(struct drm_device *dev);
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extern void intel_init_emon(struct drm_device *dev);
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extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
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struct drm_gem_object *obj,
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