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ARM: Merge next-s3c6410-andygreen

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Merge branch 'next-s3c6410-andygreen' into next-samsung-try5
This commit is contained in:
Ben Dooks 2010-01-19 17:42:25 +09:00
commit 44d6cef805
4 changed files with 113 additions and 2 deletions
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14
arch/arm/mach-s3c6400/include/mach/map.h
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@ -17,6 +17,18 @@
#include <plat/map-base.h>
/*
* Post-mux Chip Select Regions Xm0CSn_
* These may be used by SROM, NAND or CF depending on settings
*/
#define S3C64XX_PA_XM0CSN0 (0x10000000)
#define S3C64XX_PA_XM0CSN1 (0x18000000)
#define S3C64XX_PA_XM0CSN2 (0x20000000)
#define S3C64XX_PA_XM0CSN3 (0x28000000)
#define S3C64XX_PA_XM0CSN4 (0x30000000)
#define S3C64XX_PA_XM0CSN5 (0x38000000)
/* HSMMC units */
#define S3C64XX_PA_HSMMC(x) (0x7C200000 + ((x) * 0x100000))
#define S3C64XX_PA_HSMMC0 S3C64XX_PA_HSMMC(0)
@ -38,6 +50,8 @@
#define S3C_VA_UART2 S3C_VA_UARTx(2)
#define S3C_VA_UART3 S3C_VA_UARTx(3)
#define S3C64XX_PA_SROM (0x70000000)
#define S3C64XX_PA_NAND (0x70200000)
#define S3C64XX_PA_FB (0x77100000)
#define S3C64XX_PA_USB_HSOTG (0x7C000000)

37
arch/arm/mach-s3c6410/mach-smdk6410.c
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@ -49,6 +49,7 @@
#include <plat/regs-modem.h>
#include <plat/regs-gpio.h>
#include <plat/regs-sys.h>
#include <plat/regs-srom.h>
#include <plat/iic.h>
#include <plat/fb.h>
#include <plat/gpio-cfg.h>
@ -154,10 +155,20 @@ static struct s3c_fb_platdata smdk6410_lcd_pdata __initdata = {
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
};
/*
* Configuring Ethernet on SMDK6410
*
* Both CS8900A and LAN9115 chips share one chip select mediated by CFG6.
* The constant address below corresponds to nCS1
*
* 1) Set CFGB2 p3 ON others off, no other CFGB selects "ethernet"
* 2) CFG6 needs to be switched to "LAN9115" side
*/
static struct resource smdk6410_smsc911x_resources[] = {
[0] = {
.start = 0x18000000,
.end = 0x18000000 + SZ_64K - 1,
.start = S3C64XX_PA_XM0CSN1,
.end = S3C64XX_PA_XM0CSN1 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
@ -430,10 +441,32 @@ static void __init smdk6410_map_io(void)
static void __init smdk6410_machine_init(void)
{
u32 cs1;
s3c_i2c0_set_platdata(NULL);
s3c_i2c1_set_platdata(NULL);
s3c_fb_set_platdata(&smdk6410_lcd_pdata);
/* configure nCS1 width to 16 bits */
cs1 = __raw_readl(S3C64XX_SROM_BW) &
~(S3C64XX_SROM_BW__CS_MASK << S3C64XX_SROM_BW__NCS1__SHIFT);
cs1 |= ((1 << S3C64XX_SROM_BW__DATAWIDTH__SHIFT) |
(1 << S3C64XX_SROM_BW__WAITENABLE__SHIFT) |
(1 << S3C64XX_SROM_BW__BYTEENABLE__SHIFT)) <<
S3C64XX_SROM_BW__NCS1__SHIFT;
__raw_writel(cs1, S3C64XX_SROM_BW);
/* set timing for nCS1 suitable for ethernet chip */
__raw_writel((0 << S3C64XX_SROM_BCX__PMC__SHIFT) |
(6 << S3C64XX_SROM_BCX__TACP__SHIFT) |
(4 << S3C64XX_SROM_BCX__TCAH__SHIFT) |
(1 << S3C64XX_SROM_BCX__TCOH__SHIFT) |
(0xe << S3C64XX_SROM_BCX__TACC__SHIFT) |
(4 << S3C64XX_SROM_BCX__TCOS__SHIFT) |
(0 << S3C64XX_SROM_BCX__TACS__SHIFT), S3C64XX_SROM_BC1);
gpio_request(S3C64XX_GPN(5), "LCD power");
gpio_request(S3C64XX_GPF(13), "LCD power");
gpio_request(S3C64XX_GPF(15), "LCD power");

5
arch/arm/plat-s3c64xx/cpu.c
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@ -72,6 +72,11 @@ static struct map_desc s3c_iodesc[] __initdata = {
.pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)S3C_VA_MEM,
.pfn = __phys_to_pfn(S3C64XX_PA_SROM),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = (unsigned long)(S3C_VA_UART + UART_OFFS),
.pfn = __phys_to_pfn(S3C_PA_UART),

59
arch/arm/plat-s3c64xx/include/plat/regs-srom.h Normal file
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@ -0,0 +1,59 @@
/* arch/arm/plat-s3c64xx/include/plat/regs-srom.h
*
* Copyright 2009 Andy Green <andy@warmcat.com>
*
* S3C64XX SROM definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __PLAT_REGS_SROM_H
#define __PLAT_REGS_SROM_H __FILE__
#define S3C64XX_SROMREG(x) (S3C_VA_MEM + (x))
#define S3C64XX_SROM_BW S3C64XX_SROMREG(0)
#define S3C64XX_SROM_BC0 S3C64XX_SROMREG(4)
#define S3C64XX_SROM_BC1 S3C64XX_SROMREG(8)
#define S3C64XX_SROM_BC2 S3C64XX_SROMREG(0xc)
#define S3C64XX_SROM_BC3 S3C64XX_SROMREG(0x10)
#define S3C64XX_SROM_BC4 S3C64XX_SROMREG(0x14)
#define S3C64XX_SROM_BC5 S3C64XX_SROMREG(0x18)
/*
* one register BW holds 5 x 4-bit packed settings for NCS0 - NCS4
*/
#define S3C64XX_SROM_BW__DATAWIDTH__SHIFT 0
#define S3C64XX_SROM_BW__WAITENABLE__SHIFT 2
#define S3C64XX_SROM_BW__BYTEENABLE__SHIFT 3
#define S3C64XX_SROM_BW__CS_MASK 0xf
#define S3C64XX_SROM_BW__NCS0__SHIFT 0
#define S3C64XX_SROM_BW__NCS1__SHIFT 4
#define S3C64XX_SROM_BW__NCS2__SHIFT 8
#define S3C64XX_SROM_BW__NCS3__SHIFT 0xc
#define S3C64XX_SROM_BW__NCS4__SHIFT 0x10
/*
* applies to same to BCS0 - BCS4
*/
#define S3C64XX_SROM_BCX__PMC__SHIFT 0
#define S3C64XX_SROM_BCX__PMC__MASK 3
#define S3C64XX_SROM_BCX__TACP__SHIFT 4
#define S3C64XX_SROM_BCX__TACP__MASK 0xf
#define S3C64XX_SROM_BCX__TCAH__SHIFT 8
#define S3C64XX_SROM_BCX__TCAH__MASK 0xf
#define S3C64XX_SROM_BCX__TCOH__SHIFT 12
#define S3C64XX_SROM_BCX__TCOH__MASK 0xf
#define S3C64XX_SROM_BCX__TACC__SHIFT 16
#define S3C64XX_SROM_BCX__TACC__MASK 0x1f
#define S3C64XX_SROM_BCX__TCOS__SHIFT 24
#define S3C64XX_SROM_BCX__TCOS__MASK 0xf
#define S3C64XX_SROM_BCX__TACS__SHIFT 28
#define S3C64XX_SROM_BCX__TACS__MASK 0xf
#endif /* _PLAT_REGS_SROM_H */